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* arm64: zynqmp: Disable bootelf and fdt commands for mini configurationsMichal Simek2018-11-262-0/+4
| | | | | | | | | | | | | There is no reason to enable these commands for mini configurations. It saves some space: aarch64: (for 2/2 boards) all -19076.0 bss -1048.0 data -1720.0 rodata -3840.0 text -12468.0 xilinx_zynqmp_mini_emmc1: all -19076 bss -1048 data -1720 rodata -3840 text -12468 xilinx_zynqmp_mini_emmc0: all -19076 bss -1048 data -1720 rodata -3840 text -12468 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM: zynq: cse: Shrink u-boot sizeMichal Simek2018-11-262-0/+6
| | | | | | | | | U-Boot is growing that's why not needed features can be disabled: - CMDLINE_EDITING - AUTO_COMPLETE - SYS_LONGHELP Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM: zynq: cse: Disable autoboot featureMichal Simek2018-11-263-1/+3
| | | | | | | Intention of CSE targets is not boot anything that's why also bootdelay is not necessary Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM: zynq: cse: Disable distro bootcommandsMichal Simek2018-11-261-3/+3
| | | | | | | | | | | cse targets shouldn't never have distro default enabled because these targets are not designed for booting images. It was enabled by: "configs: Re-sync with CONFIG_DISTRO_DEFAULTS" (sha1: fa2c14676c7c6f3115dd4d9b2a4cc3b35c3ad2a2) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM: zynq: Guard zynq_help_text with CONFIG_SYS_LONGHELPMichal Simek2018-11-261-0/+2
| | | | | | | | | | If SYS_LONGHELP is disabled the following warning is generated: board/xilinx/zynq/cmds.c:496:13: warning: ‘zynq_help_text’ defined but not used [-Wunused-variable] Normal way for fixing this is to guard the whole variable. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* mtd: nand: Arasan: Add subpage configuration supportMartin Lund2018-11-261-0/+4
| | | | | | | | | | | | | | | | Add support for disabling subpage write support via CONFIG_SYS_NAND_NO_SUBPAGE_WRITE. Currently the Linux Arasan driver does not support subpage writes and in case of running UBI and accessing the same UBI volume from both U-Boot and Linux it is required to have the same subpage write configuration else the location of the UBI headers (EC + VID) will be misaligned (subpage vs page) and incompatible. Hence the need for disabling subpage write support in the U-Boot Arasan NAND driver. Signed-off-by: Martin Lund <malu@gomspace.com> Acked-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm: zynq: cse_qspi: Fix overwriting spi-rx-bus-width propertySiva Durga Prasad Paladugu2018-11-262-2/+2
| | | | | | | | | spi-rx-bus-width property is part of flash, so it should be moved to flash node from qspi node. This patch fixes the incorrect read of spi-rx-bus-width property by moving it to flash node. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Fix logic in CG/EG/EV detectionSiva Durga Prasad Paladugu2018-11-261-11/+37
| | | | | | | | | | | | | The VCU disable bit(8) in IP disable register of efuse is valid only if PL powered up and hence PL powerup status has to be considered while determining the CG part also. This patch considers the PL powerup status and ignores the VCU disable bit if PL not powered up. This fixes the issue of "unknown" id for CG parts if PL not powered up and VCU bit(8) is not set. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Enable SPL gzip support for zcu102 and zcu100Michal Simek2018-11-263-0/+3
| | | | Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Merge tag 'pull-tg18' of git://git.denx.de/u-boot-dmTom Rini2018-11-2352-148/+909
|\ | | | | | | | | | | Various minor sandbox improvements Better buildman warning handling Misc other things
| * sf: Add a method to obtain the block-protect settingSimon Glass2018-11-208-0/+86
| | | | | | | | | | | | | | | | | | It is useful to obtain the block-protect setting of the SPI flash, so we know whether it is fully open or (perhaps partially) write-protected. Add a method for this. Update the sandbox driver to process this operation and add a test. Signed-off-by: Simon Glass <sjg@chromium.org>
| * test: sf: Add a simple SPI flash testSimon Glass2018-11-201-2/+44
| | | | | | | | | | | | | | | | | | | | | | The current test is a functional test, covering all the way from the command line to the sandbox SPI driver. This is useful, but it is easier to diagnose failures with a smaller test. Add a simple test which reads and writes data and checks that it is stored and retrieved correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
| * misc: Update read() and write() methods to return bytes xferedSimon Glass2018-11-208-15/+27
| | | | | | | | | | | | | | | | | | | | | | At present these functions return 0 on success. For some devices we want to know how many bytes were transferred. It seems useful to adjust the API to be more like the POSIX read() and write() functions. Update these two methods, a test and all users. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
| * string: Include the config headerSimon Glass2018-11-201-0/+1
| | | | | | | | | | | | | | At present the config header is not included in this file, but it does use a CONFIG option. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * video: Update video_set_default_colors() to support invertSimon Glass2018-11-203-11/+23
| | | | | | | | | | | | | | | | | | | | | | | | It is useful to be able to invert the colours in some cases so that the text matches the background colour. Add a parameter to the function to support this. It is strange that function takes a private data structure from another driver as an argument. It seems better to pass the device and have the function internally work out how to find its required information. Signed-off-by: Simon Glass <sjg@chromium.org>
| * binman: Set the pathname correctly for ELF filesSimon Glass2018-11-201-3/+2
| | | | | | | | | | | | | | At present, stripped files don't have the right pathname which means that blob compression cannot be used. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * binman: Drop an unnecessary comma in blob handlingSimon Glass2018-11-201-1/+1
| | | | | | | | | | | | This comma is not needed. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * binman: Add a way to enable debugging from the buildSimon Glass2018-11-202-2/+10
| | | | | | | | | | | | | | | | | | When the build fails due to something wrong in binman it is sometimes useful to get a full backtrace showing the location of the failure. Add a BINMAN_DEBUG environment variable to support this along with some documentation. Signed-off-by: Simon Glass <sjg@chromium.org>
| * spl: lz4: Allow use of lz4 compression in SPLSimon Glass2018-11-202-1/+9
| | | | | | | | | | | | | | | | In some cases U-Boot is compressed and it is useful to be able to decompress it in SPL. Add a Kconfig and Makefile change to allow this. Note that this does not actually implement decompression. Signed-off-by: Simon Glass <sjg@chromium.org>
| * spl: Support bootstage, log, hash and early malloc in TPLSimon Glass2018-11-202-3/+42
| | | | | | | | | | | | | | | | | | At present these features are supported in SPL but not TPL. Update the Kconfig and Makefile to allow this. Also add a few Makefile comments to make earier to track what is going on. Signed-off-by: Simon Glass <sjg@chromium.org>
| * sandbox: Update some drivers to work in SPL/TPLSimon Glass2018-11-201-0/+15
| | | | | | | | | | | | | | | | At present sandbox drivers are mostly not used before relocation. Some of these are needed by Chromium OS verified boot, since it uses sandbox TPL, so update them accordingly. Signed-off-by: Simon Glass <sjg@chromium.org>
| * sandbox: cros_ec: exynos: Drop use of cros_ec_get_error()Simon Glass2018-11-203-19/+12
| | | | | | | | | | | | | | | | This function is really just a call to uclass_get_device() and there is no reason why the caller cannot do it. Update sandbox and snow accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
| * sandbox: Add a function to read a host fileSimon Glass2018-11-202-3/+55
| | | | | | | | | | | | | | | | Add a way to read a file from the host filesystem. This can be useful for reading test data, for example. Also fix up the writing function which was not the right version, and drop the debugging lines. Signed-off-by: Simon Glass <sjg@chromium.org>
| * sandbox: log: Add a category for sandboxSimon Glass2018-11-201-0/+1
| | | | | | | | | | | | | | It seems useful to make sandbox its own log category since it is used for so much testing. Add this as a new category. Signed-off-by: Simon Glass <sjg@chromium.org>
| * sandbox: tpm: Allow debugging of data packagesSimon Glass2018-11-201-0/+6
| | | | | | | | | | | | | | This is not normally useful, so change the code to avoid writing out every data package. This can be enabled with #define DEBUG. Signed-off-by: Simon Glass <sjg@chromium.org>
| * cros_ec: Add new features for events and powerSimon Glass2018-11-203-7/+429
| | | | | | | | | | | | | | This adds new commands to the EC related to setting and clearing events as well as controlling power-related settings. Signed-off-by: Simon Glass <sjg@chromium.org>
| * cros_ec: Align uclass data to a cache boundarySimon Glass2018-11-201-0/+1
| | | | | | | | | | | | | | The LPC driver expects its buffer to be word-aligned. Add the required flag to the uclass driver to ensure this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * cros_ec: Fail if we cannot determine the flash burst sizeSimon Glass2018-11-201-0/+3
| | | | | | | | | | | | | | This value is required for flashing to work correctly. Add a check for it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * cros_ec: Add error logging on a few commandsSimon Glass2018-11-201-2/+9
| | | | | | | | | | | | Add some more logging to provide more information on failures. Signed-off-by: Simon Glass <sjg@chromium.org>
| * cros_ec: Use uint instead of u8 for parametersSimon Glass2018-11-201-6/+4
| | | | | | | | | | | | | | | | | | There is no advantage to using a u8 for function parameters. It forces the compiler to mask values and can increase code size. Also the command enum has been extended to 16 bits. Update the functions to use uint instead. Signed-off-by: Simon Glass <sjg@chromium.org>
| * buildman: Show boards with warning with w+Simon Glass2018-11-202-19/+54
| | | | | | | | | | | | | | | | At present we should boards with warnings in the same way as those with errors. This is not ideal. Add a new 'warn' state and show these listed in yellow to match the actual warning lines printing with -e. Signed-off-by: Simon Glass <sjg@chromium.org>
| * buildman: Rename the good, better, worse variablesSimon Glass2018-11-201-14/+14
| | | | | | | | | | | | | | | | | | | | At present we don't distinguish between errors and warnings when printing the architecture summary. Rename the variables to better describe their purpose. 'Worse' at present means we got an error, so use that as the name. Signed-off-by: Simon Glass <sjg@chromium.org>
| * buildman: Detect dtc warningsSimon Glass2018-11-202-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | At present messages from the device-tree compiler like this: arch/arm/dts/socfpga_arria10_socdk_sdmmc.dtb: Warning (avoid_unnecessary_addr_size): /clocks: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property are detected as errors since they don't match the gcc warning regex. Add a new one for dtc to fix this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * buildman: Only print toolchain probing with -vSimon Glass2018-11-202-2/+2
| | | | | | | | | | | | | | | | | | At present --list-tool-chains prints a lot of information about the toolchain-probing process. This is generally not very interesting. Update buildman to print this only if --list-tool-chains is given with -v. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: spi: prevent setting a speed of 0 HzSimon Goldschmidt2018-11-201-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When the device tree is missing a correct spi slave description below the bus (compatible "spi-flash" or spi-max-frequency are missing), the 'set_speed' callback can be called with 'speed' == 0 Hz. At least with cadence qspi, this leads to a division by zero. Prevent this by initializing speed to 100 kHz in this case (same fallback value as is done in 'dm_spi_claim_bus') and issue a warning to console. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * fdt: restore board_fdt_blob_setup() declarationBaruch Siach2018-11-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Commit 90c08fa038451d (fdt: Add device tree memory bindings) removed the prototype declaration of board_fdt_blob_setup(), most likely by mistake. This didn't break the build because the only file calling this function (lib/fdtdec.c) provides a local weak definition. Restore the declaration. Cc: Michael Pratt <mpratt@chromium.org> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Simon Glass <sjg@chromium.org>
| * cmd: fdt: Fix fdt address information after the movementHiroyuki Yokoyama2018-11-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the address information of fdt. wrong case: => fdt addr 0x48000000 => fdt move 0x48000000 0x41000000 0xa000 => fdt addr The address of the fdt is 48000000 Active address in this case is 0x41000000. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * fdt: Fix uncompress_blob() for U-Boot properMarek Vasut2018-11-201-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When U-Boot proper is compiled with CONFIG_MULTI_DTB_FIT and tries to call uncompress_blob(), it fails with -ENOTSUPP. This is because the full implementation of this function which includes compression is available only in SPL. In U-Boot proper or if the compression is not enabled, the blob is not compressed and thus can be passed to locate_dtb_in_fit() in fdtdec_setup() without any changes. Pass the blob without any changes if compression is not enabled instead of failing. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * dm: core: Widen the dump tree to show more of the driver's name.Liviu Dudau2018-11-202-18/+18
| | | | | | | | | | | | | | | | | | | | | | With drivers that have prefix names that are quite long (like 'versatile_') it is useful to have a wider column for the driver's name when dumping the device driver tree. Also update the tests to take into account the wider output format. Signed-off-by: Liviu Dudau <liviu.dudau@foss.arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * sandbox: README: use setenv ethrotate noHeinrich Schuchardt2018-11-201-0/+4
| | | | | | | | | | | | | | | | | | If we want to control which network interface is actually used, we have to issue 'setenv ethrotate no'. If ethrotate is not set any interface may be used. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * sandbox: README: setting environment variablesHeinrich Schuchardt2018-11-201-8/+8
| | | | | | | | | | | | | | The command to set environment variables is setenv. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * sandbox: remove stray DEBUGHeinrich Schuchardt2018-11-201-4/+4
| | | | | | | | | | | | | | | | | | DEBUG should not be defined in production code. Change printf() to debug() where this writes a debug message. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * dm/pci: Change the first CFG read to Vendor ID in enumerationHou Zhiqiang2018-11-201-4/+7
|/ | | | | | | | | | | As the PCIe specification recommend reading the Vendor ID register to determine if a Function is present, read the Vendor ID of a non-existent Function must not result in system error, so we'd better make the first CFG read to Vendor ID instead of Header Type register in the PCIe enumeration. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge git://git.denx.de/u-boot-marvellTom Rini2018-11-2014-31/+466
|\ | | | | | | | | | | - Clearfog GT-8K support added by Baruch / Raheeb - const and sizes cleanup (also in MIPS) from Baruch - Minor cleanup to db-88f6820 from Chris
| * ARM: mvebu: dts: add Clearfog GT-8KRabeeh Khoury2018-11-203-0/+391
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The SolidRun Clearfog GT-8K is based on Armada 8040. https://wiki.solid-run.com/doku.php?id=products:a8040:clearfoggt8k The config file is identical to the Macchiatobin one (mvebu_mcbin-88f8040_defconfig) with only the default device-tree changed. Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
| * ARM: mvebu: db-88f6820: remove redundant commentChris Packham2018-11-202-10/+0
| | | | | | | | | | | | | | | | After migration to Kconfig the comment about TEXT_BASE has become redundant. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm64: mvebu: a8k: autodetect RAM sizeBaruch Siach2018-11-201-1/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some Armada 8K boards like Macchiatobin and Clearfog GT-8K use RAM from external DIMM. Hard coding the RAM size in the device-tree is not convenient. Fortunately, the ATF that initializes the RAM knows the size of RAM, and U-Boot can query the ATF using a SMC call. The ATF maps the lower 3G of RAM starting at address 0. Higher RAM is mapped at 4G. This leaves a 1G hole between 3G and 4G for IO peripherals. Use a second bi_dram[] entry to describe the higher RAM area. As a result, CONFIG_NR_DRAM_BANKS must be set to 2 to use more than 3GB RAM. This code in this commit is mostly taken from downstream Marvell U-Boot code by Grzegorz Jaszczyk. Cc: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
| * linux/sizes.h: sync from kernelBaruch Siach2018-11-202-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The kernel added SZ_4G macro in commit f2b9ba871b (arm64/kernel: kaslr: reduce module randomization range to 4 GB). Include linux/const.h for the _AC macro. Drop a local SZ_4G definition in tegra code. Cc: Tom Warren <twarren@nvidia.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
| * MIPS: drop asm/const.hBaruch Siach2018-11-201-27/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit 86f21c96f467368 (mips: Use common _AC macro now.) removed the _AC definition from const.h. All other macros defined in const.h are not used anywhere, and there is now no user of this header. Remove this header. Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * Use _AC and UL macros from linux/const.hBaruch Siach2018-11-204-10/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Drop the _AC and UL macros from common.h. Linux headers is the original source of this macro, so keep its definition in the same header. Update existing users of these macros to include const.h directly. Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Rick Chen <rick@andestech.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
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