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* configs: enable use of DT for all m68k boardsAngelo Dureghello2019-05-2446-0/+46
| | | | | | | Enable DT usage for all m68k boards. To provide a working single binary, the dts has been kept as embedded. Signed-off-by: Angelo Dureghello <angelo@sysam.it>
* m68k: enabling long jumps on mcf54x5 SoCsAngelo Dureghello2019-05-241-2/+4
| | | | | | | Growing of binary size asks for long assembly jumps. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Angelo Dureghello <angelo@sysam.it>
* m68k: add initial dts files for all m68k boardsAngelo Dureghello2019-05-2451-0/+1069
| | | | | | | | | This patch adds basic dts files for all the m68k boards. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Angelo Dureghello <angelo@sysam.it> [trini: Add CONFIG_TARGET_M5329EVB dtbs and update M5329EVB defconfigs] Signed-off-by: Tom Rini <trini@konsulko.com>
* m68k: architecture changes to support fdtAngelo Dureghello2019-05-232-2/+37
| | | | | | | This patch adds fdt support to the m68k architecture. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Angelo Dureghello <angelo@sysam.it>
* m68k: add basic set of devicetreesAngelo Dureghello2019-05-2318-0/+763
| | | | | | | | | | | This patch adds a basic group of devicetrees, one for each cpu family, including actually just uart and dspi devices, since these are the drivers supporting devicetree (support added in this patch-set). Acked-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Angelo Dureghello <angelo@sysam.it> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* Merge tag 'dm-pull-22may19' of git://git.denx.de/u-boot-dmTom Rini2019-05-2211-47/+151
|\ | | | | | | | | Various DM fixes Addition of ofnode_get_addr_size_index()
| * dm: core: Fix dm_extended_scan_fdt()Patrice Chotard2019-05-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | This function takes an argument, blob, but never uses it, instead uses gd->fdt_blob directly. Fixes: e81c98649b7a ("dm: core: add clocks node scan") Reported-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * core: ofnode: Have ofnode_read_u32_default return a u32Trent Piepho2019-05-212-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | It was returning an int, which doesn't work if the u32 it is reading, or the default value, will overflow a signed int. While it could be made to work, when using a C standard/compiler where casting negative signed values to unsigned has a defined behavior, combined with careful casting, it seems obvious one is meant to use ofnode_read_s32_default() with signed values. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Trent Piepho <tpiepho@impinj.com>
| * buildman: Deal more nicely with invalid build-status fileSimon Glass2019-05-211-1/+6
| | | | | | | | | | | | | | | | | | | | The 'done' files created by buildman may end up being empty if buildman runs out of disk space while writing them. At present buildman dies with an exception when using -s to check the build status. Fix this. Seriesl-cc: trini Signed-off-by: Simon Glass <sjg@chromium.org>
| * core: ofnode: Add ofnode_get_addr_size_indexKeerthy2019-05-212-3/+24
| | | | | | | | | | | | | | | | Add ofnode_get_addr_size_index function to fetch the address and size of the reg space based on index. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * common: fdt_support: Check mtdparts cell sizeStefan Mavrodiev2019-05-211-9/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When using fdt_fixup_mtdparts() offset and length cell sizes are limited to 4 bytes (1 cell). However if the mtd device is bigger then 4GiB, then #address-cells and #size-cells are 8 bytes (2 cells) [1]. This patch read #size-cells and uses either fdt32_t or fdt64_t cell size. The default is fdt32_t. [1] Documentation/devicetree/bindings/mtd/partition.txt Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * fdtdec: Remove fdt_{addr,size}_unpack()Thierry Reding2019-05-213-28/+12
| | | | | | | | | | | | | | U-Boot already defines the {upper,lower}_32_bits() macros that have the same purpose. Use the existing macros instead of defining new APIs. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * Add an empty stdint.h fileSimon Glass2019-05-211-0/+7
| | | | | | | | | | | | | | | | | | Some libraries build by U-Boot may include stdint.h. This is not used by U-Boot itself and causes conflicts with the types defined in linux/types.h. To work around this, add an empty file with this name so that it will be used in preference to the compiler version. Signed-off-by: Simon Glass <sjg@chromium.org>
| * spl: misc: Allow misc drivers in SPL and TPLSimon Glass2019-05-212-3/+77
| | | | | | | | | | | | | | | | In some cases it is necessary to read the keyboard in early phases of U-Boot. The cros_ec keyboard is kept in the misc directory. Update the config to allow this. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2019-05-2286-65/+3308
|\ \ | |/ |/| | | | | | | | | | | | | Changes from rc2 tag - Support PCIe Gen4 driver of the Mobiveil IP - NXP LS1028A SoC and platform support - Few SPI related config updates - Distinguish the ecc val by chassis version and move the ecc addr to dts - sp805 watchdog support
| * armv8: lx2160: Drop useless CONFIG_CMDLINE_EDITING from config.hAndy Shevchenko2019-05-221-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | commit 58c3e62040be ("armv8: lx2160ardb : Add support for LX2160ARDB platform") brought a new boards support with redundancy in the config.h. One of them is CONFIG_CMDLINE_EDITING which is removed by this change. Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Peng Ma <peng.ma@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * config: enable SP805 watchdog support for LS1028AQiang Zhao2019-05-222-0/+6
| | | | | | | | | | Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * arm: dts: fsl-ls1028a: add sp805 watchdog nodeQiang Zhao2019-05-221-0/+5
| | | | | | | | | | Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * driver: watchdog: add sp805 watchdog supportQiang Zhao2019-05-224-0/+136
| | | | | | | | | | | | | | | | | | sp805 is watchdog on some NXP layerscape SoCs, adding it's driver. Configs CONFIG_WDT_SP805, CONFIG_WDT, CONFIG_CMD_WDT needs to be enabled to use it. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * configs: Unset CONFIG_SPI_BAR for all LS2080A/LS2081A defconfigsRajat Srivastava2019-05-227-0/+7
| | | | | | | | | | Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * configs: Unset CONFIG_SPI_BAR for all LS1046A defconfigsRajat Srivastava2019-05-2211-0/+11
| | | | | | | | | | Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * configs: Unset CONFIG_SPI_BAR for all LS1088A defconfigsAshish Kumar2019-05-2210-0/+10
| | | | | | | | | | | | Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE.Udit Agarwal2019-05-221-9/+2
| | | | | | | | | | | | | | | | | | ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * armv8: Secure Boot: Modify boot_a_script definitionVinitha V Pillai2019-05-227-8/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | esbc_validate command will not be executed if “load” command for its header fails and will further execute the source command for bootscript, without its validation and boot process continues. To halt the boot process in case secure boot header is not loaded successfully, esbc_validate command is invoked separately after “load” command. The secure boot validation of the bootscript header will fail (if header is not loaded) and halts the boot process, which prevent source command from execution. Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * board: fsl: lx2160ardb: invert AQR107 pins polarityFlorin Chiculita2019-05-222-0/+9
| | | | | | | | | | | | | | | | AQR107 PHYs interrupt pins are active-low, while the GIC expects a level-high signal. Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * scsi: ceva: Clean up the driver codePeng Ma2019-05-221-17/+33
| | | | | | | | | | | | | | | | | | Distinguish the ecc val by chassis version and move the ecc addr to dts. Add ls1028a soc support. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * ARM: dts: Freescale: Add ecc addr for sata nodePeng Ma2019-05-225-5/+15
| | | | | | | | | | | | | | Move the ecc addr from driver to dts. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * configs: Enable CONFIG_SPI_FLASH for ls1088ardb_defconfigChuanhua Han2019-05-221-0/+1
| | | | | | | | | | | | | | Enables CONFIG_SPI_FLASH Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * armv8: ls1028aqds: Add support of LS1028AQDSYuantian Tang2019-05-2210-1/+496
| | | | | | | | | | | | | | | | | | | | | | | | | | LS1028AQDS Development System is a high-performance computing, evaluation, and development platform that supports LS1028A QorIQ Architecture processor. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang yuantian <andy.tang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * armv8: ls1028ardb: Add support for LS1028ARDBYuantian Tang2019-05-2213-0/+776
| | | | | | | | | | | | | | | | | | | | | | | | | | LS1028A is an ARMv8 implementation. LS1028ARDB is an evaluation platform that supports the LS1028A family SoCs. This patch add basic support of the platform. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * armv8: ls1028a: Add NXP LS1028A SoC supportYuantian Tang2019-05-2210-2/+525
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * armv8: lx2160a: enable PCIe supportHou Zhiqiang2019-05-224-0/+22
| | | | | | | | | | | | | | | | Enable the PCIe Gen4 controller driver and e1000 for LX2160ARDB and LX2160AQDS boards. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * armv8: lx2160a: add PCIe controller DT nodesHou Zhiqiang2019-05-221-0/+85
| | | | | | | | | | | | | | | | The LX2160A integrated 6 PCIe Gen4 controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * pci: ls_pcie_g4: add device tree fixups for PCI Stream IDsHou Zhiqiang2019-05-223-6/+251
| | | | | | | | | | | | | | | | | | Add the infrastructure for Layerscape SoCs PCIe Gen4 controller to update device tree nodes to convey SMMU stream IDs in the device tree. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * kconfig: add dependency PCIE_LAYERSCAPE_GEN4 for FSL_PCIE_COMPATHou Zhiqiang2019-05-221-1/+1
| | | | | | | | | | | | | | | | | | The LX2160A PCIe is using driver PCIE_LAYERSCAPE_GEN4 instead of PCIE_LAYERSCAPE. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCsHou Zhiqiang2019-05-224-0/+850
| | | | | | | | | | | | | | | | | | | | | | Add PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe controller is based on the Mobiveil IP, which is compatible with the PCI Express™ Base Specification, Revision 4.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bao Xiaowei <Xiaowei.Bao@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * armv8: lx2160a: add MMU table entries for PCIeHou Zhiqiang2019-05-223-1/+29
| | | | | | | | | | | | | | | | The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * armv8: fsl-layerscpae: correct the PCIe controllers' region sizeHou Zhiqiang2019-05-221-0/+7
| | | | | | | | | | | | | | | | | | The LS2080A has 8GB region for each PCIe controller, while the other platforms have 32GB. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * armv8: layerscape: use PCIe address macro for precompile PCIe MMU entryHou Zhiqiang2019-05-221-1/+3
| | | | | | | | | | | | | | | | Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * configs: ls1046: Update mtd-id for QSPI nor in mtdparts variableKuldeep Singh2019-05-2210-20/+20
|/ | | | | | | | | | | | | | | | | Update mtd-id for QSPI nor due to change introduced in mtd/spi in linux 5.0. commit 84d043185dbe ("spi: Add a driver for the Freescale/NXP QuadSPI controller") This modification is only for linux kernel version >= 5.0. To use bootargs for kernel < 5.0, use the following bootargs CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:2m(uboot),14m(free)" CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:2m(uboot),14m(free)" Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* Merge git://git.denx.de/u-boot-mpc83xxTom Rini2019-05-21220-5901/+20053
|\ | | | | | | - Update MPC83xx platform support to current best practices, etc.
| * mpc83xx: Add gazerbeam boardDirk Eibach2019-05-219-2/+564
| | | | | | | | | | | | | | | | | | | | | | | | The gdsys gazerbeam board is based on a Freescale MPC8308 SOC. It boots from NOR-Flash, kernel and rootfs are stored on SD-Card. On board peripherals include: - 2x 10/100 Mbit/s Ethernet (optional) Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * gazerbeam: Add u-boot specific dts include fileMario Six2019-05-212-0/+252
| | | | | | | | | | | | | | Add a U-Boot specific dts file, which encapsulates the needed modifications to the Gazerbeam Linux device tree. Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * gazerbeam: Import Linux DTMario Six2019-05-219-0/+1178
| | | | | | | | | | | | Import the Linux device tree for the Gazerbeam board. Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * board: gazerbeam: Fix SC detectionMario Six2019-05-211-10/+12
| | | | | | | | | | | | | | | | | | The single channel detection in the gazerbeam board driver was not implemented correctly. Fix the detection. Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * gdsys: ioep-fpga: Switch to gazerbeam-style reportingMario Six2019-05-211-140/+489
| | | | | | | | | | | | | | Use a more extensive FPGA feature reporting style in the gdsys ioep-fpga driver. Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * gdsys: cmd_ioloop: Make DM compatibleMario Six2019-05-211-5/+288
| | | | | | | | | | | | | | Make the ioloop command DM compatible, while keeping the old functionality for not-yet-converted boards. Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * gdsys: cmd_ioloop: Introduce commenting enumMario Six2019-05-211-4/+9
| | | | | | | | | | | | | | Replace the boolean parameter of io_check_status that controls whether the status is printed or not with a documenting enum. Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * gdsys: cmd_ioloop: Fix style violationsMario Six2019-05-211-40/+38
| | | | | | | | | | | | | | Fix some style violations in the ioloop command, and make the code more readable where possible. Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * gdsys: mpc8308: Add FPGA flavor optionMario Six2019-05-211-0/+20
| | | | | | | | | | | | | | | | | | More recent versions of IHS FPGAs feature a different memory layout. Add a Kconfig option to differentiate between the legacy layout, and the new layout (which is used on the upcoming "Gazerbeam" and later boards). Signed-off-by: Mario Six <mario.six@gdsys.cc>
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