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* rockchip: rk3188: sdram: Set correct sdram baseHeiko Stübner2017-04-041-1/+1
| | | | | | | | | Right now we're setting the wrong value of 0 as base in the ram_info struct, which is obviously wrong for the rk3188. So instead set the correct value we already have in CONFIG_SYS_SDRAM_BASE. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3188: add README.rockchip paragraph describing sd bootHeiko Stübner2017-04-041-0/+26
| | | | | | | | | Building sd images for rk3188 requires more steps due to the needed split into TPL and SPL as loaders. Describe how to build an image for it in a separate paragraph in the READER.rockchip file. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3188: enable TPL_LIBGENERIC for generic memsetHeiko Stübner2017-04-041-0/+3
| | | | | | | | | | Commit c67c8c604b6c ("board_init.c: Always use memset()") dropped the naive memset alternative from board_init_f_init_reserve. So activate CONFIG_TPL_LIBGENERIC for that common memset implementation. We cannot use the ARCH-specific memset, as that would incur 200bytes of additional TPL size, space we do not have. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* rockchip: spl: use spl_early_init() instead of spl_init()Kever Yang2017-04-042-4/+4
| | | | | | | | | | Rockchip spl driver needs using spl_early_init(). Fixes: b3d2861e (spl: Remove overwrite of relocated malloc limit) Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* rockchip: pinctrl: use per-SoC option names for KconfigPhilipp Tomsich2017-04-041-4/+4
| | | | | | | | | | | | | | | | The config options for pinctrl on the RK3188, RK3288, RK3328 and RK3399 previously showed up in menuconfig with the generic string descriptor "Rockchip pin control driver" requiring one to look through the help/full description to identify which chip each menu entry was for. This change renames each option with the chip-name in the description string to make it easy to identify the configuration options in menuconfig. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* rockchip: mkimage: update rkimage to support pre-padded payloadsPhilipp Tomsich2017-04-042-31/+13
| | | | | | | | | | | | | | | | | To simplify the creation of AArch64 SPL images for the RK3399, we use the ENABLE_ARM_SOC_BOOT0_HOOK option and prepend 4 bytes of padding at the start of the text section. This makes it easy for mkimage to rewrite this word with the 'RK33' boot magic. This change brings logic to calculate the header size and allocate the header back in sync. For the RK3399 we now limit the header to before the payload (i.e. the 'header0' and the padding up to the actual image) and overwrite the first word (inserted by the boot0-hook for this purpose) with the 'RK33' magic in-place. X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
* rockchip: spl: RK3399: use boot0 hook to create space for SPL magicPhilipp Tomsich2017-04-043-1/+20
| | | | | | | | | | | | | | | | | | | | | The SPL binary needs to be prefixed with the boot magic ('RK33' for the RK3399) on the Rockchip platform and starts execution of the instruction word following immediately after this boot magic. This poses a challenge for AArch64 (ARMv8) binaries, as the .text section would need to start on the odd address, violating natural alignment (and potentially triggering a fault for any code that tries to access 64bit values embedded in the .text section). A quick and easy fix is to have the .text section include the 'RK33' magic and pad it with a boot0 hook to insert 4 bytes of padding at the start of the section (with the intention of having mkimage overwrite this padding with the appropriate boot magic). This avoids having to modify the linker scripts or more complex logic in mkimage. X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
* rockchip: mkimage: pad the header to 8-bytes (using a 'nop') for RK3399Philipp Tomsich2017-04-044-36/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RK3399 boot code (running as AArch64) poses a bit of a challenge for SPL image generation: * The BootROM will start execution right after the 4-byte header (at the odd instruction word loaded into SRAM at 0xff8c2004, with the 'RK33' boot magic residing at 0xff8c2000). * The default padding (during ELF generation) for AArch64 is 0x0, which is an illegal instruction and the .text section needs to be naturally aligned (someone might locate a 64bit constant relative to the section start and unaligned loads trigger a fault for all privileged modes of an ARMv8)... so we can't simply define the CONFIG_SPL_TEXT_BASE option to the odd address (0xff8c2004). * Finally, we don't want to change the values used for padding of the SPL .text section for all ARMv8 targets to the instruction word encoding 'nop', as this would affect all padding in this section and might hide errors that would otherwise quickly trigger an illegal insn exception. To deal with this situation, we modify the rkimage generation to - understand the fact that the RK3399 needs to pad the header to an 8 byte boundary using an AArch64 'nop' - the necessary logic to adjust the header_size (which controls the location where the payload is copied into the image) and to insert this padding (AArch64 insn words are always little-endian) into the image following the 4-byte header magic. X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
* rockchip: mkimage: simplify start/size calculation for rc4_encodePhilipp Tomsich2017-04-042-4/+4
| | | | | | | | | | | | | | | The RC4 encoding works on full blocks, but the calculation of the starting offset and size are needlessly complicated by using a reference value known to be offset into a block by the size of the header and then correcting for the (hard-coded) size of the header (i.e. 4 bytes). We change this over to use the RK_SPL_HDR_START directly (which is known to be on a block boundary). X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
* rockchip: configs: correct mmc env dev for rk3288 based boardsJacob Chen2017-04-044-4/+4
| | | | | | | we are using mmc alias , so mmc index have been changed. now mmc dev 0 is emmc and mmc dev 1 is sdmmc. Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
* Prepare v2017.05-rc1v2017.05-rc1Tom Rini2017-04-041-2/+2
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-tegraTom Rini2017-04-0415-0/+3125
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| * apalis-tk1: disable external clock loopback on SDMMC3Marcel Ziswiler2017-04-011-0/+1
| | | | | | | | | | | | | | | | Actually make use of that shiny new CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * mmc: tegra: allow disabling external clock loopbackMarcel Ziswiler2017-04-013-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | Introduce CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK to disable the external clock loopback and use the internal one on SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits being set to 0xfffd according to the TRM. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * arm: tegra: initial support for apalis tk1Marcel Ziswiler2017-04-0112-0/+3095
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds board support for the Toradex Apalis TK1 a computer on module which can be used on different carrier boards. The module consists of a Tegra TK1 SoC, a PMIC solution, 2 GB of DDR3L RAM, a bunch of level shifters, an eMMC, a TMP451 temperature sensor chip, an I210 gigabit Ethernet controller and a SGTL5000 audio codec. Furthermore, there is a Kinetis MK20DN512 companion micro controller for analogue, CAN and resistive touch functionality. For the sake of ease of use we do not distinguish between different carrier boards for now as the base module features are deemed sufficient enough for regular booting. The following functionality is working so far: - eMMC boot, environment storage and Toradex factory config block - Gigabit Ethernet - MMC/SD cards (both MMC1 as well as SD1 slot) - USB client/host (dual role OTG port as client e.g. for DFU/UMS or host, other two ports as host) Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Merge git://git.denx.de/u-boot-arcTom Rini2017-04-042-6/+39
|\ \ | | | | | | | | | | | | In this patch-set we add support of new AXS103 firmware as well as troubleshoot unexpected execution by multiple cores simultaneously.
| * | arcv2: Halt non-master coresAlexey Brodkin2017-03-311-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even though we expect only master core to execute U-Boot code let's make sure even if for some reason slave cores attempt to execute U-Boot in parallel with master they get halted very early. If platform wants it may kick-start slave cores before passing control to say Linux kernel or any other application that want to see all cores of SMP SoC up and running. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | axs103: Support slave core kick-start on axs103 v1.1 firmwareAlexey Brodkin2017-03-311-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In axs103 v1.1 procedure to kick-start slave cores has changed quite a bit compared t previous implementation. In particular: * We used to have a generic START bit for all cores selected by CORE_SEL mask. But now we don't touch CORE_SEL at all because we have a dedicated START bit for each core: bit 0: Core 0 (master) bit 1: Core 1 (slave) * Now there's no need to select "manual" mode of core start Additional challenge for us is how to tell which axs103 firmware we're dealing with. For now we'll rely on ARC core version which was bumped from 2.1c to 3.0. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | axs103: Clean-up smp_kick_all_cpus()Alexey Brodkin2017-03-311-7/+5
| |/ | | | | | | | | | | | | | | | | | | | | | | * Rely on default pulse polarity value * Don't mess with "multicore" value as it doesn't affect execution In essence we now do a bare minimal stuff: 1) Select HS38x2_1 with CORE_SEL=1 bits 2) Select "manual" core start (via CREG) with START_MODE=0 3) Generate cpu_start pulse with START=1 Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | Merge git://git.denx.de/u-boot-mmcTom Rini2017-04-041-27/+73
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| * | mmc: omap_hsmmc: add support for CONFIG_BLKJean-Jacques Hiblot2017-03-301-0/+17
| | | | | | | | | | | | | | | Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | mmc: omap_hsmmc: move the mmc_config to platdata when DM_MMC is usedJean-Jacques Hiblot2017-03-301-5/+22
| | | | | | | | | | | | | | | | | | | | | This is a preparation work for the support of CONFIG_BLK. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | mmc: omap_hsmmc: use mmc_get_blk_desc() to get the block device descJean-Jacques Hiblot2017-03-301-1/+1
| | | | | | | | | | | | | | | Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | mmc: omap_hsmmc: use an accessor to get the private dataJean-Jacques Hiblot2017-03-301-21/+33
| |/ | | | | | | | | | | | | | | For consistency, use an accessor to access the private data. Also for the same reason, rename all priv_data to priv. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Merge git://git.denx.de/u-boot-dmTom Rini2017-04-0414-21/+711
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| * | Add single register pin controller driverFelix Brack2017-03-263-0/+153
| | | | | | | | | | | | | | | | | | This patch adds a pin controller driver supporting devices using a single configuration register per pin. Signed-off-by: Felix Brack <fb@ltec.ch>
| * | reset: Add STi reset supportPatrice Chotard2017-03-264-0/+330
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a reset controller implementation for STMicroelectronics STi family SoCs; it allows a group of related reset like controls found in multiple system configuration registers to be represented by a single controller device. Driver code has been mainly extracted from kernel drivers/reset/sti/reset-stih407.c Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
| * | pci: correct a function descriptionHou Zhiqiang2017-03-261-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | In the description of function pci_match_one_id(), there are some problems on arguments list and return value description, so correct them. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | lib: tpm: Add command to list resourcesmario.six@gdsys.cc2017-03-262-1/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is sometimes convenient to know how many and/or which resources are currently loaded into a TPG, e.g. to test is a flush operation succeeded. Hence, we add a command that lists the resources of a given type currently loaded into the TPM. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | cmd: tpm: Fix flush commandmario.six@gdsys.cc2017-03-261-14/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 7690be35de ("lib: tpm: Add command to flush resources") added a command to flush resources from a TPM. However, a previous development version was accidentially used to generate the patch, resulting in a non-functional command. This patch fixes the flush command. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | tpm: Add function to load keys via their parent's SHA1 hashmario.six@gdsys.cc2017-03-264-0/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we want to load a key into a TPM, we need to know the designated parent key's handle, so that the TPM is able to insert the key at the correct place in the key hierarchy. However, if we want to load a key whose designated parent key we also previously loaded ourselves, we first need to memorize this parent key's handle (since the handles for the key are chosen at random when they are inserted into the TPM). If we are, however, unable to do so, for example if the parent key is loaded into the TPM during production, and its child key during the actual boot, we must find a different mechanism to identify the parent key. To solve this problem, we add a function that allows U-Boot to load a key into the TPM using their designated parent key's SHA1 hash, and the corresponding auth data. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | libfdt: use CONFIG_IS_ENABLED for OF_LIBFDTVignesh R2017-03-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Use CONFIG_IS_ENABLED() macro to check whether OF_TRANSLATE is enabled, so that code block is compiled irrespective of SPL or U-Boot build and fdt address translation is used. Signed-off-by: Vignesh R <vigneshr@ti.com>
| * | Ensure device tree DTS is compiledJames Balean2017-03-261-3/+10
| |/ | | | | | | | | | | | | | | Enables custom DTS files, or those not associated with a specific target, to be compiled into a boot image. Signed-off-by: James Balean <james@balean.com.au> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Simon Glass <sjg@chromium.org>
* | Merge git://www.denx.de/git/u-boot-marvellTom Rini2017-04-0411-229/+1760
|\ \ | | | | | | | | | | | | | | | This includes Marvell mvpp2 patches with the ethernet support for the ARMv8 Armada 7k/8k platforms. The ethernet patches are all acked by Joe and he is okay with me pushing them via the Marvell tree.
| * | arm64: mvebu: Enable CONFIG_PHY_MARVELL in Armada7k/8k-DB defconfigStefan Roese2017-03-292-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Marvell PHY support is needed espescially for the A7040-DB with the SGMII port (port 2). As without the marvell PHY driver configuration for SGMII, ethernet won't work. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | arm64: mvebu: armada-7040-db.dts: Change eth1 speed from 2.5G to 1GStefan Roese2017-03-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The default configuration for the COMPHY-0 port should be 1G, as its used as 1G SGMII connection. This change is necessary to get the MAC2 port (SGMII) working on this DB. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: mvpp2: Remove unreferenced in_use_thresh from struct mvpp2_bm_poolStefan Roese2017-03-291-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | As pointed out by Stefan Chulski, this variable is unused and should be removed. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: mvpp2: Configure SMI PHY address needed for PHY pollingStefan Roese2017-03-291-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On PPv2.2 we enable PHY polling, so we also need to configure the PHY address in the specific PHY address rgisters. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: mvpp2: Enable PHY polling mode on PPv2.2Stefan Roese2017-03-291-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Testing shows, that PHY polling needs to be enabled on Armada 7k/8k. Otherwise ethernet transfers will not work correctly. PHY polling is enabled per default after reset, so we do not need to specifically enable it, but this makes it clearer. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: mvpp2: Add missing PHY_INTERFACE_MODE_RGMII_IDStefan Roese2017-03-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a missing occurrance of PHY_INTERFACE_MODE_RGMII_ID, which should be handled identical to PHY_INTERFACE_MODE_RGMII. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: mvpp2: Add GoP and NetC support for port 0 (SFI)Stefan Roese2017-03-291-0/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to the Marvell mvpp2 ethernet driver for the missing port 0. This code is mostly copied from the Marvell U-Boot version and was written by Stefan Chulski. Please note that only SFI support have been added, as this is the only interface that this code has been tested with. XAUI and RXAUI support might follow at a later stage. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: mvpp2: Add GoP and NetC support for ports 2 & 3 (RGMII & SGMII)Stefan Roese2017-03-291-8/+756
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to the Marvell mvpp2 ethernet driver. This code is mostly copied from the Marvell U-Boot version and was written by Stefan Chulski. Please note that only RGMII and SGMII support have been added, as these are the only interfaces that this code has been tested with. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: mvpp2: Read phy-speed from DT to select between 1GB and 2.5GB SGMIIStefan Roese2017-03-291-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Read the "phy-speed" DT property to differentiate between 1 and 2.5GB SGMII operations. Please note that its unclear right now, if this DT property will be accepted in mainline Linux. If not, we need to revisit this code and change it to use the accepted property. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: mvpp2: Restructure probe / init functionsStefan Roese2017-03-291-30/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch does a bit of restructuring of the probe / init functions, mainly to allow earlier register access as it is needed for the upcoming GoP (Group of Ports) and NetC (Net Complex) code. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: include/phy.h: Add new PHY interface modesStefan Roese2017-03-291-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the new PHY interface modes XAUI, RXAUI and SFI that will be used by the PPv2.2 support in the Marvell mvpp2 ethernet driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: mvpp2: Add RX and TX FIFO configuration for PPv2.2Stefan Roese2017-03-291-7/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the PPv2.2 specific FIFO configuration to the mvpp2 driver. The RX FIFO packet data size is changed to the recommended FIFO sizes. The TX FIFO configuration is newly added. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: mvpp2: Handle eth device naming in multi-CP case correctlyStefan Roese2017-03-291-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the naming of the ethernet ports is not handled correctly in the multi-CP (Communication Processor) case. On Armada 8k, the slave-CP also instantiates an ethernet controller with the same device ID's. This patch now takes this into account and adds the required base-id so that the slave-CP ethernet devices will be named "mvpp2-3 ...". This patch also updates my Copyright notice to include 2017 as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | arm64: mvebu: armada-7k/8k: Enable MVPP2 ethernet driverStefan Roese2017-03-293-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | Since we've now integrated the A7k/8k support in the mvpp2 ethernet driver, lets enable the support for both Marvell developments boards. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | arm64: marvell: dts: add PPv2.2 description to Armada 7K/8KThomas Petazzoni2017-03-294-0/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds the description of the PPv2.2 hardware block for the Marvell Armada 7K and Armada 8K processors, and their corresponding Armada 7040 and 8040 Development boards. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: mvpp2: Enable compilation for Armada 7K/8K platformsStefan Roese2017-03-291-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since Armada 7K/8K is also equipped with a newer version of the MVPP2 ethernet controller, lets enable compilation of this driver for these platforms. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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