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* Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spiWIP/27Jan2020Tom Rini2020-01-2716-239/+1290
|\ | | | | | | | | | | | | | | | | - spi cs accessing slaves (Bin Meng) - spi prevent overriding established bus (Marcin Wojtas) - support speed in spi command (Marek Vasut) - add W25N01GV spinand (Robert Marko) - move cadence_qspi to use spi-mem (Vignesh Raghavendra) - add octal mode (Vignesh Raghavendra)
| * spi: cadence-qspi: Add compatible for TI AM654Vignesh Raghavendra2020-01-271-0/+1
| | | | | | | | | | | | | | | | TI's AM654 SoC has a Cadence OSPI IP. Add a new compatible string for the same. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: cadence-qspi: Add support for Cadence Octal SPI controllerVignesh Raghavendra2020-01-272-2/+7
| | | | | | | | | | | | | | | | | | Cadence OSPI is similar to QSPI IP except that it supports Octal IO (8 IO lines) flashes. Add support for Cadence OSPI IP with existing driver using new compatible Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * mtd: spi-nor-core: Add octal mode supportVignesh Raghavendra2020-01-276-2/+43
| | | | | | | | | | | | | | | | Add support for Octal flash devices. Octal flash devices use 8 IO lines for data transfer. Currently only 1-1-8 Octal Read mode is supported. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: cadence-qspi: Add direct mode supportVignesh Raghavendra2020-01-273-33/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: cadence_qspi: Move to spi-mem frameworkVignesh Raghavendra2020-01-273-178/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
| * mtd: spinand: winbond: Add support for W25N01GVRobert Marko2020-01-271-0/+8
| | | | | | | | | | | | | | | | Linux has supported W25N01GV for a long time, so lets import it. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: ti_qspi: Add support for CS other than CS0Vignesh Raghavendra2020-01-271-8/+13
| | | | | | | | | | | | | | | | | | | | Make sure corresponding setup registers are updated depending on CS. This ensures that driver can support QSPI flashes on ChipSelects other than on CS0 Reported-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: prevent overriding established bus settingsMarcin Wojtas2020-01-271-9/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPI stack relies on a proper bus speed/mode configuration by calling dm_spi_claim_bus(). However the hitherto code allowed to accidentally override those settings in the spi_get_bus_and_cs() routine. The initially established speed could be discarded by using the slave platdata, which turned out to be an issue on the platforms whose slave maximum supported frequency is not on par with the maximum frequency of the bus controller. This patch fixes above issue by configuring the bus from spi_get_bus_and_cs() only in case it was not done before. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
| * cmd: spi: Permit setting bus frequencyMarek Vasut2020-01-271-4/+10
| | | | | | | | | | | | | | | | | | | | The 'sspi' command hard-coded 1 MHz bus frequency for all transmissions. Allow changing that at runtime by specifying '@freq' bus frequency in Hz. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * test: dm: spi: Fix sandbox dm_test_spi_find()Bin Meng2020-01-271-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Per sandbox_cs_info(), sandbox spi controller only supports chip select 0. Current test case tries to locate devices on chip select 1, and any call to spi_get_bus_and_cs() or spi_cs_info() with cs number 1 should not return 0. This updates the test case to handle it correctly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * dm: spi: Check cs number before accessing slavesBin Meng2020-01-272-20/+28
| | | | | | | | | | | | | | Add chip select number check in spi_find_chip_select(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # SoPine
| * spi: nxp_fspi: new driver for the FlexSPI controllerMichael Walle2020-01-273-0/+1004
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a port of the kernel's spi-nxp-fspi driver. It uses the new spi-mem interface and does not expose the more generic spi-xfer interface. The source was taken from the v5.3-rc3 tag. The port was straightforward: - remove the interrupt handling and the completion by busy polling the controller - remove locks - move the setup of the memory windows into claim_bus() - move the setup of the speed into set_speed() - port the device tree bindings from the original fspi_probe() to ofdata_to_platdata() There were only some style change fixes, no change in any logic. For example, there are busy loops where the return code is not handled correctly, eg. only prints a warning with WARN_ON(). This port intentionally left most functions unchanged to ease future bugfixes. This was tested on a custom LS1028A board. Because the LS1028A doesn't have proper clock framework support, changing the clock speed was not tested. This also means that it is not possible to change the SPI speed on LS1028A for now (neither is it possible in the linux driver). Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Kuldeep Singh <kuldeep.singh@nxp.com>
* | Merge branch '2020-01-27-master-imports'Tom Rini2020-01-2714-13/+939
|\ \ | |/ |/| | | | | | | | | - Add Dialog DA9063 PMIC support - s35392a RTC bugfix - Allow for opt-in of removal of DTB properties from the resulting binary.
| * pmic: allow dump command for non contiguous register mapsMartin Fuzzey2020-01-271-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some PMICs (such as the DA9063) have non-contiguous register maps. Attempting to read the non implemented registers returns an error rather than a dummy value which causes 'pmic dump' to terminate prematurely. Fix this by allowing the PMIC driver to return -ENODATA for such registers, which will then be displayed as '--' by pmic dump. Use a single error code rather than any error code so that we can distinguish between a hardware failure reading the PMIC and a non implemented register known to the driver. Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
| * power: regulator: add driver for Dialog DA9063 PMICMartin Fuzzey2020-01-274-0/+421
| | | | | | | | | | | | | | | | | | | | | | Add a driver for the regulators in the the DA9063 PMIC. Robert Beckett: move regulator modes to header so board code can set modes. Correct mode mask used in ldo_set_mode. Add an option CONFIG_SPL_DM_REGULATOR_DA9063. Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group> Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
| * power: pmic: add driver for Dialog DA9063 PMICMartin Fuzzey2020-01-274-0/+453
| | | | | | | | | | | | | | | | | | | | | | | | This adds the basic register access operations and child regulator binding (if a regulator driver exists). Robert Beckett: simplify accesses by using bottom bit of address as offset overflow. This avoids the need to track which page we are on. Add an option CONFIG_SPL_DM_PMIC_DA9063. Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group> Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
| * rtc: s35392a: encode command correctlyIan Ray2020-01-271-11/+18
| | | | | | | | | | | | | | | | | | The 3-bit "command", or register, is encoded within the device address. Configure the device accordingly, and pass command in DM I2C read/write calls correctly. Signed-off-by: Ian Ray <ian.ray@ge.com> Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
| * cmd: sata: Add block unbind device functionPeng Ma2020-01-271-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we didn't unbind the sata from block device, the same devices would be added after sata remove, This patch is to resolve this issue as below: => sata info SATA#0: (3.0 Gbps) SATA#1: (3.0 Gbps) Device 0: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005PY30 Type: Hard Disk Supports 48-bit addressing Capacity: 286168.1 MB = 279.4 GB (586072368 x 512) Device 1: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005VX30 Type: Hard Disk Supports 48-bit addressing Capacity: 286168.1 MB = 279.4 GB (586072368 x 512) => sata stop => sata info SATA#0: (3.0 Gbps) SATA#1: (3.0 Gbps) Device 0: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005PY300 Type: Hard Disk Supports 48-bit addressing Capacity: 286168.1 MB = 279.4 GB (586072368 x 512) Device 1: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005VX300 Type: Hard Disk Supports 48-bit addressing Capacity: 286168.1 MB = 279.4 GB (586072368 x 512) Device 2: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005PY300 Type: Hard Disk Supports 48-bit addressing Capacity: 286168.1 MB = 279.4 GB (586072368 x 512) Device 3: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005VX300 Type: Hard Disk Supports 48-bit addressing Capacity: 286168.1 MB = 279.4 GB (586072368 x 512) Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * tbs2910: add custom CONFIG_OF_REMOVE_PROPS list to defconfigAnatolij Gustschin2020-01-271-0/+2
| | | | | | | | | | | | | | This shrinks the image size: all -3840.0 text -3840.0 Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Soeren Moch <smoch@web.de>
| * dts: add property removal option CONFIG_OF_REMOVE_PROPSAnatolij Gustschin2020-01-273-0/+33
|/ | | | | | | | | | This can be used for device tree size reduction similar as CONFIG_OF_SPL_REMOVE_PROPS option. Some boards must pass the built-in DTB unchanged to the kernel, thus we may not cut it down unconditionally. Therefore enable the property removal list option only if CONFIG_OF_DTB_PROPS_REMOVE is selected. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* Merge tag 'u-boot-clk-26Jan2020' of ↵Tom Rini2020-01-279-106/+34
|\ | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-clk - Various clock fixes and enhancements
| * clock_imx8mq: Make frac_pll_init() staticPedro Jardim2020-01-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | Since frac_pll_init() is only used in this file, change it to 'static'. This fixes the following sparse warning: arch/arm/mach-imx/imx8m/clock_imx8mq.c:662:5: warning: no previous prototype for ‘frac_pll_init’ [-Wmissing-prototypes] Signed-off-by: Pedro Jardim <jardim.c.pedro@gmail.com>
| * clock_imx8mq: Remove the function sscg_pll_init()Pedro Jardim2020-01-261-71/+0
| | | | | | | | | | | | | | | | | | | | | | | | Function sscg_pll_init() is not used anywhere, so it can simply be deleted. This was found because of the following sparse warning: arch/arm/mach-imx/imx8m/clock_imx8mq.c:702:5: warning: no previous prototype for ‘sscg_pll_init’ [-Wmissing-prototypes] int sscg_pll_init(u32 pll) ^~~~~~~~~~~~~ Signed-off-by: Pedro Jardim <jardim.c.pedro@gmail.com>
| * clock_imx8mq: Make do_imx8m_showclocks() staticPedro Jardim2020-01-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Since do_imx8m_showclocks() is only used inside this file, make it 'static'. This fixes the following sparse warning: arch/arm/mach-imx/imx8m/clock_imx8mq.c:836:5: warning: no previous prototype for ‘do_imx8m_showclocks’ [-Wmissing-prototypes] int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, ^~~~~~~~~~~~~~~~~~~ Signed-off-by: Pedro Jardim <jardim.c.pedro@gmail.com>
| * clock_imx8mq: Delete not used init_usb_clk()Pedro Jardim2020-01-261-22/+0
| | | | | | | | | | | | | | | | | | | | | | | | Function init_usb_clk() is not used anywhere, so it can simply be deleted. This was detected by the following sparse warning: arch/arm/mach-imx/imx8m/clock_imx8mq.c:377:6: warning: no previous prototype for ‘init_usb_clk’ [-Wmissing-prototypes] void init_usb_clk(void) ^~~~~~~~~~~~ Signed-off-by: Pedro Jardim <jardim.c.pedro@gmail.com>
| * clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate()Giulio Benetti2020-01-261-2/+8
| | | | | | | | | | | | | | Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
| * clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate()Giulio Benetti2020-01-261-0/+3
| | | | | | | | | | | | | | | | Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
| * clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate()Giulio Benetti2020-01-261-2/+8
| | | | | | | | | | | | | | Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
| * clk: Fix error checking of dev_read_addr_ptrSean Anderson2020-01-263-3/+3
| | | | | | | | | | | | dev_read_addr_ptr returns NULL on error, not FDT_ADDR_T_NONE. Signed-off-by: Sean Anderson <seanga2@gmail.com>
| * clk: Include missing headers for linux/clk-provider.hSean Anderson2020-01-261-0/+4
| | | | | | | | | | | | | | This header was missing a couple of include dependencies when included on its own. Signed-off-by: Sean Anderson <seanga2@gmail.com>
| * clk: uclass: clk_get_by_name() must not be available if CONFIG_OF_PLATDATA ↵Giulio Benetti2020-01-261-1/+1
| | | | | | | | | | | | | | | | | | | | is enabled clk_get_by_name() requires clk_get_by_id() that is not available if CONFIG_OF_PLATDATA is defined, so move clk_get_by_name() into #else condition of #if CONFIG_IS_ENABLED(OF_PLATDATA). Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
| * clk: show more error info when uclass_get_device_by_namePeng Fan2020-01-261-2/+4
| | | | | | | | | | | | | | It will ease debug when uclass_get_device_by_name failed with more error info printed out. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * clk: mediatek: use unsigned type for returning the clk rateFabien Parent2020-01-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | mtk_clk_find_parent_rate is calling clk_get_rate to know the rate of a parent clock. clk_get_rate returns a ulong, while mtk_clk_find_parent_rate returns an int. This implicit cast creates an issue for clock rates big enough to need the full 32 bits to store its data. When that happen the clk rate will become incorrect because of the implicit cast between ulong -> int -> ulong. This commit change the return type of mtk_clk_find_parent_rate to ulong. Signed-off-by: Fabien Parent <fparent@baylibre.com>
* | common: fix regression on block cache initAngelo Durgehello2020-01-262-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | m68k needs block cache list initialized after relocation. Other architectures must not be involved. Fixing regression related to: commit 1526bcce0f7285087621e16e6720636d01839da8 ("common: add blkcache init") Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
* | arm: mvebu: fix A38x breakage from commit bb872dd930ccJoel Johnson2020-01-261-1/+1
| | | | | | | | | | | | | | | | | | This function parameter usage of load_addr was incorrectly caught in the clarifying renames of commit bb872dd930cc, which results in boot failures on Marvell A38x. Signed-off-by: Joel Johnson <mrjoel@lixil.net> Patch-to: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiWIP/26Jan2020Tom Rini2020-01-2661-751/+1782
|\ \ | |/ |/| | | | | | | | | - Libre Computer ALL-H3-IT/ALL-H5-CC board (Chen-Yu Tsai) - Allwinner R40 Ethernet, usb phy enablement (Andre Przywara) - Sunxi auto load from 128KB MMC offset (Andre Przywara) - Orange Pi Win Ethernet phy enablement (Jernej Skrabec)
| * configs: Orange Pi Win: enable ethernet phyJernej Skrabec2020-01-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | Orange Pi Win has gigabit ethernet port, but default U-Boot configuration for that board enabled ethernet driver but didn't enable realtek phy. Fix that. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: Automate loading from 128KB MMC offsetAndre Przywara2020-01-261-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 067e0b9684d4 ("sunxi: Allow booting from 128KB SD/eMMC offset") we support having the SPL loaded from either the traditional 8KB SD card/eMMC offset, or from the alternative location at 128KB. However the sector to find the U-Boot image was still hard-coded at compile time, and had to be adjusted for one of the two choices. Since we can actually override the function to return the sector offset, we can just check the boot source byte there to select the proper offset based on from where the SPL was loaded. This allows the very same binary image to be loaded from either 128KB or 8KB, with the U-Boot proper image always being located just behind the SPL. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: SPL: Factor out sunxi_get_boot_source()Andre Przywara2020-01-261-5/+13
| | | | | | | | | | | | | | | | | | | | The Boot ROM write some boot source ID (SD card, eMMC, SPI, ...) into a certain location in SRAM, so the SPL can easily determine where to load U-Boot proper from. Factor out reading this value, as it will come in handy again shortly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: Add Libre Computer ALL-H5-CC H5 boardChen-Yu Tsai2020-01-242-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Libre Computer ALL-H5-CC board is an upgraded version of the ALL-H3-CC. Changes include: - Gigabit Ethernet via external RTL8211E Ethernet PHY - 16 MiB SPI NOR flash memory - PoE tap header - Line out jack removed Only H5 variant test samples were made available, and the vendor is not certain whether other SoC variants would be made or not. Furthermore the board is a minor upgrade compared to the ALL-H3-CC. Thus the device tree simply includes the one for the ALL-H3-CC, and adds the changes on top. The device tree was synced over from the Linux kernel, along with other H3/H5 changes, in a previous patch. Thus only the defconfig and an entry to the MAINTAINERS file is added. Signed-off-by: Chen-Yu Tsai <wens@csie.org> [jagan: drop CONFIG_SYS_SPI_U_BOOT_OFFS] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: Add Libre Computer ALL-H3-IT H5 boardChen-Yu Tsai2020-01-242-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Libre Computer ALL-H3-IT board is a small single board computer that is roughly the same size as the Raspberry Pi Zero, or around 20% smaller than a credit card. The board features: - H2, H3, or H5 SoC from Allwinner - 2 DDR3 DRAM chips - Realtek RTL8821CU based WiFi module - 128 Mbit SPI-NOR flash - micro-SD card slot - micro HDMI video output - FPC connector for camera sensor module - generic Raspberri-Pi style 40 pin GPIO header - additional pin headers for extra USB host ports, ananlog audio and IR receiver Only H5 variant test samples were made available, but the vendor does have plans to include at least an H3 variant. Thus the device tree is split much like the ALL-H3-CC, with a common dtsi file for the board design, and separate dts files including the common board file and the SoC dtsi file. The other variants will be added as they are made available. The device tree was synced over from the Linux kernel, along with other H3/H5 changes, in a previous patch. Thus only the defconfig and an entry to the MAINTAINERS file is added. Signed-off-by: Chen-Yu Tsai <wens@csie.org> [jagan: drop CONFIG_SYS_SPI_U_BOOT_OFFS] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: move CONFIG_SYS_SPI_U_BOOT_OFFS out of defconfigAndre Przywara2020-01-249-8/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For Allwinner SoCs the CONFIG_SYS_SPI_U_BOOT_OFFS value is not really a board choice: The boot ROM only loads the SPL from offset 0 of the SPI NOR flash, and loads at most 32KB. This is a similar situation as on MMC, so consequently we create our "joint" image (SPL + U-Boot proper) with that 32KB offset during the build. So define the value of this symbol to be 32KB by default for every Allwinner SoC. This removes the definition of this symbol from the _defconfig files, and avoids every board to define this over and over again. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: defconfig: R40 boards: enable USBAndre Przywara2020-01-242-0/+8
| | | | | | | | | | | | | | | | | | | | Now that the USB PHY on the Allwinner R40 SoC is supported, enable USB support for the two R40 boards U-Boot supports. For this we need to add the GPIO pin that powers the USB port(s), also enable the usual suspects (OHCI/EHCI support). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * phy: sun4i-usb: Add Allwinner R40 supportAndre Przywara2020-01-242-0/+13
| | | | | | | | | | | | | | | | | | | | | | Since every Allwinner USB PHY seems to be slightly different from each other, we need to add the compatible string and the respective data structure to make it work on the R40/V40 SoC. Nothing spectacular this time, just one less USB controller than the H3. Copied from the Linux kernel. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: defconfig: Bananapi M2 Berry: enable EthernetAndre Przywara2020-01-241-0/+2
| | | | | | | | | | | | | | | | The M2 Berry features the normal Gigabit PHY connected to the SoC's MAC, so enable the sun8i-emac driver to support Ethernet on the board. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: dts: R40: Update Bananapi M2 Berry .dtsAndre Przywara2020-01-241-15/+120
| | | | | | | | | | | | | | | | Update the .dts file from the kernel, which carries much more nodes, some of them we need to enable USB and Ethernet support for the board. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: H3/H5 Sync DT files from upstream Linux kernel as of next-20200108Chen-Yu Tsai2020-01-2443-723/+1550
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sync the device tree files and device tree header files from upstream Linux kernel, as of 2020-01-08. The commit synced to in the sunxi repo 98d25b0b266d Merge branch 'sunxi/dt-for-5.6' into sunxi/for-next which is also part of next-20200108. Changes brought in include: - cleanup of pinmux node names - addition of Security ID, MBUS, CSI, crypto engine, video codec, pmu, and thermal sensor device nodes for both SoCs - addition of deinterlacing engine device node on H3 - cleanup of RTC device node and addition of its clocks - various board cleanups and improvements - removal of pinmux node for GPIO lines - cpufreq / DVFS - HDMI output - UART-based Bluetooth - audio codec - USB ports - new boards Most of the changes don't concern U-boot. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * common: Update comment to show progressSimon Glass2020-01-241-3/+2
| | | | | | | | | | | | | | This file doesn't include any declarations anymore but it does include other headers. Update the header comment to mention this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * common: Collect all the header files togetherSimon Glass2020-01-241-24/+0
| | | | | | | | | | | | | | There are many header files included here. Put them all together since the blank lines are not useful. Signed-off-by: Simon Glass <sjg@chromium.org>
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