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* configs: j721e_evm: Add configs for ADMA SupportFaiz Abbas2020-01-202-0/+3
| | | | | | | Add configs for ADMA Support. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* arm: dts: k3-j721e-common-proc-board: Add pinmux for SD cardFaiz Abbas2020-01-203-1/+39
| | | | | | | Add pinmux for sdhci1 node connected to the SD card. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* arm: dts: k3-j721e-common-proc-board: Remove voltage-ranges from sdhci nodesFaiz Abbas2020-01-201-2/+0
| | | | | | | voltage-ranges properties are NOP. Remove them. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* mmc: am654_sdhci: Add Support for configuring PHY in J721eFaiz Abbas2020-01-201-29/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Support for writing to PHY registers for J721e. There are number of differences between the J721e 8 bit PHY, J721e 4 bit PHY and AM654 PHY. Create a driver_data structure with an ops and flags field and use the flags field to indicate these differences. The differences are as follows: 1. The J721e 4 bit instance PHY does not have a DLL. Introduce a DLL_PRESENT flag to make sure that DLL related registers are accessed only where they are present. Also add a separate set_ios_post() callback. 2. The J721e 8 bit instance is not muxed with anything else inside the SoC and hence the IOMUX_ENABLE filed does not exist. Add a flag which is used to indicate the presence of this field. 3. The register field used to select DLL frequency is 3 bit wide in J721e as compared to 2 bits in AM65x. Add another flag that distinguishes these fields. 4. The strobe select field is 8 bit wide as compared to 4 bit wide for AM65x. Add yet another flag to indicate this difference. Strobe select is used only for HS400 speed mode, support for which has not been added in AM65x. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* mmc: am654_sdhci: Get Xin clock by nameFaiz Abbas2020-01-202-2/+3
| | | | | | | | Get clk_xin by name instead of by index to avoid having to put clocks in the same order in all devices. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* dma: ti: k3-udma: Fix build warnings when building for 32 bit platformsVignesh Raghavendra2020-01-201-8/+8
| | | | | | | | | Cast pointers properly so as to avoid warnings when driver is built for 32 bit platforms Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* dma: ti: k3-udma: Fix ring push operation for 32 bit coresVignesh Raghavendra2020-01-201-3/+11
| | | | | | | | | | | UDMA always expects 64 bit address pointer of the transfer descriptor in the Ring. But on 32 bit cores like R5, pointer is always 32 bit in size. Therefore copy over 32 bit pointer value to 64 bit variable before pushing it over to the ring, so that upper 32 bits are 0s. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* dma: ti: k3-udma: Switch to exposed ring modeVignesh Raghavendra2020-01-201-2/+2
| | | | | | | | | Exposed ring mode works well with 32 bit and 64 bit cores without need for Proxies for 32 bit cores. Therefore switch to exposed ring mode. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* dma: ti: k3-udma: Fix debug prints during enabling MEM_TO_DEV transfersVignesh Raghavendra2020-01-201-2/+2
| | | | | | | | | Fix up the debug prints that were dumping state of TCHAN RT registers to use tchan for MEM_TO_DEV transfers. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* dma: ti: k3-udma: Remove coherency check for cache opsVignesh Raghavendra2020-01-201-33/+16
| | | | | | | | | | Remove redundant coherency checks before calling cache ops in UDMA driver. This is now handled in arch specific cache operation implementation based on Kconfig option Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* soc: ti: k3-navss-ringacc: Get SYSFW reference from DT phandleVignesh Raghavendra2020-01-201-1/+2
| | | | | | | | | | Instead of looking getting reference to SYSFW device using name which is not guaranteed to be constant, use phandle supplied in the DT node to get reference to SYSFW Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* soc: ti: k3-navss-ringacc: Flush/invalidate caches on ring push/popVignesh Raghavendra2020-01-201-0/+11
| | | | | | | | | | | Flush caches when pushing an element to ring and invalidate caches when popping an element from ring in Exposed Ring mode. Otherwise DMA transfers don't work properly in R5 SPL (with caches enabled) where the core is not in coherency domain. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* dma: ti: k3-udma: Query DMA channels allocated from Resource ManagerVignesh Raghavendra2020-01-201-79/+214
| | | | | | | | | | | On K3 SoCs, DMA channels are shared across multiple entities, therefore U-Boot DMA driver needs to query resource range from centralised resource management controller i.e SystemFirmware and use DMA channels allocated for A72 host. Add support for the same. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* lib: Import few bitmap functions from LinuxVignesh Raghavendra2020-01-202-0/+145
| | | | | | | | | | Import few basic bitmap functions (bitmap_{weight,fill,set,clear,or}()) and their dependencies from Linux. These are required for upcoming DMA resource allocation support for TI's K3 SoCs. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* board: ti: am43xx: remove net platform codeGrygorii Strashko2020-01-201-105/+1
| | | | | | | | | The TI AM43xx platform has DM_ETH and OF_CONTROL enabled, so remove networking platform code. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* board: ti: dra7-evm: remove net platform codeGrygorii Strashko2020-01-201-105/+1
| | | | | | | | | The DRA7 has DM_ETH and OF_CONTROL enabled, so remove networking platform code. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: dts: da850-lcdk: Update DTS files for SPL device tree supportAdam Ford2020-01-202-1/+15
| | | | | | | | | | | | | Currently, the da850-lcdk uses SPL_OF_PLATDATA and manually loads the necessary source code instead of using the auto-generated, because the drivers don't properly autogenerate the code. This patch simply enables the various device tree options to mimic the da850-evm which doesn't need or use OF_PLATDATA for device tree support. It does not disable OF_PLATDATA. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* thermal: ti-bandgap: Fix adc value datatypeFaiz Abbas2020-01-201-3/+3
| | | | | | | | | The CORE_TEMP_SENSOR_MPU register gives a raw adc value which needs to be indexed into a lookup table to get the actual temperature. Fix the naming and datatype of the adc value variable. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* configs: j721e_evm_a72_defconfig: Enable USB related configsVignesh Raghavendra2020-01-201-0/+28
| | | | | | | Enable USB host and device related configs. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* arm: dts: k3-j721e: Add DT nodes for USBVignesh Raghavendra2020-01-204-0/+128
| | | | | | | | | J721e has two instances of Cadence USB3 controller. Add DT nodes for the same. USB0 is configured to device mode and USB1 is configured to host mode. For now only high speed mode is supported. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* environment: ti: Add DFU environment variables k3_dfu.hVignesh Raghavendra2020-01-202-0/+56
| | | | | | | Setup env variables for updating firmwares on eMMC/OSPI/MMC via DFU Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* Merge branch '2020-01-17-improve-aes-support'Tom Rini2020-01-1719-87/+1268
|\ | | | | | | - Add support and tests for AES192 and AES256
| * u-boot: fit: add support to decrypt fit with aesWIP/2020-01-17-improve-aes-supportPhilippe Reynes2020-01-178-1/+240
| | | | | | | | | | | | | | | | | | | | This commit add to u-boot the support to decrypt fit image encrypted with aes. The FIT image contains the key name and the IV name. Then u-boot look for the key and IV in his device tree and decrypt images before moving to the next stage. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
| * mkimage: fit: add support to encrypt image with aesPhilippe Reynes2020-01-1710-2/+716
| | | | | | | | | | | | | | | | | | | | | | This commit add the support of encrypting image with aes in mkimage. To enable the ciphering, a node cipher with a reference to a key and IV (Initialization Vector) must be added to the its file. Then mkimage add the encrypted image to the FIT and add the key and IV to the u-boot device tree. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
| * aes: add test unit for aes196 and aes256Philippe Reynes2020-01-171-0/+4
| | | | | | | | | | | | | | This commit add test unit for aes196 and aes256. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * aes: add test unit for aes128Philippe Reynes2020-01-172-0/+163
| | | | | | | | | | | | | | This commit add test unit for aes128. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * aes: add support of aes192 and aes256Philippe Reynes2020-01-174-65/+125
| | | | | | | | | | | | | | | | Until now, we only support aes128. This commit add the support of aes192 and aes256. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * aes: add a define for the size of a blockPhilippe Reynes2020-01-173-20/+21
|/ | | | | | | | | | | In the code, we use the size of the key for the size of the block. It's true when the key is 128 bits, but it become false for key of 192 bits and 256 bits. So to prepare the support of aes192 and 256, we introduce a constant for the iaes block size. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge tag 'mmc-1-16-2020' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmcWIP/16Jan2020Tom Rini2020-01-1619-166/+66
|\ | | | | | | | | - Cleanup of fsl_esdhc driver together with arch/defconfig change - Add quirk for APP_CMD retry
| * mmc: config help typo fixJoel Johnson2020-01-161-1/+1
| | | | | | | | | | | | Fix typo in description of MMC_QUIRKS config option. Signed-off-by: Joel Johnson <mrjoel@lixil.net>
| * mmc: add additional quirk for APP_CMD retryJoel Johnson2020-01-162-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | It was observed (on ClearFog Base) that sending MMC APP_CMD returned an error on the first attempt. The issue appears to be timing related since even inserting a puts() short debug entry before the execution added sufficient delay to receive success on first attempt. Follow the existing quirks pattern to retry if initial issuance failed so as to not introduce any delay unless needed. Signed-off-by: Joel Johnson <mrjoel@lixil.net>
| * Drop CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK usageYangbo Lu2020-01-164-50/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The eSDHC reference clocks should be provided by speed.c in arch/. And we do not need CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK option to select which clock to use. Because we can make the driver to select the periperhal clock which is better (provides higher frequency) automatically if its value is provided by speed.c. This patch is to drop this option and make driver to select clock automatically. Also fix peripheral clock calculation issue in fsl_lsch2_speed.c/fsl_lsch3_speed.c. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * configs: ls1028a: use default SDHC clock divider valueYangbo Lu2020-01-164-4/+0
| | | | | | | | | | | | | | The SDHC clock divider value for LS1028A should be default 2, not 1. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * Add global variable sdhc_per_clk for arm/powerpcYangbo Lu2020-01-162-0/+5
| | | | | | | | | | | | | | | | | | | | | | The QorIQ eSDHC controller supports two reference clocks. They are platform clock and periperhal clock. The global variable sdhc_clk has already been used for platform clock. This patch is to add another global variable sdhc_per_clk for periperhal clock, which provides higher frequency and is required to be used for SD UHS and eMMC HS200/HS400 speed modes. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * powerpc/mpc85xx: drop eSDHC periperhal clock codeYangbo Lu2020-01-166-61/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The below patch added eSDHC periperhal clock code initially. 2d9ca2c mmc: fsl_esdhc: Add peripheral clock support The purpose was to fix up device tree properties "peripheral-frequency" so that linux could get the periperhal clock by it. However the implementation on both u-boot and linux was only for a Freescale SDK release. The linux part implementation had never been upstreamed. These code should not have been exist on u-boot mainline. Let's remove the powerpc part changes but keep the changes in fsl_esdhc driver. The changes in fsl_esdhc driver could be utilized to support SD UHS and eMMC HS200/HS400 speed modes for current Layerscape ARM platforms. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * mmc: fsl_esdhc: drop useless fdt fixupYangbo Lu2020-01-161-9/+0
| | | | | | | | | | | | | | | | The fdt fixup for properties "peripheral-frequency" and "adapter-type" was once for a Freescale SDK release. The properties haven't been existed in linux mainline. Drop these useless code. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * mmc: fsl_esdhc_imx: drop QorIQ eSDHC specific peripheral clock codeYangbo Lu2020-01-161-40/+0
| | | | | | | | | | | | Drop QorIQ eSDHC specific peripheral clock code. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini2020-01-164-9/+27
|\ \ | | | | | | | | | | | | | | | - Clearfog: Fix SD booting (Baruch) - Misc updates to MMC handling in SPL to support booting from main data partition (vs hardware boot partition) on MVEBU (Baruch)
| * | arm: mvebu: clearfog: update eMMC documentationBaruch Siach2020-01-161-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPL now automatically selects the correct U-Boot image offset for both eMMC and SD card. No need to tweak CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR anymore. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm: mvebu: clearfog: set uboot image SD card offsetBaruch Siach2020-01-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Armada 38x ROM skips the first SD card offset when loading SPL. This affects the location of the main U-Boot image. SPL MMC code now supports U-Boot image offset based on run-time detection of the boot partition. Use this feature to make the same generated image support both SD card and eMMC boot partition. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * | spl: mmc: support uboot image offset on main partitionBaruch Siach2020-01-162-2/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Armada 38x platforms the ROM code loads SPL from offset 0 of eMMC hardware boot partitions. When there are no boot partitions (i.e. SD card) the ROM skips the first sector that usually contains the (logical) partition table. Since the generated .kwb image contains the main U-Boot image in a fixed location (0x140 sectors by default), we end up with the main U-Boot image in offset of 1 sector. The current workaround is to manually set CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR to 0x141 to compensate for that. This patch uses the run-time detected boot partition to determine the right offset of the main U-Boot partition. The generated .kwb image is now compatible with both eMMC boot partition, and SD card main data partition. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * | configs: clearfog: enable SPL_DM_GPIO to fix boot from SDBaruch Siach2020-01-161-0/+1
| |/ | | | | | | | | | | | | | | | | | | SPL needs DM GPIO to read the SD card-detect signal. This complements the fix in commit 70bae02f71d4 ("arm: mvebu: clearfog: fix boot from SD card"). Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge tag 'xilinx-for-v2020.04' of ↵Tom Rini2020-01-16119-3899/+1677
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx/FPGA changes for v2020.04 ARM64: - Add INIT_SPL_RELATIVE dependency SPL: - FIT image fix - Enable customization of bl2_plat_get_bl31_params() Pytest: - Add test for octal/hex conversions Microblaze: - Fix manual relocation for one SPI instance Nand: - Convert zynq/zynqmp drivers to DM Xilinx: - Enable boot script location via Kconfig - Support OF_SEPARATE in board FDT selection - Remove low level uart setup it is done later by code - Add support for DEVICE_TREE variable passing for SPL Zynq: - Enable jtag boot mode via distro boot - Removing unused baseaddresses from hardware.h - DT fixups ZynqMP: - Fix emmc boot sequence - Simplify spl logic around bss and board_init_r() - Support psu_post_config_data() calling - Tune mini-nand DTS - Fix psu wiring for a2197 boards - Add runtime MMC device boot order filling in spl - Clear ATF handoff handling with custom bl2_plat_get_bl31_params() - Add support u-boot.its generation - Use single image configuration for all platforms - Enable PANIC_HANG via Kconfig - DT fixups - Firmware fixes - Add support for zcu208 and zcu1285 Versal: - Fix emmc boot sequence - Enable board_late_init() by default
| * | arm64: versal: Enable board_late_init callingMichal Simek2020-01-141-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Qemu v4.2.0 maps bootmode registers to address space which was the reason why board_late_init() was disabled and accesses were failing. With new Qemu board_late_init() can be called without any issue. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: dts: zynq: enablement of coresight topologyZumeng Chen2020-01-141-0/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to build the coresight topology structure of zynq-7000 series according to the docs of coresight and userguide of zynq-7000. Signed-off-by: Zumeng Chen <zumeng.chen@windriver.com> Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm64: zynqmp: Sync gem clock nodes with mainline LinuxMichal Simek2020-01-141-9/+13
| | | | | | | | | | | | | | | | | | Just fixing indentation and update year in Copyright. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm64: zynqmp: Sync gpio-controller name locationMichal Simek2020-01-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Sync location with mainline kernel. Added by Linux kernel commit 75926f07baae ("arm64: dts: zynqmp: Add missing gpio-controller to ps gpio"). Fixes: 0b33e0b15600 ("arm64: zynqmp: Add missing gpio property to dtsi") Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm64: dts: zynqmp: replace gpio-key,wakeup with wakeup-source propertySudeep Holla2020-01-144-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the legacy "gpio-key,wakeup" boolean property is already replaced with "wakeup-source". However few occurrences of old property has popped up again, probably from the remnants in downstream trees. This patch replaces the legacy properties with the unified "wakeup-source" property introduced by: "Input: gpio_keys - switch to using generic device properties" (sha1: 700a38b27eefc582099fdf69effacfad0ad738a4) Cc: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm64: dts: zcu100-revC: Give wifi some time after power-onJan Kiszka2020-01-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Somewhere along recent changes to power control of the wl1831, power-on became very unreliable on the Ultra96, failing like this: wl1271_sdio: probe of mmc2:0001:1 failed with error -16 wl1271_sdio: probe of mmc2:0001:2 failed with error -16 After playing with some dt parameters and comparing to other users of this chip, it turned out we need some power-on delay to make things stable again. In contrast to those other users which define 200 ms, Ultra96 is already happy with 10 ms. Fixes: 5869ba0653b9 ("arm64: zynqmp: Add support for Xilinx zcu100-revC") Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm64: dts: zynqmp: Fix node names which contain "_"Michal Simek2020-01-146-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | s/_/-/ for node names. It fixes warnings like this: ... Warning (node_name_chars_strict): /cpu_opp_table: Character '_' not recommended in node name ... Issues reported by make dtbs W=12 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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