summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeFilesLines
* mips: bmips: enable the SPI flash on the Comtrend AR-5387unÁlvaro Fernández Rojas2018-01-242-0/+20
| | | | | | | | | It's a Macronix (mx25l12805d) 16 MB SPI flash. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* mips: bmips: add bcm63xx-hsspi driver support for BCM63268Álvaro Fernández Rojas2018-01-241-0/+21
| | | | | | | | | This driver manages the high speed SPI controller present on this SoC. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* mips: bmips: add bcm63xx-hsspi driver support for BCM6328Álvaro Fernández Rojas2018-01-241-0/+24
| | | | | | | | | This driver manages the SPI controller present on this SoC. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* dm: spi: add BCM63xx HSSPI driverÁlvaro Fernández Rojas2018-01-243-0/+423
| | | | | | | | | This driver is a simplified version of linux/drivers/spi/spi-bcm63xx-hsspi.c Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* mips: bmips: enable the SPI flash on the Netgear CG3100DÁlvaro Fernández Rojas2018-01-242-0/+20
| | | | | | | | | It's a Spansion (s25fl064a) 8 MB SPI flash. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* mips: bmips: enable the SPI flash on the Sagem F@ST1704Álvaro Fernández Rojas2018-01-242-0/+20
| | | | | | | | | It's a Winbond (w25x32) 4 MB SPI flash. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* mips: bmips: add bcm63xx-spi driver support for BCM63268Álvaro Fernández Rojas2018-01-241-0/+17
| | | | | | | | | This driver manages the low speed SPI controller present on this SoC. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* mips: bmips: add bcm63xx-spi driver support for BCM3380Álvaro Fernández Rojas2018-01-241-0/+17
| | | | | | | | | This driver manages the SPI controller present on this SoC. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* mips: bmips: add bcm63xx-spi driver support for BCM6358Álvaro Fernández Rojas2018-01-241-0/+17
| | | | | | | | | This driver manages the SPI controller present on this SoC. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* mips: bmips: add bcm63xx-spi driver support for BCM6348Álvaro Fernández Rojas2018-01-241-0/+17
| | | | | | | | | This driver manages the SPI controller present on this SoC. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* mips: bmips: add bcm63xx-spi driver support for BCM6338Álvaro Fernández Rojas2018-01-241-0/+17
| | | | | | | | | This driver manages the SPI controller present on this SoC. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: spi: add BCM63xx SPI driverÁlvaro Fernández Rojas2018-01-243-0/+442
| | | | | | | | | This driver is a simplified version of linux/drivers/spi/spi-bcm63xx.c Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* drivers: spi: consider command bytes when sending transfersÁlvaro Fernández Rojas2018-01-242-2/+2
| | | | | | | | | | Command bytes are part of the written bytes and they should be taken into account when sending a spi transfer. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* drivers: spi: allow limiting readsÁlvaro Fernández Rojas2018-01-242-0/+6
| | | | | | | | | | | | For some SPI controllers it's not possible to keep the CS active between transfers and they are limited to a known number of bytes. This splits spi_flash reads into different iterations in order to respect the SPI controller limits. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* wait_bit: use wait_for_bit_le32 and remove wait_for_bitÁlvaro Fernández Rojas2018-01-2433-263/+205
| | | | | | | | wait_for_bit callers use the 32 bit LE version Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* wait_bit: add 8/16/32 BE/LE versions of wait_for_bitÁlvaro Fernández Rojas2018-01-241-0/+65
| | | | | | | | | | Add 8/16/32 bits and BE/LE versions of wait_for_bit. This is needed for reading registers that are not aligned to 32 bits, and for Big Endian platforms. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* doc: bindings: soft-spi: update documentation to match the codeMiquel Raynal2018-01-101-10/+14
| | | | | | | | | | | Linux bindings have been introduced in the code (removing the U-Boot specific ones) without documentation update. Compatible string has changed, as well as the four GPIO properties. Reflect this by updating the soft-spi.txt documentation. Fixes: 102412c415 ("dm: spi: soft_spi: switch to use linux compatible string") Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* Merge git://git.denx.de/u-boot-rockchipTom Rini2018-01-0912-0/+223
|\
| * rockchip: clk: bind reset driverElaine Zhang2018-01-099-0/+80
| | | | | | | | | | | | | | | | | | Bind rockchip reset to clock-controller with rockchip_reset_bind(). Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: reset: support a (common) rockchip reset driversElaine Zhang2018-01-093-0/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create driver to support the soft reset (i.e. peripheral) of all Rockchip SoCs. Example of usage: i2c driver: ret = reset_get_by_name(dev, "i2c", &reset_ctl); if (ret) { error("reset_get_by_name() failed: %d\n", ret); } reset_assert(&reset_ctl); udelay(50); reset_deassert(&reset_ctl); i2c dts node: resets = <&cru SRST_P_I2C1>, <&cru SRST_I2C1>; reset-names = "p_i2c", "i2c"; Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [Fixed commit tag:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | Merge git://git.denx.de/u-boot-uniphierTom Rini2018-01-093-2/+25
|\ \ | |/ |/|
| * ARM: uniphier: hide memory top by platform hook instead of CONFIGMasahiro Yamada2018-01-092-2/+7
| | | | | | | | | | | | | | I do not see a good reason to do this by a CONFIG option that affects all SoCs. The ram_size can be adjusted by dram_init() at run-time. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: enable CONFIG_MMC_SDHCI_SDMA for ARMv8 SoCsMasahiro Yamada2018-01-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I did not enable SDMA when I added sdhci-cadence support because LD20 boards are equipped with a large amount memory beyond 32 bit address range, but SDMA does not support the 64bit address. U-Boot relocates itself to the end of effectively available RAM. This would make the MMC enumeration fail because the buffer for EXT_CSD allocated in the stack would go too high, then SDMA would fail to transfer data. Recent SDHCI-compatible controllers support ADMA, but unfortunately U-Boot does not support ADMA. In the previous commit, I hided the DRAM area that exceeds the 32 bit address range. Now, I can enable CONFIG_MMC_SDHCI_SDMA. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: do not use RAM that exceeds 32 bit address rangeMasahiro Yamada2018-01-091-0/+17
|/ | | | | | | | | | | | | | | | | | | | | LD20 / PXs3 boards are equipped with a large amount of memory beyond the 32 bit address range. U-Boot relocates itself to the end of the available RAM. This is a problem for DMA engines that only support 32 bit physical address, like the SDMA of SDHCI controllers. In fact, U-Boot does not need to run at the very end of RAM. It is rather troublesome for drivers with DMA engines because U-Boot does not have API like dma_set_mask(), so DMA silently fails, making the driver debugging difficult. Hide the memory region that exceeds the 32 bit address range. It can be done by simply carving out gd->ram_size. It would also possible to override get_effective_memsize() or to define CONFIG_MAX_MEM_MAPPED, but dram_init() is a good enough place to do this job. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Prepare v2018.01v2018.01Tom Rini2018-01-081-1/+1
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-imxTom Rini2018-01-0831-122/+1001
|\
| * mtd: nand: mxs_nand_spl: Remove nand size printJagan Teki2018-01-081-2/+0
| | | | | | | | | | | | | | It is not much needed to print nand size in SPL during nand boot, and most of nand spl drivers doesn't print the same. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * board: engicam: Fix to remove legacy board/icorem6_rqsJagan Teki2018-01-081-48/+0
| | | | | | | | | | | | | | | | | | board/icorem6_rqs/ is forgot to remove while moving common board files together in (sha1: 52aaddd6f415397bb2eae0d68a8cc1c5c4a98bb3) "i..MX6: engicam: Add imx6q/imx6ul boards for existing boards" Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * imx: initialize and use generic timer on i.MX 6UL/ULLStefan Agner2018-01-084-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX 6UL/ULL feature a Cortex-A7 CPU which suppor the ARM generic timer. This change makes use of the ARM generic timer in U-Boot. This is crucial to make the ARM generic timers usable in Linux since timer_init() initalizes the system counter module, which is necessary to use the generic timers CP15 registers. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * imx: introduce CONFIG_GPT_TIMERStefan Agner2018-01-084-1/+7
| | | | | | | | | | | | | | | | Introduce a new config symbol to select the i.MX General Purpose Timer (GPT). Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * imx: move CONFIG_SYSCOUNTER_TIMER to KconfigStefan Agner2018-01-084-2/+4
| | | | | | | | | | Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * mx6ull: Handle the CONFIG_MX6ULL cases correctlyFabio Estevam2018-01-0410-28/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 051ba9e082f7 ("Kconfig: mx6ull: Deselect MX6UL from CONFIG_MX6ULL") CONFIG_MX6ULL does not select CONFIG_MX6UL anymore, so take this into consideration in all the checks for CONFIG_MX6UL. This fixes a boot regression. Reported-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Stefan Agner <stefan@agner.ch> Tested-by: Breno Lima <breno.lima@nxp.com> Tested-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Tested-by: Jörg Krause <joerg.krause@embedded.rocks>
| * ARM: imx: cm_fx6: env: don't run boot scripts twiceChristopher Spinrath2018-01-031-7/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot scripts located in the root directory of the first partition of USB, mmc, and SATA drives are executed twice: first by the distro boot command and then by the legacy boot command. This may have weird side effects if those scripts only change or extend the environment (including parts of the boot command itself). Removing the script execution from the legacy boot command has its own caveats. For instance, the distro boot command may execute the boot.scr on the mmc drive, then the boot.scr on the SATA drive, before the legacy boot command actually boots from the mmc drive. However, the current behavior would only execute the boot.scr once more before the actual boot, but it does not prevent the script located on the SATA drive from being executed, and thus, both scripts from being mixed up. Considering that the legacy boot command is only in place to boot old (standard) installations, let's go with the resolution having less custom code and remove the script execution from the legacy boot command. Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * ARM: imx: cm_fx6: env: support distro boot commandChristopher Spinrath2018-01-032-20/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current default environment of the cm_fx6 is not suitable for booting modern distributions. Instead of extending the custom environment, let's use the distro boot command, which has been developed for precisely this use case. If the distro boot command fails, fall back to the old behavior (except for USB drives where the old behaviour is completely covered by the distro boot command). That way it is still possible to create "rescue SD cards" for old installations (e.g. if one messes up the on-flash environment). Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * ARM: imx: cm_fx6: env: use standard variablesChristopher Spinrath2018-01-031-12/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation for supporting the distro boot command, introduce the standard variables for specifying load addresses, which are documented in README and doc/README.distro, and replace the custom variables used so far with them. Since the current address layout disregards an address for an initramfs, also switch to the load addresses used and proven by other imx6 boards (e.g. the wandboard and nitrogen6x), instead of going on with our own way. Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * imx: spl: Fix NAND bootmode detectionEran Matityahu2018-01-033-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 20f14714169 ("imx: spl: Update NAND bootmode detection bit") broke the NAND bootmode detection by checking if BOOT_CFG1[7:4] == 0x8 for NAND boot mode. This commit essentially reverts it, while using the IMX6_BMODE_* macros that were introduced since. Tables 8-7 & 8-10 from IMX6DQRM say the NAND boot mode selection is done when BOOT_CFG1[7] is 1, but BOOT_CFG1[6:4] is not necessarily 0x0 in this case. Actually, NAND boot mode is when 0x8 <= BOOT_CFG1[7:4] <= 0xf, like it was in the code before. Signed-off-by: Eran Matityahu <eran.m@variscite.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Jagan Teki <jagan@openedev.com> Cc: Tim Harvey <tharvey@gateworks.com>
| * mx6: Add board mx6memcal for use in validating DDREric Nelson2018-01-0310-0/+894
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a virtual "board" that uses configuration files and Kconfig to define the memory layout used by a real board during the board bring-up process. It generates an SPL image that can be loaded using imx_usb or SB_LOADER.exe. When run, it will generate a set of calibration constants for use in either or both a DCD configuration file for boards that use u-boot.imx or struct mx6_mmdc_calibration for boards that boot via SPL. In essence, it is a configurable, open-source variant of the Freescale ddr-stress tool. https://community.nxp.com/docs/DOC-105652 File mx6memcal_defconfig configures the board for use with mx6sabresd or mx6qsabreauto. Signed-off-by: Eric Nelson <eric@nelint.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
* | Merge git://git.denx.de/u-boot-x86Tom Rini2018-01-087-7/+64
|\ \
| * | x86: tangier: Add Bluetooth to ACPI tableAndy Shevchenko2018-01-081-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As defined on reference board followed by Intel Edison a Bluetooth device is attached to HSU0, i.e. PCI 0000:04.1. Describe it in ACPI accordingly. Note, we use BCM2E95 ID here as one most suitable for such device based on the description in commit message of commit 89ab37b489d1 ("Bluetooth: hci_bcm: Add support for BCM2E95 and BCM2E96") in the Linux kernel source tree. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: tangier: Use actual GPIO hardware numbersAndy Shevchenko2018-01-081-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The recent commit 03c4749dd6c7 ("gpio / ACPI: Drop unnecessary ACPI GPIO to Linux GPIO translation") in the Linux kernel reveals the issue we have in ACPI tables here, i.e. we must use hardware numbers for GPIO resources and, taking into consideration that GPIO and pin control are *different* IPs on Intel Tangier, we need to supply numbers properly. Besides that, it improves user experience since the official documentation for Intel Edison board is referring to GPIO hardware numbering scheme. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: Move commands from under arch/x86 to cmd/x86/Tom Rini2018-01-086-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We only need to compile and link these files when building for full U-Boot. Move them to under cmd/x86/ to make sure they aren't linked in and undiscarded due to u_boot_list_2_cmd_* being included). Cc: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | crypto/fsl: fix BLOB encapsulation and decapsulationClemens Gruber2018-01-082-16/+91
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The blob_encap and blob_decap functions were not flushing the dcache before passing data to CAAM/DMA and not invalidating the dcache when getting data back. Therefore, blob encapsulation and decapsulation failed with errors like the following due to data cache incoherency: "40000006: DECO: desc idx 0: Invalid KEY command" To ensure coherency, we require the key_mod, src and dst buffers to be aligned to the cache line size and flush/invalidate the memory regions. The same requirements apply to the job descriptor. Tested on an i.MX6Q board. Reviewed-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
* | Merge git://git.denx.de/u-boot-rockchipTom Rini2018-01-034-3/+34
|\ \
| * | rockchip: firefly-rk3399: enable SPL_ATF_NO_PLATFORM_PARAMPhilipp Tomsich2018-01-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Rockchip-released ATF for the Firefly apparently (i.e. Kever reported this) does not tolerate a FDT being passed as the platform parameter and will run into a hard stop. To work around this limitation in the ATF parameter handling, we enable SPL_ATF_NO_PLATFORM_PARAM (which will force passing NULL for the platform parameters). Note that this only affects this platform, as the ATF releases for the RK3368 and RK3399 have always either ignored the platform parameter (i.e. before the FDT-based parameters were supported) or support receiving a pointer to a FDT. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | spl: atf: add SPL_ATF_NO_PLATFORM_PARAM optionPhilipp Tomsich2018-01-032-3/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While we expect to call a pointer to a valid FDT (or NULL) as the platform parameter to an ATF, some ATF versions are not U-Boot aware and have an insufficiently robust (or an overzealour) parameter validation: either way, this may cause a hard-stop with uncooperative ATF versions. This change adds the option to suppress passing a platform parameter and will always pass NULL. Debug output from ATF w/ this option disabled (i.e. default): INFO: plat_param_from_bl2: 0x291450 Debug output from ATF w/ this option enabled: INFO: plat_param_from_bl2: 0 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: board: lion-rk3368: reduce env-size default to 8KiBPhilipp Tomsich2018-01-021-0/+6
| |/ | | | | | | | | | | | | | | | | | | We want to have the same configuration defaults for the RK3368-uQ7 as for the RK3399-Q7: this change reduces the default env-size to 8KiB to ensure that it does not overlap the boot-payload on SD/MMC configurations. References: commit fe529e6597c0 ("rockchip: rk3399-puma: reduce env size to 8kiB") Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | video: Support multiple lines version string displayPeng Fan2018-01-031-7/+23
| | | | | | | | | | | | | | | | | | | | | | | | The calculation of left space for version string is not correct, should use VIDEO_COLS not VIDEO_LINE_LEN / 2, otherwise we will get larger space than actual have and cause string to overlay logo picture. Also current version string display only supports two lines words at max. This also causes overlay when the LCD pixel column size is not enough. Signed-off-by: Peng Fan <peng.fan@nxp.com> Tested-by: Anatolij Gustschin <agust@denx.de>
* | video: ipu: Fix dereferencing NULL pointer problemPeng Fan2018-01-031-1/+5
|/ | | | | | | | The clk_set_rate function dereferences the clk pointer without checking whether it is NULL. This may cause problem when clk is NULL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
* boards: amlogic: khadas-vim: Typo fixupNeil Armstrong2018-01-021-1/+1
| | | | | | | | Khadas VIM is an Open Source DIY Box manufactured by Shenzhen Wesion NOT 'Tomato' The fix was provided by Khadas Team member 'numbqq'. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* Prepare v2018.01-rc3v2018.01-rc3Tom Rini2018-01-011-1/+1
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
View Lorry Controller Status