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* ARM: uniphier: add uniphier_cache_inv_way() to support way invalidationMasahiro Yamada2016-08-112-1/+10
| | | | | | This invalidates entries in specified ways of the outer cache. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: fix CONFIG_SYS_CACHELINE_SIZE when outer cache is onMasahiro Yamada2016-08-111-0/+4
| | | | | | | The UniPhier outer cache (L2 cache on ARMv7 SoCs) has 128 byte line length and its tags are also managed per 128 byte line. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: move (and rename) CONFIG_UNIPHIER_L2CACHE_ON to KconfigMasahiro Yamada2016-08-113-4/+8
| | | | | | | Move this option to Kconfig, renaming it into CONFIG_CACHE_UNIPHIER. The new option name makes sense enough, and the same as Linux has. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: move outer cache register macros to .c fileMasahiro Yamada2016-08-112-69/+55
| | | | | | | Now, all of these macros are only used in cache-uniphier.c, so there is no need to export them in a header file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: reuse uniphier_cache_disable() for lowlevel_initMasahiro Yamada2016-08-111-7/+3
| | | | | | | The DRAM is available at this point, so setup the temporary stack and call the C function to reduce the code duplication a bit. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: export uniphier_cache_enable/disable functionsMasahiro Yamada2016-08-112-10/+26
| | | | | | | | The System Cache (outer cache) is used not only as L2 cache, but also as locked SRAM. The functions for turning on/off it is necessary whether the L2 cache is enabled or not. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: move lowlevel debug init code after page table switchMasahiro Yamada2016-08-111-4/+4
| | | | | | | | | As the sLD3 Boot ROM has a complex page table, it is difficult to set up the debug UART with enabling it. It will be much easier to initialize the UART port after switching over to the straight-mapped page table. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: fix ROM boot mode for PH1-sLD3Masahiro Yamada2016-08-111-0/+5
| | | | | | | | | | | | | | Commit 4b50369fb535 ("ARM: uniphier: create early page table at run-time") broke the ROM boot mode for PH1-sLD3 SoC, because the run-time page table creation requires the outer cache register access but the page table in the sLD3 Boot ROM does not straight-map virtual/physical addresses. The idea here is to check the current page table to determine if it is a straight map table. If not, adjust the outer cache register base. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: refactor L2 zero-touching code in lowlevel_initMasahiro Yamada2016-08-111-26/+22
| | | | | | | Here, the ldr pseudo-instruction falls into the ldr + data set. The register access by [r1, #offset] produces shorter code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: do not compile v7_outer_cache_disable if L2 is disabledMasahiro Yamada2016-08-111-1/+1
| | | | | | | | If CONFIG_UNIPHIER_L2CACHE_ON is undefined, the L2 cache is never enabled, so there is no need for v7_outer_cache_disable(). The weak stub avoids the compile error anyway. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: support prefetch and touch operations for outer cacheMasahiro Yamada2016-08-112-10/+57
| | | | | | | | | | The UniPhier outer cache (L2 cache on ARMv7 SoCs) can be used as SRAM by locking ways. These functions will be used to transfer the trampoline code for SMP into the locked SRAM. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: refactor outer cache codeMasahiro Yamada2016-08-111-47/+52
| | | | | | | | | Unify the range/all operation routines into the common function, uniphier_cache_maint_common(), and sync code with Linux a bit more. This reduces the code duplication. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge git://www.denx.de/git/u-boot-ppc4xxTom Rini2016-08-091-21/+45
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| * ppc4xx: Fix platform supportDirk Eibach2016-08-091-21/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit "ecc3066 Fix board init code to respect the C runtime environment" broke platform support for ppc4xx. start.S prepares a stackframe that is later rendered unusable by appending the reserved space for global data. Instead the reserved space has to be put first. Then the stackframe can be pushed. I can only test the 405EP OCM case. At least all other ppc4xx boards still build. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>
* | i2c: i2c-uclass-compat: avoid any BSS usageVignesh R2016-08-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | As I2C can be used before DRAM initialization for reading EEPROM, avoid using static variables stored in BSS, since BSS is in DRAM, which may not have been initialised yet. Explicitly mark "static global" variables as belonging to the .data section. Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Heiko Schocher<hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* | efi_loader: disk: Sanitize exposed devicesAlexander Graf2016-08-081-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | When a target device is 0 bytes long, there's no point in exposing it to the user. Let's just skip them. Also, when an offset is passed into the efi disk creation, we should remove this offset from the total number of sectors we can handle. This patch fixes both things. Signed-off-by: Alexander Graf <agraf@suse.de>
* | efi_loader: disk: Fix CONFIG_BLK breakageAlexander Graf2016-08-082-12/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When using CONFIG_BLK, there were 2 issues: 1) The name we generate the device with has to match the name we set in efi_set_bootdev() 2) The device we pass into our block functions was wrong, we should not rediscover it but just use the already known pointer. This patch fixes both issues. Signed-off-by: Alexander Graf <agraf@suse.de>
* | tiny-printf: Adjust to avoid using data sectionSimon Glass2016-08-081-44/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can pass all the variables down to the functions that need them, and then everything is on the stack. This is safer than using the data section. At least on firefly-rk3288, the code size is the same and the data size is 12 bytes smaller: before: 18865 2636 40 21541 5425 b/firefly-rk3288/spl/u-boot-spl after: 18865 2624 40 21529 5419 b/firefly-rk3288/spl/u-boot-spl Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefan Roese <sr@denx.de>
* | configs: k2l_evm: add random eth address supportMugunthan V N2016-08-081-0/+2
| | | | | | | | | | | | | | | | | | There is only one ethernet mac address in e-fuse, but there are multiple slaves in keystone net, so enable random mac address support. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | configs: k2e_evm: add random eth address supportMugunthan V N2016-08-081-0/+2
| | | | | | | | | | | | | | | | | | There is only one ethernet mac address in e-fuse, but there are multiple slaves in keystone net, so enable random mac address support. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | configs: k2hk_evm: add random eth address supportMugunthan V N2016-08-081-0/+2
| | | | | | | | | | | | | | | | | | There is only one ethernet mac address in e-fuse, but there are multiple slaves in keystone net, so enable random mac address support. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | drivers: net: keystone_net: add support for multi slave ethernetMugunthan V N2016-08-081-45/+177
| | | | | | | | | | | | | | | | | | Keystone net can have multiple ethernet slaves, currently only slave 1 is supported by the driver. Register multiple slaves as individual ethernets to network framework. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | drivers: net: keystone_net: fix line termination with semi-colonMugunthan V N2016-08-081-3/+3
| | | | | | | | | | | | | | | | | | Each line should be terminated by semi-colon. It was not caught earlier as there is a proper statement. Fix it by changing the comma with semi-colon. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: dts: dra72-evm: Add mode-gpios entry for mac nodeVignesh R2016-08-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | On DRA72 EVM, cpsw slave1 is muxed with VIN2A, hence switch to cpsw slave0 for ethernet. This is controlled by pcf gpio line. Add appropriate mode-gpios DT entry so that driver can select the required slave. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* | net: cpsw: Add support to drive gpios for ethernet to be functionalVignesh R2016-08-081-0/+12
| | | | | | | | | | | | | | | | | | | | | | On DRA72 EVM, cpsw slaves may be muxed with other modules. This selection is controlled by a pcf gpio line. Add support for cpsw driver to acquire mode-gpios and select the appropriate slave using gpio APIs. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* | ARM: dts: dra7xx: Add u-boot specific property for PCF8575 nodesVignesh R2016-08-082-0/+3
| | | | | | | | | | | | | | | | | | | | PCF8575 does not have any registers hence, offset field needs to be ignored for i2c read/write. Therefore populate u-boot,i2c-offset-len with 0 in PCF8575 DT nodes. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: dra7xx_evm: Enable support for TI PCF8575Vignesh R2016-08-082-0/+2
| | | | | | | | | | | | | | | | | | | | On DRA7, pcf chip present at address 0x21 on i2c1, is used to switch between cpsw slave0 and slave1. Hence, enable PCF driver for the same. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | gpio: Add driver for TI PCF8575 I2C GPIO expanderVignesh R2016-08-084-0/+259
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TI's PCF8575 is a 16-bit I2C GPIO expander.The device features a 16-bit quasi-bidirectional I/O ports. Each quasi-bidirectional I/O can be used as an input or output without the use of a data-direction control signal. The I/Os should be high before being used as inputs. Read the device documentation for more details[1]. This driver is based on pcf857x driver available in Linux v4.7 kernel. It supports basic reading and writing of gpio pins. [1] http://www.ti.com/lit/ds/symlink/pcf8575.pdf Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* | spl_nor.c: Support devicetree sizes different from 16kMike Looijmans2016-08-083-2/+4
|/ | | | | | | | | The devicetrees for various platforms already exceed 16k. Add a define CONFIG_SYS_FDT_SIZE to specify the FDT size, and set to 16k for the two boards that define this CONFIG_SYS_FDT_BASE parameter. This allows platforms with larger devicetree blobs to boot from NOR. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
* spi: cadence_qspi_apb: Ensure baudrate doesn't exceed max valueChin Liang See2016-08-071-2/+5
| | | | | | | | | | | | | | | | Ensuring the baudrate divisor value doesn't exceed the max value in the calculation.It will be capped at max value to ensure the correct value being written into the register. Example of the existing bug is when calculated div = 16. After and with the mask, the value written to register is actually 0 (register field for baudrate divisor). With this fix, the value written is now 15 which is max value for baudrate divisor. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jteki@openedev.com> Cc: Dinh Nguyen <dinguyen@altera.com>
* ARM: socfpga: use the default CONFIG_BOOTDELAY=2Masahiro Yamada2016-08-078-8/+0
| | | | | | | | This option controls how long it should be paused before entering the auto-boot mode. The default value from Kconfig should be fine except socfpga_vining_fpga_defconfig. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge git://git.denx.de/u-boot-rockchipTom Rini2016-08-0631-29/+1901
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| * rockchip: remove log2 reimplementation from clock driversHeiko Stübner2016-08-052-14/+6
| | | | | | | | | | | | | | | | | | The already available ilog2 function does exactly the same in the common case than the log2 function the current clock-driver reimplement. So, simply move to that one. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
| * config: rk3399: enable dwmmc controllerKever Yang2016-08-052-0/+2
| | | | | | | | | | | | | | Enable the rockchip dwmmc driver for rk3399 and its evb. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * dts: rk3399: enable dwmmc for sdcardKever Yang2016-08-052-2/+6
| | | | | | | | | | | | | | | | | | rk3399 sdcard is using dwmmc controller, enable it for sdcard. SCLK_SDMMC is the clock for controller operation clock, move it to the first place. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * clock: rk3399: add support for dwmmc 400KKever Yang2016-08-051-8/+21
| | | | | | | | | | | | | | | | | | MMC core will use 400KHz for card initialize first and then switch to higher frequency like 50MHz, we need to support both 400KHz and about 50MHz for dwmmc controller. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * configs: rk3399: add gpt and fs supportKever Yang2016-08-051-0/+14
| | | | | | | | | | | | | | | | | | To compatible with distro boot, we need to add gpt and fs support, including gpt table and vfat, ext2, ext4 support. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: add usb mass storage feature support for rk3288Xu Ziyuan2016-08-051-0/+4
| | | | | | | | | | | | | | | | Enable ums feature for rk3288 boards, so that we can mount the mmc device to PC. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: add basic partitions support for rk3288Xu Ziyuan2016-08-051-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For compatibility with distro boot, fastboot, and mount the mmc deivce to PC via usb mass storage feature, GPT partitions are essential. You should write the partitions to mmc device prior to use above feature. => gpt write mmc 1 $partitions GPT successfully written to block device! success! Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: add support for rk3288 miniarm boardXu Ziyuan2016-08-0511-6/+746
| | | | | | | | | | | | | | | | Miniarm is a rockchip rk3288 based development board, which has lots of interface such as HDMI, USB, micro-SD card, Audio etc. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * move: rockchip: move clock drivers into a subdirectoryHeiko Stübner2016-08-055-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | With the number of Rockchip clock drivers increasing, don't clutter up the core drivers/clk directory with them and instead move them out of the way into a separate subdirectory. Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org> Updated for rk3399: Signed-off-by: Simon Glass <sjg@chromium.org>
| * rk3399: add basic soc driverKever Yang2016-08-056-0/+980
| | | | | | | | | | | | | | | | | | | | This patch add driver for: - clock driver including set_rate for cpu, mmc, vop, I2C. - sysreset driver - grf syscon driver Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: rockchip, sdram-channel 0xff fix remaining dtsSandy Patterson2016-08-052-2/+2
| | | | | | | | | | | | | | Add an extra byte so that this data is not byteswapped. Signed-off-by: Sandy Patterson <apatterson@sightlogix.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: add fastboot support for rk3036 boardXu Ziyuan2016-08-054-3/+112
| | | | | | | | | | | | | | | | Enable fastboot feature on rk3036, please refer to doc/README.rockchip for more detailed usage. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | zynq_sdhci.c: Fix warning in arasan_sdhci_probeTom Rini2016-08-051-2/+0
| | | | | | | | | | | | | | | | | | We no longer need to set 'caps' as it's not passed to sdhci_setup_cfg anymore. Fixes: 14bed52d276a ("mmc: sdhci: remove the unnecessary arguments for sdhci_setup_cfg") Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2016-08-0511-32/+1698
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| * | ARM: tegra: call tegra_board_init on Tegra186Stephen Warren2016-08-041-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce tegra_board_init() and call it from board_init(). Tegra wil use tegra_board_init() for board-specific initialization, and board_init() for SoC-specific initialization. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: add I2C controllers to Tegra186 DTBryan Wu2016-08-041-0/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra186 has 8 I2C controllers including BPMP I2C. This patch adds the other 7 generic controllers to Tegra186's DT. Signed-off-by: Bryan Wu <pengw@nvidia.com> (swarren, fixed DT node sort order, tweak patch description) Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: add PCIe controller to Tegra186 SoC DTStephen Warren2016-08-041-0/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra186 PCIe DT content is almost identical to previous chips, except that the: - There are 3 ports instead of 2. - Some physical addresses have moved. - PHY programming is handled by firmware, so CCPLEX DTs don't need to reference any PHY. - The power domain is explicitly represented in DT. This change is mandatory for Tegra186 since standard power domain APIs are used, and should be made to the DT for older SoCs, although we get away without doing so since U-Boot currently uses custom APIs that hard-code power domain IDs. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: add BPMP I2C to Tegra186 device treeStephen Warren2016-08-041-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | This allows the BPMP I2C device to be instantiated, which makes it available to other drivers and the user. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
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