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| * mmc: tmio: Simplify pinmux handlingMarek Vasut2018-11-021-19/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SD UHS SDR12, SDR25, SDR50, SDR104, DDR50 and MMC HS200, HS400 modes all use 1.8V signaling, while all the legacy modes use 3.3V signaling. While there are extra modes which use 1.2V signaling, the existing hardware does not support those. Simplify the pinmux such that 3.3V signaling implies legacy mode pinmux and the rest implies UHS mode pinmux. This prevents the massive case statement from growing further. Moreover, it fixes an edge case where during SD 1.8V switch, the bus mode is still set to default while the signaling is already set to 1.8V, which results in an attempt to communicate with a 1.8V card using pins in 3.3V mode and thus communication failure. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: rmobile: Generate fitting mem_map on Gen3Marek Vasut2018-11-022-1/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch "ARM: rmobile: Mark 4-64GiB as DRAM on Gen3" marked the entire 64bit DRAM space as cachable. On CortexA57, this might result in odd side effects, where the CPU tries to prefetch from those areas and if there is no DRAM backing them, CPU bus hang can happen. This patch fixes it by generating the mem_map structure based on the actual memory layout obtained from the DT, thus not marking areas without any DRAM behind them as cachable. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Fixes: c1ec34763811d ("ARM: rmobile: Mark 4-64GiB as DRAM on Gen3") Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * pinctrl: renesas: Add POCCTRL handling to r8a77990Marek Vasut2018-11-021-2/+32
| | | | | | | | | | | | | | | | | | Add definition of the POCCTRL register and bits therein to R8A77990 E3 pincontrol driver. This allows the pincontrol driver to configure SDHI pin voltage according to power-source DT property. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * pinctrl: renesas: Fix DRV register offsetMarek Vasut2018-11-021-1/+1
| | | | | | | | | | | | | | | | | | Use fixed 4bit size for generating the DRV register element mask, not the size of the value, which can be smaller. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | Merge tag 'mips-fixes-for-v2018.11' of git://git.denx.de/u-boot-mipsTom Rini2018-11-034-30/+40
|\ \ | | | | | | | | | | | | | | | - replace the dynamic size of the relocation table with a fixed but configurable size - fixes non-working CONFIG_OF_SEPARATE=y due to invalid _end symbol
| * | MIPS: make size of relocation table fixed but configurableDaniel Schwierzeck2018-11-024-30/+40
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the size of the relocation table will be shrunk to the actual size needed. Although this gives a maximal space saving, it messes up the _end symbol. This breaks features like appended DTBs because the _end symbol doesn't point to the real end of the U-Boot binary. Remove the size shrinking and make the size of the relocation table fixed but configurable. This follows the Linux approach and the user can adjust the size to his needs. Also rename the relocation table section from .rel to .data.reloc to follow the Linux approach and to avoid ambiguities with the .rel.* sections added by the linker. Reported-by: Lars Povlsen <lars.povlsen@microsemi.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | Merge tag 'arc-for-2018.11' of git://git.denx.de/u-boot-arcTom Rini2018-11-0211-33/+180
|\ \ | | | | | | | | | | | | | | | | | | Just 2 non-functinal changes: 1. Rename of EMDK to EMSDP so it matches real marketing name 2. Add essential README for IoTDK
| * | iot_dk: Add READMEAlexey Brodkin2018-11-011-0/+145
| | | | | | | | | | | | Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | emdk->emsdp: Rename boardAlexey Brodkin2018-11-0110-33/+35
| |/ | | | | | | | | | | | | | | Real marketing name of the board was recently updated so to accommodate that change renaming the board and all related to it. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | arm: ti: boot: Don't read environment partitionSam Protsenko2018-11-011-1/+0
| | | | | | | | | | | | | | | | | | This part should've been remove in commit 88d60db01168 ("arm: ti: boot: Remove environment partition"), but I missed it somehow. Remove reading dtb file from environment partition on eMMC, as we don't have it anymore. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
* | test: tee: fix resource leak in dm_test_tee()Jens Wiklander2018-11-011-9/+26
| | | | | | | | | | | | | | Fixes possible resource leak in dm_test_tee() reported by Coverity. Reported-by: Coverity (CID: 184175) Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
* | cmd: remove CONFIG_SOURCE support in MakefilePatrick Delaunay2018-11-011-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | This line is no more needed and can be removed. Only CONFIG_CMD_SOURCE is defined in Kconfig and used in defconfig files. CONFIG_SOURCE if not defined in source code and "config SOURCE" is not present in any Kconfig. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* | power: spl: add SPL_DM_REGULATOR_GPIO in KconfigLokesh Vutla2018-11-011-1/+8
| | | | | | | | | | | | | | The Makefile already tests for SPL_DM_REGULATOR_GPIO, but Kconfig does not provide it. This adds SPL_DM_REGULATOR_GPIO to Kconfig. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | cmd: remoteproc: Fix the base of strtoul for ID conversion from 3 to 10Keerthy2018-11-011-2/+2
| | | | | | | | | | | | | | Currently the base is 3 fix it 10 so that IDs follow decimal system. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Lokesh Vutla <lokeshvulta@ti.com>
* | configs: sama5d2_ptc_ek: read environment from FATAndrei.Stefanescu@microchip.com2018-11-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | On our demo setup for SD card boot, the u-boot environment is in a FAT partition. This patch changes the default configuration, specifing that the u-boot environment is in a FAT partition instead of raw MMC. Signed-off-by: Andrei Stefanescu <andrei.stefanescu@microchip.com> Acked-by: Eugen Hristev <eugen.hristev@microchip.com>
* | configs: at91: at91sam9x5ek: fix bootcmd for NAND flashEugen.Hristev@microchip.com2018-11-011-2/+3
| | | | | | | | | | | | | | | | | | The default bootcommand needs to be accurate w.r.t the nand memory map at http://www.at91.com/linux4sam/bin/view/Linux4SAM/AT91sam9x5ekMainPage#NAND_Flash_demo_Memory_map Updated to load kernel + dtb at right offsets and boot the zImage. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
* | w1: fix data abort if no one wire bus master presentMartin Fuzzey2018-11-011-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When the "w1 bus" command is used with no bus master present a data abort may occur. This is because uclass_first_device() returns zero, but sets the output struct udevice pointer to NULL in the no device found case. Fix w1_get_bus() to account for this and return an error code as is expected by the callers. Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group> Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com>
* | w1-eeprom: ds24xxx: fix data abort in ds24xxx_probe()Martin Fuzzey2018-11-011-1/+1
|/ | | | | | | | | | | | | Data abort was occurring when using "w1 bus" with a DS24B33 present. The abort occurred in the ds24xxx_probe() because the struct w1_device pointer was NULL. This is because that structure is allocated by the parent device uclass (by .per_child_platdata_auto_alloc_size) and thus the correct accessor is dev_get_parent_platdata() not dev_get_platdata() Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group> Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com>
* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2018-10-314-3/+16
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| * arm: socfpga: imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITIONSimon Goldschmidt2018-10-311-1/+1
| | | | | | | | | | | | | | | | Using imply for SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION instead of select ensures we can build without partition support (used to build a network boot only version of SPL and U-Boot). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * arm: socfpga: Fix bootcounter located at the end of internal SRAMStefan Roese2018-10-311-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 768f23dc8ae3 ("ARM: socfpga: Put stack at the end of SRAM") broke those socfpga boards that keep the bootcounter at the end of the internal SRAM as the bootcounter needs 8 bytes by default and thus the very first SPL call to board_init_f_alloc_reserve overwrites the bootcounter. This patch allows to move the initial stack pointer down a bit by checking if CONFIG_SYS_BOOTCOUNT_ADDR is located in the internal SRAM area and then using this address as location for the start of the stack pointer. No new macros / defines are added by this approach. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * arm: socfpga: fpga: fix type of local variableSimon Goldschmidt2018-10-312-2/+2
| | | | | | | | | | | | | | | | The 'status' variable in 'socfpga_load()' for both gen5 and arria10 is of type 'unsigned long' while it is always used as 'int' only. Change it to 'int'. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* | Merge tag 'mpc85xx-for-v2018.11' of git://git.denx.de/u-boot-mpc85xxTom Rini2018-10-309-7/+65
|\ \ | |/ |/| | | | | | | | | Workaround and bug fix for Freescale PowerPC Add workaround for Freescale USB erratum A005275. Correct RCW macros for T1080.
| * powerpc: t1040: Correct RCW EC2 settingsBin Meng2018-10-292-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Per T1040RM (Rev. 1, 08/2015), there are 2 issues with the RCW EC2 settings. - The value of FSL_CORENET_RCWSR13_EC2_FM1_GPIO is wrong and should be 0x04000000 (value of 1 in RCW bit [420:421]) - Value of 2/3 are reserved in RCW bit [420:421], hence there is no macro FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * powerpc: t1040: Correct RCW MAC2_GMII_SEL valueBin Meng2018-10-291-1/+1
| | | | | | | | | | | | | | | | | | | | Per T1040RM (Rev. 1, 08/2015), the value of FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT is wrong and should be 0x00000080 (bit 440 in the RCW). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl/usb: Workaround for USB erratum-A005275Chris Packham2018-10-297-1/+63
|/ | | | | | | | | | | | | | | | | | | Workaround makes FS as default mode on all affected socs. Add support to check erratum-A005275 validity for an soc. This info is required to determine whether a given soc is affected by this erratum. Add quirk for this erratum "has_fsl_erratum_a005275" . This quirk is used to enable workaround for the errata Force FS mode as default by: - making EPS as FS - setting PFSC bit to disable HS chirping This workaround can be disabled by mentioning "no_erratum_a005275" in hwconfig string Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Prepare v2018.11-rc3v2018.11-rc3Tom Rini2018-10-291-1/+1
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2018-10-2911-39/+120
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| * sunxi: store DRAM size in SPL headerAndre Przywara2018-10-292-2/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we rely on the infamous get_ram_size() function to learn the actual DRAM size in U-Boot proper. This function has two issues: 1) It only works if the DRAM size is a power of two. We start to see boards which have 3GB of (usable) DRAM, so this does not fit anymore. 2) As U-Boot has no notion of reserved memory so far, it will happily ride through the DRAM, possibly stepping on secure-only memory. This could be a region of DRAM reserved for OP-TEE or some other secure payload, for instance. It will most likely crash in that case. As the SPL DRAM init routine has very accurate knowledge of the actual DRAM size, lets propagate this wisdom to U-Boot proper. We re-purpose a currently reserved word in our SPL header for that. The SPL itself stores the detected DRAM size there, and bumps the SPL header version number in that case. U-Boot proper checks for a valid SPL header and a high enough version number, then uses the DRAM size from there. If the SPL header field is not sufficient, we fall back to the old DRAM scanning routine. Part of the DRAM might be present and probed by SPL, but not accessible by the CPU. They're restricted in the main U-Boot binary, when accessing the DRAM size from SPL header. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: add Kconfig option for the maximum accessible DRAMIcenowy Zheng2018-10-291-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allwinner 64-bit SoCs can use 4GiB DRAM chip, however their memory map has only allocated 3GiB for DRAM, so only 3GiB of the DRAM is accessible. Add a Kconfig option for the maximum accessible DRAM. For A80 it should be a much higher value (8GiB), but as I have no A80 device to test and originally U-Boot only supports 2GiB DRAM on A80, it currently still falls under the 2GiB situation. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: map DRAM part with 3G sizeIcenowy Zheng2018-10-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | All Allwinner 64-bit SoCs now are known to be able to access 3GiB of external DRAM, however the size of DRAM part in the MMU translation table is still 2GiB. Change the size of DRAM part in MMU table to 3GiB. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: board.c: refactor SPL header checksAndre Przywara2018-10-291-11/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | So far we have two users which want to look at the SPL header. We will get more in the future. Refactor the existing SPL header checks into a common function, to simplify reusing the code. Now that this is easy, add proper version checks to the DT name parsing. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com>
| * sunxi: Extend SPL header versioningAndre Przywara2018-10-292-7/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Allwinner SoCs we use some free bytes at the beginning of the SPL image to store various information. We have a version byte to allow updates, but changing this always requires all tools to be updated as well. Introduce the concept of semantic versioning [1] to the SPL header: The major part of the version number only changes on incompatible updates, a minor number bump indicates backward compatibility. This patch just documents the major/minor split, adds some comments to the header file and uses the versioning information for the existing users. [1] https://semver.org Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com>
| * sunxi: disable Pine A64 model detection code on other boardsIcenowy Zheng2018-10-293-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Pine A64 Plus/non-Plus model detection code is now built on all 64-bit ARM SoCs, even if the code cannot be triggered when H5/H6 is in use. Disable them when the board is Pine A64 by adding a Kconfig option that is only selected on Pine A64. On GCC 7.3.1 this makes the size of the function reduces 184 bytes, and saves a 104 byte strstr() function, then makes SPL on H6 succeed to build. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: display: Mark sunxi_rgb2yuv_coef array as constPriit Laes2018-10-241-1/+1
| | | | | | | | | | | | | | | | | | sunxi_rgb2yuv_coef is readonly and never modified. Signed-off-by: Priit Laes <plaes@plaes.org> Acked-by: Anatolij Gustschin <agust@denx.de> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: docs: Mention CONFIG_NAND requirementPriit Laes2018-10-241-3/+3
| | | | | | | | | | | | Signed-off-by: Priit Laes <plaes@plaes.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: Fix typos of spelling AllwinnerPriit Laes2018-10-243-3/+3
| | | | | | | | | | | | Signed-off-by: Priit Laes <plaes@plaes.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * pwm: sunxi: choose best prescaler to improve PWM resolutionVasily Khoruzhick2018-10-241-13/+19
| | | | | | | | | | | | | | | | | | | | | | Choose best prescaler to improve PWM resolution. Without this change driver chooses first prescaler that gives us period value within range, but it could be not the best one. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Tested-by: Vagrant Cascadian <vagrant@debian.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * pwm: sunxi: use new prescaler when configuring PWMVasily Khoruzhick2018-10-241-1/+1
| | | | | | | | | | | | | | | | Looks like old prescaler was used when configuring PWM, fix it. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * pwm: sunxi: fix off-by-one that prevented PWM to use prescaler bypassVasily Khoruzhick2018-10-241-1/+1
| | | | | | | | | | | | | | | | | | Fix off-by-one that prevented PWM driver to use prescaler bypass. Without this change prescaler is always enabled. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | Merge git://git.denx.de/u-boot-x86Tom Rini2018-10-286-28/+36
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| * | x86: Fix car_uninit weak symbol definitionBin Meng2018-10-281-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 80df194f0165 ("x86: detect unsupported relocation types"), an error message is seen on QEMU x86 target during boot: do_elf_reloc_fixups32: unsupported relocation type 0x1 at fff841f0, offset = 0xfff00087 do_elf_reloc_fixups32: unsupported relocation type 0x2 at fff841f8, offset = 0xfff00091 Check offset 0xfff00087 and 0xfff00091 in the u-boot ELF image, fff00087 000df401 R_386_32 00000000 car_uninit fff00091 000df402 R_386_PC32 00000000 car_uninit we see R_386_32 and R_386_PC32 relocation type is generated for symbol car_uninit, which is declared as a weak symbol in start.S. However the actual weak symbol implementation ends up nowhere. As we can see below, it's *UND*. $ objdump -t u-boot | grep car_uninit 00000000 w *UND* 00000000 car_uninit With this fix, it is normal now. $ objdump -t u-boot | grep car_uninit fff00094 w F .text.start 00000001 car_uninit Reported-by: Hannes Schmelzer <hannes@schmelzer.or.at> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>
| * | x86: theadorable-x86-xxx_defconfig: Move VGA BIOS to make room for U-BootStefan Roese2018-10-283-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | The build breaks because its not fitting the U-Boot binary into the ROM image. So lets move VGA BIOS a bit to make room for the grown U-Boot binary. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: theadorable-x86: Generate and pass root=PARTUUID instead of /dev/sdaXStefan Roese2018-10-283-14/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To enable the root device selection (kernel cmd-line) via PARTUUID, this patch enables CMD_PART on all missing theadorable-x86 boards and changes the default environment to generate the root=PARTUUID string automatically. This fixes problems that have been noticed on systems with multiple SATA/AHCI controller connected via PCIe, where the device name for the root device / partition (/dev/sdaX) was incorrect. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: theadorable-x86-common: Change pci hotplug cmdline parameters (again)Stefan Roese2018-10-281-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is needed for the PCIe hotplug to work correctly on some boards with the newer Linux kernel versions. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: BayTrail: southcluster.asl: Change PCI 64 bit address range / regionStefan Roese2018-10-281-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To allow bigger 64 bit prefetchable PCI regions in Linux, this patch changes the base address and range of the ACPI area passed to Linux. BayTrail can only physically access 36 bit of PCI address space. So just chaning the range without changing the base address won't work here, as 0xf.ffff.ffff is already the maximum address. With this patch, a maximum of 16 GiB of local DDR is supported. This should be enough for all BayTrail boards though. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | drivers: cosmetic: Convert SPDX license tags to Linux Kernel stylePatrick Delaunay2018-10-2824-38/+32
|/ / | | | | | | | | | | | | | | | | Complete in the drivers directory the work started with commit 83d290c56fab ("SPDX: Convert all of our single license tags to Linux Kernel style"). Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* | vf610twr: Enable thumb2 for buildsTom Rini2018-10-262-0/+4
| | | | | | | | | | | | To help with size constraints, enable thumb2 when building. Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2018-10-2563-86/+446
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| * | net: fec_mxc: add support for i.MX8XAnatolij Gustschin2018-10-243-4/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add compatible property and enable the FEC ipg clock when probing on i.MX8X. Add specific function for reading FEC clock rate via clock driver when configuring MII speed register. Allow FEC_MXC selection for i.MX8. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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