summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeFilesLines
* ARM: rockchip: rv1108: Add support for default distro_bootcmdOtavio Salvador2018-11-302-0/+18
| | | | | | | | | | | This allow easier integration of RV1108 based boards on generic distributions and build systems. To avoid behavior change, we make evb-rv1108 to use the existing environment as it boots from its SPI NOR. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* ARM: dts: rockchip: Add rv1108 USB OTG pinctrlOtavio Salvador2018-11-301-3/+42
| | | | | | | | | This adds the definitions need to use the USB OTG in rv1108 board. This has been tested using USB Mass Storage to export and program a eMMC device. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* ARM: rockchip: rv1108: Add a board_usb_init for USB OTGOtavio Salvador2018-11-302-0/+82
| | | | | | | | Like it is done for other Rockchip SoCs, introduce a board_usb_init() function so that USB OTG can be functional on rv1108 too. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* ARM: dts: rockchip: Add rv1108 eMMC pinctrlOtavio Salvador2018-11-301-0/+29
| | | | | | | | This adds the pinctrl handles to enable the use of eMMC on custom boards (as minievk) and makes it easier for later addition. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* ARM: rockchip: rv1108: Enable BOUNCE_BUFFEROtavio Salvador2018-11-301-0/+3
| | | | | | | | | | In order to be able to build the Rockchip eMMC driver on rv1108, the BOUNCE_BUFFER option needs to be selected. Select it like it is done on the other Rockchip SoC common files. Reviewed-by: Andy Yan <andy.yan@rock-chips.com> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* ARM: rockchip: rv1108: Sync clock with vendor treeOtavio Salvador2018-11-304-33/+729
| | | | | | | | Make adjustments to the rv1108 clock driver in order to align it with the internal Rockchip version. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: rk3399-puma: reduce sd card max-frequency to 40MHzPhilipp Tomsich2018-11-301-1/+1
| | | | | | | | | | | | | | | | Some SanDisk Ultra cards trigger intermittent errors on detection resulting in an -EOPNOTSUPP, when running at 50MHz. Waveform analysis suggest that the level shifters that are used on the RK3399-Q7 module (for voltage translation between the on-module voltages and the 3.3V required on the card-edge) don't handle clock rates at or above 48MHz properly. This change reduces the maximum frequency on the external SD-interface to 40MHz (for a safety margin of 20%). Reported-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
* rockchip: rock: remove TPL_TINY_MEMSETKever Yang2018-11-301-1/+0
| | | | | | | | | | The RK3188 rock board does not need TPL: remove TPL_TINY_MEMSET from config. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [Fixed up commit message:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: rk3399: spl: always report errors triggering a hard stopPhilipp Tomsich2018-11-301-2/+2
| | | | | | | | | | | | The RK3399 SPL has two cases that may end in a hard-stop: if either the pinctrl can not be initialised or if the DRAM fails to initialise. Both have previously not triggered an error message unless DEBUG was defined (i.e. both used debug() to print the error). This converts both error messages to be printed using pr_err() to ensure that some output points to the cause of the hard-stop. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: video: mipi: Fix phy frequency settingRichard Röjfors2018-11-301-1/+1
| | | | | | | | | | There was an incorrect check when looping and finding the first fast enough frequency in the freq_rang table. The code did actually return the first that was either exactly correct or too slow. Signed-off-by: Richard Röjfors <richard@puffinpack.se> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: video: mipi: Do not write to the version registerRichard Röjfors2018-11-301-1/+1
| | | | | | | | There was a copy and paste error where the data enable setting was written to the version register. Signed-off-by: Richard Röjfors <richard@puffinpack.se> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: rk3188: fix early uart setupHeiko Stuebner2018-11-301-0/+10
| | | | | | | | | | | | | | Commit 7a6d7d3e1279 ("rockchip: pinctrl: rk3188: Move the iomux definitions into pinctrl-driver") moved the iomux settings out of the grf header to prevent conflicts with the iomux definitions of other rockchip socs. This also breaks the early uart setup, as the iomux for uart2 are needed. To fix that just put the tiny amount of needed iomux definitions next to the early uart code. Fixes: 7a6d7d3e1279 ("rockchip: pinctrl: rk3188: Move the iomux definitions into pinctrl-driver") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: rk3188: add support for usb-uart functionalityHeiko Stuebner2018-11-303-4/+73
| | | | | | | | | | | Rockchip socs can route the debug uart pins through the d+ and d- pins of one specific usbphy per soc. Add a config option and implement the setting on the rk3188. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [Fixed up to mark grf as maybe unused:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2018-11-2931-341/+1264
|\
| * arm: socfpga: fix SPL booting from fpga OnChip RAMSimon Goldschmidt2018-11-294-4/+25
| | | | | | | | | | | | | | This patch prevents disabling the FPGA bridges when SPL or U-Boot is executed from FPGA onchip RAM. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * arm: socfpga: make socfpga_socrates_defconfig boot from QSPISimon Goldschmidt2018-11-291-0/+2
| | | | | | | | | | | | | | | | | | This fixes the board's dts to supply SPL with QSPI info. The EBV Socrates board has DIP switches to boot from SD card or QSPI, so let's fix its defconfig to work for both cases. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * dts: arm: socfpga: merge gen5 devicetrees from linuxSimon Goldschmidt2018-11-2920-329/+1222
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add -u-boot.dtsi files to keep the current U-Boot behaviour: - add u-boot,dm-pre-reloc where required - disable watchdog - set uart clock frequency - add gpio bank-name properties where appropriate: - make qspi work (add alias for spi0, fix compatible for flash) - enable usb (status okay, add alias for udc0) Adapt board dts files that are not in Linux to keep their old behaviour. Change licenses to SPDX. (Patman warnings/errors are in 1:1 copied files from Linux) Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * spi: cadence_qspi: use "cdns,qspi-nor" as compatibleSimon Goldschmidt2018-11-296-6/+6
| | | | | | | | | | | | | | Linux uses "cdns,qspi-nor" as compatible string for the cadence qspi driver, so change driver, docs and all device trees. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * gpio: dwapb_gpio: fix binding without bank-name propertySimon Goldschmidt2018-11-291-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As a preparation for merging the socfpga gen5 devicetree files from Linux, this patch makes the dwapb gpio driver work correctly without the 'bank-name' property on the gpio-controller nodes. This property is not present in the Linux drivers and thus is not present in the Linux devicetrees. It is only used to access pins via bank name. This fallback is necessary since without it, the driver will return an error code which will lead to an error in U-Boot startup. The bank names will still be added to the default board device trees in follow-up patch, but other boards using this driver and not including the bank name should also work with the socfpga.dtsi without adding the bank-name property. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * arm: socfpga: make config structs constSimon Goldschmidt2018-11-291-2/+2
| | | | | | | | | | | | | | There are two config structs left in wrap_sdram_config.c that can be made const. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* | Merge tag 'u-boot-amlogic-20181126' of git://git.denx.de/u-boot-amlogicTom Rini2018-11-2986-754/+5172
|\ \ | | | | | | | | | | | | | | | | | | Cleanup and update towards support for Amlogic Meson AXG SoCs : - mmc: meson-gx: Add AXG compatible - net: designware: add meson meson compatibles - Amlogic Meson cleanup for AXG SoC support
| * | ARM: meson: Add boot device discoveryNeil Armstrong2018-11-268-0/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Amlogic Meson SoCs ROM supports a boot over USB with a custom protocol. When no other boot medium are available (or by forcing the USB mode), the ROM sets the primary USB port as device mode and waits for a Host to enumerate. When enumerated, a custom protocol described at [1] permits writing to memory and execute some specific FIP init code to run the loaded Arm Trusted Firmware BL2 and BL3 stages before running the BL33 stage. In this mode, we can load different binaries that can be used by U-boot like a script image file. This adds support for a custom USB boot stage only available when the boot mode is USB and the script file at a pre-defined address is valid. This support was heavily copied from the Sunxi Allwinner FEL U-Boot support. The tool pyamlboot described at [2], permits using this boot mode on boards exposing the first USB port, either as OTG or Host port. [1] https://github.com/superna9999/pyamlboot/blob/master/PROTOCOL.md [2] https://github.com/superna9999/pyamlboot/blob/master/README.md Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | ARM: meson: factorize common code out amlogic's boardsJerome Brunet2018-11-265-48/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now we have moved all the Amlogic board support to common generic board code, we can move the identical board_init() and ft_board_setup() functions to weak functions into the board-common mach-meson file. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | board: amlogic: add support for S400 boardNeil Armstrong2018-11-266-0/+194
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The S400 board is the Amlogic AXG SoC reference board including : - Amlogic A113DX ARM Cortex-A53 quad-core SoC @ 1.2GHz - 1GB DDR4 SDRAM - 10/100 Ethernet - 2 x USB 2.0 Host - eMMC - Infrared receiver - SDIO WiFi Module - MIPI DSI Connector - Audio HAT Connector - PCI-E M.2 Connectors Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | clk: Add clock driver for AXGNeil Armstrong2018-11-263-1/+421
| | | | | | | | | | | | | | | | | | | | | This patch adds a minimal clock driver for the Amlogic AXG SoC to handle the basic gates and PLLs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | ARM: dts: Sync Amlogic Meson AXG DT from Linux 4.20-rc1Neil Armstrong2018-11-2610-1/+2618
| | | | | | | | | | | | | | | | | | | | | | | | | | | Synchronize the Amlogic AXG Device Tree files and bindings include from the recent Linux 4.20-rc1, because it includes patches fixing support for U-boot. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | ARM: meson: Add support for AXG familyNeil Armstrong2018-11-265-0/+177
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the Amlogic AXG SoC, which is very close from the Amlogic GXL SoCs with : - Same 4xCortex-A53 CPUs but clocked at 1.2GHZ max - DDR Interface limited to DDR4 16bit - The whole physical register address space has been moved to 0xfxxxxxxx - The pinctrl setup has changed - The clock tree is different enough to use a different driver Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | ARM: meson: rework soc arch file to prepare for new SoCJerome Brunet2018-11-2613-125/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | We are about to add support for the Amlogic AXG SoC. While very close to the Gx SoC family, we will need to handle a few thing which are different in this SoC. Rework the meson arch directory to prepare for this. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | clk: meson: silence debug printJerome Brunet2018-11-261-1/+1
| | | | | | | | | | | | | | | | | | | | | This debug print was not designed to be active in non-debug mode. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | clk: meson: add static to meson_gates tableNeil Armstrong2018-11-261-1/+1
| | | | | | | | | | | | | | | | | | The meson_gates table should be set static in the clk_meson driver. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | pinctrl: meson: add axg supportJerome Brunet2018-11-265-0/+1180
| | | | | | | | | | | | | | | | | | | | | | | | This adds support for the Amlogic AXG SoC pinctrl and GPIO controller using a specific set of pinctrl functions which differs from the GX SoCs. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | pinctrl: meson: select generic pinctrlJerome Brunet2018-11-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Meson pinctrl needs generic pinctrl, rather than depending on it select it Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | pinctrl: meson: rework gx pmx functionJerome Brunet2018-11-268-121/+191
| | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation of supporting the new Amlogix AGX SoCs, we need to move the Amlogic GX pinmux functions out of the common code to be able to add a different set of SoC specific pinmux functions for AXG. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | configs: meson: change default load addressesJerome Brunet2018-11-261-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original chosen addresses conflict with the BL2 initialisation. So far there was no issue with them but if we preload binaries in RAM (ROMUSB boot) before running the BL2 they get corrupted by the execution of BL2 init. If we load them around 0x08000000, there is no such issue. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | ARM: rework amlogic configurationJerome Brunet2018-11-2617-175/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rework the board SYS_BOARD, SYS_VENDOR and SYS_CONFIG_NAME setup by moving the board Kconfig into the mach-meson Kconfig to make it easier to add new boards for a SoC architecture and add a custom config header or custom board handler for a platform. This drops the board CONFIGs and the duplicate boards configs headers in favor of a single meson64.h config header. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | board: amlogic: factorise gxbb boardsJerome Brunet2018-11-269-91/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The nanopi-k2 and the odroid-c2 are similar enough to be supported by the same u-boot board. This change use odroid-c2 u-boot board for the nanopi-k2 as well. Dedicated defconfig are kept to customize the names and device tree. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | board: amlogic: move khadas-vim2 as q200 ref boardNeil Armstrong2018-11-269-12/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | The Khadas vim2 derive from amlogic s912 reference design (Q200). This patch moves the khadas-vim2 board support to a generic Q200 board, while keeping a dedicated defconfig to customize the names and device tree. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | board: amlogic: remove p212 derivativesJerome Brunet2018-11-2614-184/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Khadas vim and the libretech aml-s905x-cc (aka Potato) derive from amlogic s905x reference design (P212). All the code in these board is a copy/paste from the p212, which is tedious to maintain. This change use p212 u-boot board for all these boards, while keeping a dedicated defconfig to customize the names and device tree. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | configs: meson: remove unnecessary MESON_FDTFILE_SETTINGJerome Brunet2018-11-266-17/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MESON_FDTFILE_SETTING is used to define the default name of the fdt file in u-boot environment. We can easily derive it from CONFIG_DEFAULT_DEVICE_TREE instead. This will help factorize the code a bit Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | ARM: meson: clean-up platform selectionJerome Brunet2018-11-261-31/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even if multiple board are selected through Kconfig, u-boot will only compile one. This makes sense since compiling these targets will export global symbols, such as board_init() The change rework amlogic Kconfig so only one board may be selected at a time Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | net: designware: add meson meson axg compatibleNeil Armstrong2018-11-261-0/+1
| | | | | | | | | | | | | | | | | | Add the compatible string for the upcoming Amlogic AXG SoC family. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | net: designware: add meson meson gxbb compatibleNeil Armstrong2018-11-261-0/+1
| | | | | | | | | | | | | | | | | | Add the compatible string for the Amlogic GXBB SoC family. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | mmc: meson-gx: Add AXG compatibleNeil Armstrong2018-11-261-0/+1
| | | | | | | | | | | | | | | | | | Add the compatible string for the upcoming Amlogic AXG SoC family. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | | Merge branch '2018-11-28-master-imports'Tom Rini2018-11-2879-0/+11388
|\ \ \ | |_|/ |/| | | | | - Add MediaTek support
| * | MAINTAINERS: add an entry for MediaTekRyder Lee2018-11-281-0/+20
| | | | | | | | | | | | | | | | | | | | | This patch adds an entry for MediaTek. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | doc: README.mediatek: Add a simple README for MediaTekRyder Lee2018-11-281-0/+221
| | | | | | | | | | | | | | | | | | | | | | | | Add a few notes on how to try out the MediaTek support so far. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | mmc: mtk-sd: add SD/MMC host controller driver for MT7623 SoCWeijie Gao2018-11-283-0/+1406
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds MT7623 host controller driver for accessing SD/MMC. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | ram: MediaTek: add DDR3 driver for MT7629 SoCRyder Lee2018-11-283-0/+774
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds a DDR3 driver for MT7629 SoC. Signed-off-by: Wu Zou <wu.zou@mediatek.com> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | serial: MediaTek: add high-speed uart driver for MediaTek SoCsRyder Lee2018-11-283-0/+289
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many SoCs from MediaTek have a high-speed uart. This UART is compatible with the ns16550 in legacy mode. It has extra registers for high-speed mode which can reach a maximum baudrate at 921600. However this UART will no longer be compatible if it's in high-speed mode. Some BootROM of MediaTek's SoCs will change the UART into high-speed mode and the U-Boot must use this driver to initialize the UART. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> Tested-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | power domain: MediaTek: add power domain driver for MT7623 SoCRyder Lee2018-11-281-0/+80
| | | | | | | | | | | | | | | | | | | | | This adds power domain (scpsys) support for MT7623 SoC. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>
View Lorry Controller Status