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* Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into nextWIP/05Jan2021-nextTom Rini2021-01-051-1/+4
|\ | | | | | | | | | | | | | | | | Driver model: make some udevice fields private Driver model: Rename U_BOOT_DEVICE et al. dtoc: Tidy up and add more tests ns16550 code clean-up x86 and sandbox minor fixes for of-platdata dtoc prepration for adding build-time instantiation
| * spl: Drop bd_info in the data sectionSimon Glass2021-01-051-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | This uses up space in the SPL binary but it always starts as zero. Also some boards cannot support data in TPL (e.g. Intel Apollo Lake). Use malloc() to allocate this structure instead, by moving the init a little later, after malloc() is inited. Make this function optional since it pulls in malloc(). This reduces the TPL binary size on coral by about 64 bytes Signed-off-by: Simon Glass <sjg@chromium.org>
* | Merge tag 'v2021.01-rc5' into nextTom Rini2021-01-059-43/+142
|\ \ | |/ |/| | | | | | | Prepare v2021.01-rc5 Signed-off-by: Tom Rini <trini@konsulko.com>
| * armv8: fsl-layerscape: Fix automatic setting of bootmcd with TF-AAlban Bedel2020-12-101-23/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When booting from TF-A there is a logic that attempt to detect if the default environment is used, if this is the case it then set the `bootcmd` and `mcinitcmd` depending of the device we booted from. This detection logic is dubious as it access internals of the env implementation and it doesn't always work correctly. First of all it detect any valid environment as not being the default, so after running `env default -a && saveenv` the board doesn't boot anymore as `bootcmd` is then empty. But it also fails in some other ways, for example it always detect a default environment when redundant env is enabled on MMC, so in that case `bootcmd` is overwritten on every boot. Instead of increasing the complexity of the detection just check if `bootcmd` and `mcinitcmd` are set in the environment and set them if they are not. Signed-off-by: Alban Bedel <alban.bedel@aerq.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * layerscape: fdt.c: Check for NULL return value from fdt_getprop()Priyanka Singh2020-12-101-4/+6
| | | | | | | | | | | | | | | | | | Check for NULL return value from fdt_getprop() in fdt_fixup_remove_jr() Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com> [Fixed checkpatch errors/warnings] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * armv8: lx2162a: Add Soc changes to support LX2162AMeenakshi Aggarwal2020-12-108-16/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | | LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* | armv8: layerscape: don't initialize GIC in SPLMichael Walle2020-12-041-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The BL31 expects the GIC to be uninitialized. Thus, if we are loading the BL31 by the SPL we must not initialize it. If u-boot is loaded by the SPL directly, it will initialize the GIC again (in the same lowlevel_init()). This was tested on a custom board with SPL loading the BL31 and jumping to u-boot as BL33 as well as loading u-boot directly by the SPL. In case the ATF BL1/BL2 is used, this patch won't change anything, because no SPL is used at all. Signed-off-by: Michael Walle <michael@walle.cc>
* | treewide: use CONFIG_IS_ENABLED() for ARMV8_SEC_FIRMWARE_SUPPORTMichael Walle2020-12-042-5/+5
|/ | | | | | | | There is SPL_ARMV8_SEC_FIRMWARE_SUPPORT and ARMV8_SEC_FIRMWARE_SUPPORT. Thus use CONFIG_IS_ENABLED() instead of the simple #ifdef. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Michal Simek <michal.simek@xilinx.com>
* armv8: layerscape: don't remove crypto node if just partially disabledMichael Walle2020-10-231-1/+40
| | | | | | | | | | | | | | On all newer Layerscape SoCs, only the export-controlled ciphers of the crypto module are disabled on non-E parts. Thus it doesn't make sense to completely remove the node. Linux will figure out what is there and what is not. Just remove it for older SoCs, where the module is indeed completely disabled on non-E parts. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* net: lx2160a.c: Update to set ECx_PMUX precedenceRazvan Ionut Cirjan2020-10-231-8/+8
| | | | | | | | | | | | As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* pci: layerscape: add a way of specifying additional iommu mappingsLaurentiu Tudor2020-10-231-0/+67
| | | | | | | | | | | | | | | | | | | In the current implementation, u-boot creates iommu mappings only for PCI devices enumarated at boot time thus does not take into account more dynamic scenarios such as SR-IOV or PCI hot-plug. Add an u-boot env var and a device tree property (to be used for example in more static scenarios such as hardwired PCI endpoints that get initialized later in the system setup) that would allow two things: - for a SRIOV capable PCI EP identified by its B.D.F specify the maximum number of VFs that will ever be created for it - for hot-plug case, specify the B.D.F with which the device will show up on the PCI bus More details can be found in the included documentation: arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* arm: fsl-layerscape: Include device_compat.h in soc.cTom Rini2020-10-161-0/+1
| | | | | | Necessary for dev_xxx. Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge branch 'next'Tom Rini2020-10-051-1/+1
|\ | | | | | | | | | | | | Bring in the assorted changes that have been staged in the 'next' branch prior to release. Signed-off-by: Tom Rini <trini@konsulko.com>
* | armv8: lx2160a: fix reset sequenceMeenakshi Aggarwal2020-09-241-6/+8
| | | | | | | | | | | | | | | | | | Make sure that SW_RST_REQ and RST_REQ_MSK are cleared before triggering hardware reset request. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | arm64: Layerscape: Survive LPI one-way reset workaroundHou Zhiqiang2020-09-241-1/+16
| | | | | | | | | | | | | | | | | | | | | | The workaround of LPI one-way reset issue is broken by the series: https://patchwork.ozlabs.org/project/uboot/list/?series=192398 This patch is to add DT node for GIC RD tables and create corresponding reserved-memory node in kernel DT to fix it. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | fsl-layerscape: enable dwc3 snooping featureRan Wang2020-09-241-0/+37
|/ | | | | | | | | | Configure DWC3’s cache type to ‘cacheable’ for better performance. Actually related register definition and values are SoC specific, which means this setting is only applicable to Layerscape SoC, not generic for all platforms which have integrated DWC3 IP. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* arch: arm: use dt and UCLASS_SYSCON to get gic lpi detailsWIP/2020-07-29-add-brcm-ns3-supportRayagonda Kokatanur2020-07-291-27/+1
| | | | | | | | | | | | Use device tree and UCLASS_SYSCON driver to get Generic Interrupt Controller (GIC) lpi address and maximum GIC redistributors count. Also update Kconfig to select REGMAP and SYSCON when GIC_V3_ITS is enabled. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm64: ls1043a: Remove the workaround of erratum A-009929Hou Zhiqiang2020-07-272-19/+0
| | | | | | | | The workaround has been implemented in PBI phase, so remove the duplicated implementation from U-Boot. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* I2C: ls1043a, ls1046a: enable SYS_I2C_MXCBiwen Li2020-07-271-2/+2
| | | | | | | | | This enables SYS_I2C_MXC to fix a bug that failed to boot from sd card with image u-boot-with-spl-pbl.bin Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: rework spin tableMichael Walle2020-07-271-60/+23
| | | | | | | | | | | | | | | | | | | | There are two issues: (1) The spin table doesn't convert the endianness of the jump address. Although there is code for it, the result isn't used at all (x0). (2) If something goes wrong, the function returns. But that doesn't make sense at all. Use the actual converted jump address as destination to fix. If there is an error, jump to a trap loop. And rearrange the code exception level switching code to make it smaller and clearer. This reduces the size of the spin table code section from 696 bytes to 424 bytes. If CONFIG_ARMV8_SWITCH_TO_EL1 the code size reduced from 696 bytes to 632 bytes. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: relocate spin table if EFI_LOADER is enabledMichael Walle2020-07-271-0/+36
| | | | | | | | | | | On ARM64, a 64kb region is reserved for the runtime services code. Unfortunately, this code overlaps with the spin table code, which also needs to be reserved. Thus now that the code is relocatable, allocate a new page from EFI, copy the spin table code into it, update any pointers to the old region and the start the secondary CPUs. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: clean exported symbols in spintable.SMichael Walle2020-07-273-18/+21
| | | | | | | | | | | Add a new variable secondary_boot_code_start, which holds a pointer to the start of the spin table code. This will help to relocate the code section. While at it, move the size variable from the end to the beginning so there is a common section for the variables. Remove any other symbols. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: drop first .ltorg directive in spintable.SMichael Walle2020-07-271-2/+0
| | | | | | | | Now that the spin table is in a separate module, this is no longer necessary. Drop it. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: make wake_secondary_core_n() staticMichael Walle2020-07-271-1/+1
| | | | | | | This function is not used outside the module. Make it static. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: simplify get_spin_tbl_addr() callsMichael Walle2020-07-271-8/+7
| | | | | | | | There is no need to cast around. Assign the address to the local variable and use it. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: remove determine_mp_bootpg()Michael Walle2020-07-271-5/+0
| | | | | | | Only the PowerPC architecture needs this function. Remove it. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: fix alignment for spin tableMichael Walle2020-07-271-2/+2
| | | | | | | | Fix the alignment so it will match the comments. The spin table has to be 8 byte aligned, so ".align 3" is enough. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: load function pointer using ADRMichael Walle2020-07-271-3/+3
| | | | | | | | | Don't use LDR to load a pointer to a function. This will generate a literal which cannot be relocated. Use ADR which is PC-relative and therefore can easily be relocated. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: move spin table into own moduleMichael Walle2020-07-273-150/+161
| | | | | | | | | | | Move it out of lowlevel.S into spintable.S. On layerscape, the secondary CPUs are brought up in main u-boot. This will make it possible to only compile the spin table code for the main u-boot and omit it in SPL. This saves about 720 bytes in the SPL. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: properly use CPU_RELEASE_ADDRMichael Walle2020-07-271-2/+12
| | | | | | | | | | | | The generic armv8 code already has support to bring up the secondary cores. Thus, don't hardcode the jump in the layerscape lowlevel_init to the spin table code; instead just return early and let the common armv8 code handle the jump. This way we can actually use the CPU_RELEASE_ADDR feature. Signed-off-by: Michael Walle <michael@walle.cc> [Rebased, Removed kontron_sl28.h change as file does not exist] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: pretty print info about SMP coresMichael Walle2020-07-271-4/+5
| | | | | | | | Make the print of the starting address a debug output and pretty print the info about online cores. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: fix spin-table supportMichael Walle2020-07-272-11/+5
| | | | | | | | | | | | | | | | | | | Spin tables are broken with bootefi. This is because - in contrast to the booti call chain - there is no call to smp_kick_all_cpus(). Due to this missing call the secondary CPUs are never released from their "wait for interrupt state", see secondary_boot_func() in lowlevel.S. Originally, this "wait for interrupt" is there to make sure, the spin table is cleared before the secondary cores read it for the first time. But the boot flow for the layerscape architecture is different from that. The CPUs are release from their BootROM _after_ U-Boot's spin-table is cleared, see fsl_layerscape_wake_seconday_cores() in mp.c. Thus, there is no need to wait for this interrupt and no need for kicking all cores on cpu_release. An atomic 64bit write to the spin-table and a "sev" is sufficient. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: ls1028a: move FSL_LAYERSCAPE to kconfigMichael Walle2020-07-271-0/+1
| | | | | | | | | | CONFIG_FSL_LAYERSCAPE is available in kconfig. There is no need to define it per board; the ls1028a_common.h is really board dependent and only fits to the NXP eval boards. Instead select CONFIG_FSL_LAYERSCAPE when ARCH_LS1028A is selected. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* treewide: convert bd_t to struct bd_info by coccinelleMasahiro Yamada2020-07-172-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
* common: Drop linux/bitops.h from common headerWIP/2020-05-18-reduce-size-of-common.hSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop linux/delay.h from common headerSimon Glass2020-05-183-0/+3
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop asm/ptrace.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop log.h from common headerSimon Glass2020-05-188-0/+8
| | | | | | Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* command: Remove the cmd_tbl_t typedefSimon Glass2020-05-182-1/+2
| | | | | | | | | | | | | We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop init.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop image.h from common headerSimon Glass2020-05-183-0/+3
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop net.h from common headerSimon Glass2020-05-186-0/+7
| | | | | | | | | | | Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
* efi_loader: round the memory area in efi_add_memory_map()Michael Walle2020-05-172-10/+5
| | | | | | | | | | | | | | | | | Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by: Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* driver: net: fm: add DM ETH supportMadalin Bucur2020-04-291-0/+2
| | | | | | | | | | | | | | Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* fsl-layerscape: Move GIC RD tables init to soc.cHou Zhiqiang2020-04-282-0/+48
| | | | | | | | | | | | | Move GIC redistributor tables initialization to CPU setup function. This patch introduces a GIC redistributor tables init function, and moves the function of reserving memory for GIC redistributor tables to soc.c and adds a argument for the memory size to reserve, BTW rename the function so that it is more readable. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* fsl-layerscape: Kconfig: Select RESV_RAM if GIC_V3_ITSHou Zhiqiang2020-04-281-0/+4
| | | | | | | | | The GIC redistributor tables initialization depends on RESV_RAM config, so select RESV_RAM if GIC_V3_ITS is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* fsl-layerscape: Add RESV_RAM check in resv_ram addrHou Zhiqiang2020-04-281-4/+4
| | | | | | | | | The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* phy: add support for backplane kr modeFlorinel Iordache2020-04-201-0/+9
| | | | | | | | | | Add generic support for backplane kr modes currently available: 10gbase-kr, 40gbase-kr4. Remove platform generic fixups (armv8/layerscape and powerpc) for ethernet interfaces specified in device tree as supported backplane modes. Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* dm: arm64: ls1046a: add i2c DM supportBiwen Li2020-03-301-5/+5
| | | | | | | | This supports i2c DM and enables CONFIG_DM_I2C for SoC LS1046A Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* dm: arm64: ls1043a: add i2c DM supportBiwen Li2020-03-301-5/+5
| | | | | | | | This supports i2c DM and enables CONFIG_DM_I2C for SoC LS1043A Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
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