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* common: Move get_tbclk() to time.hSimon Glass2020-01-173-3/+3
| | | | | | | This function related to timer and most of the timer functions are in time.h, so move this function there. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Move clock functions into a new fileSimon Glass2020-01-1712-0/+12
| | | | | | | These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
* Drop CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK usageYangbo Lu2020-01-162-31/+20
| | | | | | | | | | | | | | The eSDHC reference clocks should be provided by speed.c in arch/. And we do not need CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK option to select which clock to use. Because we can make the driver to select the periperhal clock which is better (provides higher frequency) automatically if its value is provided by speed.c. This patch is to drop this option and make driver to select clock automatically. Also fix peripheral clock calculation issue in fsl_lsch2_speed.c/fsl_lsch3_speed.c. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
* armv7m: cache: add mmu_set_region_dcache_behaviour() stub for compatibilityGiulio Benetti2020-01-141-0/+6
| | | | | | | Since some driver requires this function add it as an empty stub when DCACHE is OFF. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
* arm: cpu: armv8: add support for arm psci reset2.Rajesh Ravi2020-01-101-0/+16
| | | | | | | | | | Current U-Boot has only support for psci reset. Adding support for arm psci reset2 allows passing of reset level and other platform sepcific parameters like strap settings to lowlevel psci implementation. Signed-off-by: Rajesh Ravi <rajesh.ravi@broadcom.com> Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com>
* Merge tag 'u-boot-imx-20200107' of ↵WIP/07Jan2020Tom Rini2020-01-072-8/+8
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx New for 2020.04 --------------- - New boards Embedded Artists COM board Xea Board - Switch to DM: Aristainetos boards Toradex colibri (DM_ETH) iCubox GE bx50v3 mx7dsabre (DM_ETH) cx9020 - New features: Bootaux with elf files Default SYS_THUMB_BUILD for i.MX6/7 - Fixes: DHCOM i.MX6 PDK Engicam i.MX8M tools (imx8m_image) Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/633679664
| * ARM: mxs: spl_boot.c: make early_delay more robustRasmus Villemoes2020-01-071-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's true that booting normally doesn't take long enough for the register to roll (which actually happens in a little over an hour, not just a few seconds). However, the counter starts at power-on, and if the board is held in reset to be booted over USB, one actually risks hitting wrap-around during boot, which can both result in too short delays (if the "st += delay" calculation makes st small) and theoretically also unbound delays (if st ends up being UINT_MAX and one just misses sampling digctl_microseconds at that point). It doesn't take more code to DTRT, and once bitten, twice shy. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
| * arm: mxs: be more careful when enabling gpmi_clkRasmus Villemoes2020-01-071-1/+4
| | | | | | | | | | | | | | | | | | The data sheet says that the DIV field cannot change while the CLKGATE bit is set or modified. So do it a little more carefully, by first clearing the bit, waiting for that to appear, then setting the DIV field. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
| * arm: mxs: fix comments in arch_cpu_init to match the codeRasmus Villemoes2020-01-071-2/+2
| | | | | | | | | | | | | | | | The comment says to clear the bypass bit, but in fact it sets it, thus selecting ref_xtal. And the next line of code does not set the divider to 12, but to (the reset value of) 1. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
* | Merge branch 'next'WIP/06Jan2020Tom Rini2020-01-067-24/+185
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bring in the following merges: commit 8fbbec12f7d2c18f8883f3371cfca74a98b5dd87 Merge: 87f69f467a83 63618e71e89b Author: Tom Rini <trini@konsulko.com> Date: Fri Jan 3 09:48:47 2020 -0500 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next - updates and fixes on ls1028a, lx2, ls1046a, MC-DPSPARSER support commit 87f69f467a8335b171c71bf217d2625d515acd7c Merge: c0912f9bbfb2 4466b9970319 Author: Tom Rini <trini@konsulko.com> Date: Tue Dec 24 08:18:19 2019 -0500 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx into next - Enable DM driver on ppc/km boards - Enable DM_USB for some of NXP powerpc platforms: P5040, T4240, T208x, T104x, P4080, P2041, P2020, P1020, P3041 - Some updates in mpc85xx-ddr driver, km boards commit c0912f9bbfb26dd03d189953678691b799d35b6e Merge: 533c9f5714bd a1d6dc3f8407 Author: Tom Rini <trini@konsulko.com> Date: Wed Dec 18 07:20:19 2019 -0500 Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next - Various x86 common codes updated for TPL/SPL - I2C designware driver updated for PCI - ICH SPI driver updated to support Apollo Lake - Add Intel FSP2 base support - Intel Apollo Lake platform specific drivers support - Add a new board Google Chromebook Coral commit 533c9f5714bdba79dc6f2629284d4c1a08a611d1 Merge: 553cb0688782 033e18b47bd0 Author: Tom Rini <trini@konsulko.com> Date: Tue Dec 17 07:53:08 2019 -0500 Merge tag '20191217-for-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c into next i2c: for next - misc: i2c_eeprom: Add partition support and add ability to query size of eeprom device and partitions - i2c common: add support for offset overflow in to address and add sandbox tests for it. commit 553cb06887825314e74a9bdac337467c77d1db88 Merge: f39abbbc531e b4f98b3b16ec Author: Tom Rini <trini@konsulko.com> Date: Thu Dec 12 08:18:59 2019 -0500 Merge tag 'dm-next-13dec19' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm into next buildman improvements including toolchain environment feature sandbox unicode support in serial
| * pci: layerscape: move PCIE related CONFIG to PCI KconfigPankaj Bansal2020-01-022-22/+0
| | | | | | | | | | | | | | | | | | move the PCIE related config from arch Kconfig to PCI Kconfig. As the PCI_LAYERSCAPE driver is being used in platform other than fsl-layerscape platforms like ls102xa. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * fsl-lsch3: soc: Enable AHB read support for Flexspi controllerKuldeep Singh2019-12-262-0/+53
| | | | | | | | | | | | | | | | | | | | | | Enable AHB support for Flexspi controller interface meaning memory can be accessed via md command using absolute addresses Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com> Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * ls1028a: Configure stream IDs for integrated PCI and fix up Linux DTAlex Marginean2019-12-263-0/+111
| | | | | | | | | | | | | | | | | | | | | | Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * armv8: Add workaround for USB erratum A-050106Ran Wang2019-12-262-1/+20
| | | | | | | | | | | | | | | | | | | | USB3.0 Receiver needs to enable fixed equalization for each of PHY instances in an SOC. This is similar to erratum A-009007, but this one is for LX2160A, and the register value is different. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * armv8: layerscape: fix SPL multi DTB loadingMichael Walle2019-12-261-1/+1
| | | | | | | | | | | | | | | | Mark board_fit_config_name_match() as weak so a board can overwrite the empty function. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | sunxi: psci: avoid error address-of-packed-memberHeinrich Schuchardt2019-12-181-5/+11
|/ | | | | | | | | | | | | | | | | | | | | | Compiling with GCC 9.2.1 leads to build errors: arch/arm/cpu/armv7/sunxi/psci.c: In function ‘sunxi_cpu_set_power’: arch/arm/cpu/armv7/sunxi/psci.c:144:21: error: taking address of packed member of ‘struct sunxi_cpucfg_reg’ may result in an unaligned pointer value [-Werror=address-of-packed-member] 144 | sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff, | ^~~~~~~~~~~~~~~~~~~~~~~ arch/arm/cpu/armv7/sunxi/psci.c:144:46: error: taking address of packed member of ‘struct sunxi_cpucfg_reg’ may result in an unaligned pointer value [-Werror=address-of-packed-member] 144 | sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff, | ^~~~~~~~~~~~~~~~~~~~ Use memcpy() and void* pointers to resolve the problem caused by packing the struct sunxi_cpucfg_reg. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
* Fix typo in macros, "FIRMEWARE" -> "FIRMWARE"Thomas Hebb2019-12-052-5/+5
| | | | Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
* armv7m: cache: add invalidate_icache_all() stubGiulio Benetti2019-12-031-0/+5
| | | | | | | | | | This commit: https://gitlab.denx.de/u-boot/u-boot/commit/d409c962169bd293e39386d0ddfa64d5222a3be4 causes build failure with ICACHE enabled. This is due to missing invalidate_icache_all() stub. Let's add empty invalidate_icache_all() in the case where ICACHE is not enabled. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
* cosmetic: Fix spelling and whitespace errorsThomas Hebb2019-12-031-1/+1
| | | | Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
* common: Move some board functions out of common.hSimon Glass2019-12-021-0/+1
| | | | | | | A number of board function belong in init.h with the others. Move them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* common: Move enable/disable_interrupts out of common.hSimon Glass2019-12-029-0/+9
| | | | | | | | Move these two functions into the irq_funcs.h header file. Also move interrupt_handler_t as this is used by the irq_install_handler() function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: powerpc: Tidy up code style for interrupt functionsSimon Glass2019-12-025-5/+5
| | | | | | | Remove the unwanted space before the bracket. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* common: Move ARM cache operations out of common.hSimon Glass2019-12-025-0/+5
| | | | | | | | | These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* common: Move some cache and MMU functions out of common.hSimon Glass2019-12-0221-0/+21
| | | | | | | | | | | | These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* common: Move some SMP functions out of common.hSimon Glass2019-12-022-0/+2
| | | | | | | These functions belong in cpu_func.h so move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* common: Move some CPU functions out of common.hSimon Glass2019-12-024-0/+4
| | | | | | | | | These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* common: Move mii_init() function out of common.hSimon Glass2019-12-021-0/+1
| | | | | | | This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* common: Move get_ticks() function out of common.hSimon Glass2019-12-0215-0/+15
| | | | | | | This function belongs in time.h so move it over and add a comment. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: pxa: Drop pxa_wait_ticks()Simon Glass2019-12-021-8/+4
| | | | | | | | | | This function has a similar name to the common wait_ticks(). It is only used in one place and seems small enough to drop. Inline it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* common: Move some time functions out of common.hSimon Glass2019-12-022-0/+2
| | | | | | | These functions belong in time.h so move them over and add comments. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* common: Move serial functions out of common.hSimon Glass2019-12-021-0/+1
| | | | | | | These functions belong in serial.h so move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* Move strtomhz() to vsprintf.hSimon Glass2019-12-024-0/+4
| | | | | | | | | | | At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* common: Move older CPU functions to their own headerSimon Glass2019-12-021-0/+1
| | | | | | | | These should be moved to driver model, but in the meantime, move them out of the common header to help reduce its size. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: drop eSDHC clock getting in mxc_get_clock() for layerscapeYangbo Lu2019-11-273-32/+0
| | | | | | | | | | Although layerscape platforms reuse mxc_get_clock() of i.MX platforms, eSDHC clock getting do not have to use it. It uses global data gd->arch.sdhc_clk directly in fsl_esdhc driver. Even there are more than one eSDHC controllers on SoC, they use same reference clock. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* env: Finish migration of common ENV optionsTom Rini2019-11-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | - In ARMv8 NXP Layerscape platforms we also need to make use of CONFIG_SYS_RELOC_GD_ENV_ADDR now, do so. - On ENV_IS_IN_REMOTE, CONFIG_ENV_OFFSET is never used, drop the define to 0. - Add Kconfig entry for ENV_ADDR. - Make ENV_ADDR / ENV_OFFSET depend on the env locations that use it. - Add ENV_xxx_REDUND options that depend on their primary option and SYS_REDUNDAND_ENVIRONMENT - On a number of PowerPC platforms, use SPL_ENV_ADDR not CONFIG_ENV_ADDR for the pre-main-U-Boot environment location. - On ENV_IS_IN_SPI_FLASH, check not for CONFIG_ENV_ADDR being set but rather it being non-zero, as it will now be zero by default. - Rework the env_offset absolute in env/embedded.o to not use CONFIG_ENV_OFFSET as it was the only use of ENV_OFFSET within ENV_IS_IN_FLASH. - Migrate all platforms. Cc: Wolfgang Denk <wd@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: uboot-stm32@st-md-mailman.stormreply.com Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* arm: arm11: allow unaligned memory accessHeinrich Schuchardt2019-11-192-0/+29
| | | | | | | | | | | | | | | The UEFI spec mandates that unaligned memory access should be enabled if supported by the CPU architecture. This patch implements the function unaligned_access() to set the enable unaligned data support flag and to clear the aligned flag in the system control register (SCTLR). It is called when UEFI related commands like bootefi are invoked. Reported-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Tested-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Tested-by: Guillaume Gardet <Guillaume.Gardet@arm.com> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* freescale/layerscape: Rename the config CONFIG_SECURE_BOOT nameUdit Agarwal2019-11-083-5/+5
| | | | | | | | Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC to avoid conflict with UEFI secure boot. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* fsl-layerscape: fix warning if no hwconfig is definedPankaj Bansal2019-11-081-1/+3
| | | | | | | | | | | | | | | While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc>
* armv8: fsl-layerscape: introduce fsl_board_late_init()Michael Walle2019-11-081-1/+6
| | | | | | | | | | The fsl-layerscape already occupies board_late_init(), therefore it is not possible for a board to have its own board_late_init(). Introduce fsl_board_late_init() which can be implemented in the board specific code. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: fsl-lsch3: convert CONFIG_TARGET_x to CONFIG_ARCH_xMichael Walle2019-11-081-5/+5
| | | | | | | | | | | The clocks are not dependent on the target but only on the SoC. Therefore, convert the CONFIG_TARGET_x macros to the corresponding CONFIG_ARCH_x. This will allow other targets to automatically use the common code. Otherwise every new target would have to add itself to the "#if defined(CONFIG_TARGET_x) || .." macros. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: ls1028a: add erratum A-050382 workaroundLaurentiu Tudor2019-11-081-0/+3
| | | | | | | | | | Erratum A-050382 states that the eDMA ICID programmed in the eDMA_AMQR register in DCFG is not correctly forwarded to the SMMU. The workaround consists in programming the eDMA ICID in the eDMA_AMQR register in DCFG to 40. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: lx2160a: add icid setup for platform devicesLaurentiu Tudor2019-11-083-1/+50
| | | | | | | | | Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, sec. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: ls2088a: add icid setup for platform devicesLaurentiu Tudor2019-11-083-1/+38
| | | | | | | | | Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, sec. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: fsl-layerscape: guard caam specific definesLaurentiu Tudor2019-11-082-0/+4
| | | | | | | | These macros should only be used when CONFIG_FSL_CAAM is present. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* fsl-layerscape: do not use layerscape EFI reset if PSCI usedMathew McBride2019-11-081-1/+1
| | | | | | | | If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* arm: mxs: Increase VDDD voltage to match specificationMarek Vasut2019-11-031-2/+2
| | | | | | | | | | | | | | According to IMX28CEC rev. 4, 10/2018, Table 15. Recommended Operating Conditions, page 16, the VDDD should be set to 1.55V when the CPU is operating at 454MHz. This is the case in U-Boot, hence increase the VDDD voltage. This fixes instability when performing TFTP transfers. Increase the brownout threshold to 1.4V. The documentation recommends 1.45V setting for the brownout, however, this triggers failure during power block init, so keep the brownout slightly lower. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
* armv7: ls102xa: Don't power down OCRAM1 during deep sleepBiwen Li2019-10-211-1/+6
| | | | | | | | To allow OCRAM to be used as wakeup source in deep sleep, do not power it down. Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv7: ls102xa: add errata ID A-008646 for workaroundBiwen Li2019-10-211-3/+4
| | | | | | | | The patch adds an errata ID A-008646 for workaround to provide more information by errata ID. Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: ls1028a: disable multimedia for ls1027a, ls1017aYuantian Tang2019-10-211-0/+23
| | | | | | | | | | | | ls1028a has 4 personalities: ls1028a, ls1027a, ls1017a and ls1018a. Both ls1027a and ls1017a personalities are lower functionality version which doesn't support the multimedia subsystems, like LCD, GPU. To disable multimedia feature on non-multimedia version, set the status property to disabled in dts nodes. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv7: ls102xa: Correct endianness of SCFG_SPARECR8 readBiwen Li2019-10-211-1/+1
| | | | | | | | The patch corrects endianness of register SCFG_SPARECR8 read in_le32 -> in_be32 Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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