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* ARM: dts: uniphier: sync DT with Linux next-20170622Masahiro Yamada2017-06-2524-353/+29
| | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge branch 'master' of git://git.denx.de/u-boot-samsungTom Rini2017-06-218-143/+303
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| * ARM: dts: exynos5422-odroidxu3: add the LDO's nodesJaehoon Chung2017-06-051-0/+209
| | | | | | | | | | | | | | Add the LDO's nodes that taken from Linux Kernel. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * ARM: dts: exynos4: change the nodes relevant to mmc/sdJaehoon Chung2017-06-057-143/+94
| | | | | | | | | | | | | | | | Change the nodes relevant to mmc/sd for using DM. compatible are also changed to each SoCs. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | Merge tag 'xilinx-for-v2017.07' of git://www.denx.de/git/u-boot-microblazeTom Rini2017-06-212-0/+18
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Xilinx changes for v2017.07 ZynqMP: - config cleanup - SD LS mode support - psu_init* cleanup - unmap OCM - Support for SMC Zynq: - add ddrc to Kconfig - add topic-miamilite board support
| * | arm: zynq: Add support for the topic-miamilite system-on-moduleMike Looijmans2017-06-202-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | The topic-miamilite SoM contains a Zynq xc7z010 SoC, 1GB DDR3L RAM, 64MB dual-parallel QSPI NOR flash and clock sources. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | ARM: dts: omap3: Fix dts->dtb typoMarek Vasut2017-06-201-1/+1
| | | | | | | | | | | | | | | | | | | | | Trivial, fix typo. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2017-06-195-1/+346
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| * | sun50i: h5: Add initial NanoPi NEO2 supportJagan Teki2017-06-142-0/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NanoPi NEO2 is designed and developed by FriendlyElec using the Allwinner 64-bit H5 SOC. NanoPi Neo2 key features - Allwinner H5, Quad-core 64-bit Cortex-A53 - 512MB DDR3 RAM - microSD slot - 10/100/1000M Ethernet - Serial Debug Port - 5V 2A DC MicroUSB power-supply Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sun50i: a64: Add initial Orangepi Win/WinPlus supportJagan Teki2017-06-142-0/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Orangepi Win/WinPlus is an open-source single-board computer using the Allwinner A64 SOC. A64 Orangepi Win/WinPlus has - A64 Quad-core Cortex-A53 64bit - 1GB(Win)/2GB(Win Plus) DDR3 SDRAM - Debug TTL UART - Four USB 2.0 - HDMI - LCD - Audio and MIC - Wifi + BT - IR receiver - 5V DC power supply Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sun50i: h5: Add initial Orangepi Zero Plus 2 supportJagan Teki2017-06-142-1/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Orangepi Zero Plus 2 is an open-source single-board computer using the Allwinner h5 SOC. H5 Orangepi Zero Plus 2 has - Quad-core Cortex-A53 - 512MB DDR3 - micrSD slot and 8GB eMMC - Debug TTL UART - HDMI - Wifi + BT - OTG+power supply Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sun8i: h3: Add initial NanoPi M1 Plus supportJagan Teki2017-06-082-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NanoPi M1 Plus is designed and developed by FriendlyElec for professionals, enterprise users, makers and hobbyists using the Allwinner H3 SOC. NanoPi M1 Plus key features - Allwinner H3, Quad-core Cortex-A7@1.2GHz - 1GB DDR3 RAM - 8GB eMMC - microSD slot - 10/100/1000M Ethernet - Serial Debug Port - 5V 2A DC power-supply Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2017-06-142-78/+0
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| * | | ARM: tegra: remove Whistler supportStephen Warren2017-06-122-78/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Whistler is an ancient Tegra 2 reference board. I may have been the only person who ever used it with upstream software, and I've just recycled the board hardware. Hence, it makes sense to remove support from software. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | | ARM: dts: keystone-k2hk-evm: Add U-boot specific dtsi fileCooper Jr., Franklin2017-06-121-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With Davinci I2C switching to device model, K2HK requires U-boot specific device tree entries. This is only required for I2C 1 which is needed extremely early during the boot process. Fixes: 1743d040b1df ("ARM: keystone: Enable DM_I2C by default") Reported-by: Yan Liu <yan-liu@ti.com> Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
* | | | serial: stm32x7: align compatible with kernel onePatrice Chotard2017-06-121-1/+1
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | stm32x7.c driver is dedicated for STM32F7. In kernel, "st,stm32-usart" and "st,stm32-uart" compatible strings are dedicated for STM32F4. To keep U-boot and kernel aligned, replace the serial compatible string from "st,stm32-usart", "st,stm32-uart" to "st,stm32f7-usart", "st,stm32f7-uart" specific for STM32F7. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Christophe KERELLO <christophe.kerello@st.com> Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
* | | rockchip: Fix regualtor typo in veyronSimon Glass2017-06-091-1/+1
| | | | | | | | | | | | | | | | | | This typo doesn't actually cause any problems, but is wrong. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | tegra: dts: Add cros-ec SPI settingsSimon Glass2017-06-091-0/+9
| | | | | | | | | | | | | | | | | | | | | At present the interrupt does not work and the SPI bus runs much less quickly than it should. Add settings to fix this. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | rockchip: dts: rk3399-puma: add DTS for the DDR3-1866 timingPhilipp Tomsich2017-06-072-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the DDR3-1866 timing via its own DTS and wires it up. This (currently) is not the default timing for the RK3399-Q7 and should be selected explicitly via the config (CONFIG_DEFAULT_DEVICE_TREE). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | rockchip: dts: rk3399-puma: add DTS for the DDR3-1333 timingPhilipp Tomsich2017-06-072-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the DDR3-1333 timing via its own DTS and wires it up. This is not the default timing for the RK3399-Q7 and should be selected explicitly via the config (CONFIG_DEFAULT_DEVICE_TREE). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | rockchip: dts: rk3399-puma: refactor and rename (default) DDR3-1600 DTSPhilipp Tomsich2017-06-073-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To better support different RAM timings (DDR3-1333 and DDR3-1866 are assembly options for the RK3399-Q7), this refactors the DTS support and renames the default DTS variant from rk3399-puma to rk3399-puma-ddr1600: - changes the rk3399-puma DTS into a board-specific DTSI by removing the inclusion of the DRAM timings - adds a new rk3399-puma-ddr1600.dts, which includes the (new) common board DTSI and the DDR3-1600 timing DTSI - wires this up from arch/arm/dts/Makefile and configs/puma-rk3399_defconfig Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | rockchip: dts: rk3399-puma: sync DTS with Linux treePhilipp Tomsich2017-06-071-45/+495
| | | | | | | | | | | | | | | | | | | | | | | | The Linux DTS for the RK3399-Q7 has moved with the times... resync against it to ensure a consistent configuration. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | rockchip: dts: rk3399: enable HDMI output in the DTSPhilipp Tomsich2017-06-071-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | This commit enables HDMI output in the DTS by adding the necessary nodes to vopl/vopb and by adding the HDMI node. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | rockchip: Add basic support for evb-rv1108 boardAndy Yan2017-06-073-1/+535
| | | | | | | | | | | | | | | | | | | | | | | | Add basic support for rv1108 evb, whith this patch we can boot into u-boot console. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | rockchip: dts: rk3399-puma: set spl-payload-offsetKlaus Goger2017-06-071-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | defines the spl-payload to 256k (0x40000) Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | rockchip: dts: rk3399-puma: release reset of on-module USB3 hub via vbus-gpioPhilipp Tomsich2017-06-071-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the RK3399-Q7, the on-module USB3 hub is held in reset at boot-up to save power and needs to be woken up using GPIO4A3. Note that this is not a negated reset-signal (due to a level shifter being needed for this signal anyway), but a negated enable-signal: to enable, we need to output LOW (i.e. 0)... so we mark this as an ACTIVE_LOW signal. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | rockchip: dts: rk3399-puma: make the debug serial dm-pre-relocPhilipp Tomsich2017-06-071-0/+1
| | | | | | | | | | | | | | | Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | rockchip: dts: rk3399-puma: Add DDR3-1866 timingsPhilipp Tomsich2017-06-071-0/+1537
| | | | | | | | | | | | | | | | | | | | | | | | | | | With the validation done for DDR3-1866 (i.e. 933 MHz bus clock), we can now add the timings (rk3399-sdram-ddr3-1866.dtsi) for boards built with the DDR3-1866 option. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | rockchip: dts: rk3328: support and enable xhciMeng Dongyang2017-06-072-0/+16
| | | | | | | | | | | | | | | Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | rockchip: dts: rk3328: add ehci and ohci node and enable host0 portMeng Dongyang2017-06-072-0/+22
| | | | | | | | | | | | | | | Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | rockchip: rk3368: Add PX5 Evaluation boardAndy Yan2017-06-072-0/+320
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PX5 EVB is designed by Rockchip for automotive field with integrated CVBS (TP2825) / MIPI DSI / CSI / LVDS HDMI video input/output interface, audio codec ES8396, WIFI / BT (on RTL8723BS), Gsensor BMA250E and light&proximity sensor STK3410. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | rockchip: rk3368: Add initial support for RK3368 based GeekBoxAndreas Färber2017-06-072-0/+320
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GeekBox is a TV box from GeekBuying, based on an MXM3 module. The module can be used with base boards such as the GeekBox Landingship. This adds basic support to chain-load U-Boot from Rockchip's miniloader. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | rockchip: rk3368: add Sheep boardAndy Yan2017-06-072-0/+284
| | | | | | | | | | | | | | | | | | | | | | | | | | | Sheep board is designed by Rockchip as a EVB for rk3368. Currently it is able to boot a linux kernel and system to console with the miniloader run as fist level loader. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
* | | rockchip: rk3368: Add core start-up code for RK3368Andreas Färber2017-06-071-0/+1090
|/ / | | | | | | | | | | | | | | | | | | The RK3368 is an octa-core Cortex-A53 SoC from Rockchip. This adds basic support to chain-load U-Boot from Rockchip's miniloader. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | ti816x: Import dts files from Linux Kernel v4.11Tom Rini2017-06-054-0/+944
|/ | | | | | | This brings in the required dts/dtsi files for the TI8168-EVM from the Linux Kernel v4.11 release. Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-sunxiTom Rini2017-06-0312-603/+731
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| * sun50i: h5: Add initial Orangepi Prime supportJagan Teki2017-06-022-1/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Orangepi Prime is an open-source single-board computer using the Allwinner h5 SOC. H5 Orangepi Prime has - Quad-core Cortex-A53 - 2GB DDR3 - Debug TTL UART - 1000M/100M Ethernet RJ45 - Three USB 2.0 - HDMI - Audio and MIC - Wifi + BT - IR receiver - HDMI - Wifi + BT Boot from MMC: ------------- U-Boot SPL 2017.05-00662-ga3f4c05-dirty (May 25 2017 - 13:30:14) DRAM: 2048 MiB Trying to boot from MMC1 NOTICE: BL3-1: Running on H5 (1718) in SRAM A2 (@0x44000) NOTICE: Configuring SPC Controller NOTICE: BL3-1: v1.0(debug):aa75c8d NOTICE: BL3-1: Built : 18:28:27, May 24 2017 INFO: BL3-1: Initializing runtime services INFO: BL3-1: Preparing for EL3 exit to normal world INFO: BL3-1: Next image address: 0x4a000000, SPSR: 0x3c9 U-Boot 2017.05-00662-ga3f4c05-dirty (May 25 2017 - 13:30:14 +0000) Allwinner Technology CPU: Allwinner H5 (SUN50I) Model: OrangePi Prime DRAM: 2 GiB MMC: SUNXI SD/MMC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: phy interface7 eth0: ethernet@1c30000 starting USB... USB0: USB EHCI 1.00 USB1: USB OHCI 1.0 scanning bus 0 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found Hit any key to stop autoboot: 0 Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * arm64: dts: sun50i: h5: orangepi-pc2: Use GPIO flag binding macroJagan Teki2017-06-011-1/+3
| | | | | | | | | | | | | | Instead of defining numerical value on GPIO flag better to use existing binding macro. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * arm64: dts: sun50i: Add sun50i-h5.dtsiJagan Teki2017-06-012-33/+78
| | | | | | | | | | | | | | | | | | | | | | The Allwinner H5 SoC is pin-compatible to the H3 SoC, but uses Cortex-A53 cores instead. So move the shared cpu based and peripherals nodes into sun50i-h5.dtsi so, that it can shared among the sun50i-h5 board dts files. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * sun50i: a64: Add initial Banana Pi M64 supportJagan Teki2017-06-012-0/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BPI-M64 is a 64-bit quad-core mini single board computer using the Allwinner A64 SOC. BPI-M64 features - 1.2 Ghz Quad-Core ARM Cortex A53 - 2GB DDR3 SDRAM with 733MHz - MicroSD/eMMC(8GB) - 10/100/1000Mbps ethernet (Realtek RTL8211E/D) - Wifi + BT - IR receiver - Audio In/Out - Video In/Out - 5V 2A DC power-supply For dts file, Sync with Linux commit 4879b7ae("Merge tag 'dmaengine-4.12-rc1'"). Boot from MMC: ------------- U-Boot SPL 2017.05-00667-g85dd258-dirty (May 29 2017 - 13:07:31) DRAM: 2048 MiB Trying to boot from MMC1 NOTICE: BL3-1: Running on A64/H64 (1689) in SRAM A2 (@0x44000) NOTICE: Configuring SPC Controller NOTICE: BL3-1: v1.0(debug):aa75c8d NOTICE: BL3-1: Built : 18:28:27, May 24 2017 NOTICE: Configuring AXP PMIC NOTICE: PMIC: setup successful INFO: BL3-1: Initializing runtime services INFO: BL3-1: Preparing for EL3 exit to normal world INFO: BL3-1: Next image address: 0x4a000000, SPSR: 0x3c9 U-Boot 2017.05-00667-g85dd258-dirty (May 29 2017 - 13:07:31 +0000) Allwinner Technology CPU: Allwinner A64 (SUN50I) Model: BananaPi-M64 DRAM: 2 GiB MMC: SUNXI SD/MMC: 0, SUNXI SD/MMC: 1 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: No ethernet found. starting USB... No controllers found Hit any key to stop autoboot: 0 Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: A64/Pine64: update device tree from LinuxAndre Przywara2017-06-015-569/+298
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Linux device tree for the Allwinner A64 SoC has changed a lot since the U-Boot version was merged. Let's replace the current DT with a exact copy of the Linux one as of: commit c6778ff813d2ca3e3c8733c87dc8b6831a64578b Merge: 0ff4c01 3c0e3abd Author: Linus Torvalds <torvalds@linux-foundation.org> Date: Tue May 9 10:07:33 2017 -0700 This is the DT used in Linux 4.12-rc1. Since U-Boot has an Ethernet driver (while Linux does not yet), we provide the required DT nodes for it in an ...-u-boot.dtsi file, to both mark them as U-Boot specific and to allow easier upgrading once Linux gets the driver and its own binding later. Compared to the existing Ethernet DT nodes we just slightly tweak the clock and reset nodes in there to match the new bindings used by Linux for those. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: Update NanoPi Neo to use dtsiMylene JOSSERAND2017-05-301-78/+1
| | | | | | | | | | | | | | Update the NanoPi Neo device tree file to use the NanoPi dtsi. Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: Add support for NanoPi M1Mylene JOSSERAND2017-05-303-0/+202
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NanoPi M1 is a board based on Allwinner H3 CPU. This commit adds the support for this platform with: - an include device tree which enables UART, LEDs, GPIO key switch, 1 USB host ports and the SD-card as a dtsi file. - a device tree specific to this board that enables the 2 additional USB ports - a defconfig file for minimal support - a section in MAINTAINERS (add myself) Synchronized with the kernel device tree, from commits: sun8i-nanopi.dtsi: 85d2913614d9ab899d23b7ab7d22d23cf45bd1de sun8i-h3-nanopi-m1.dts: 10efbf5f16336b7540ad6a16aa1cb0b26bab033b Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | arm64: mvebu: armada-7040-db: Enable 10GB port 0 / SFI (KR)Stefan Roese2017-05-311-2/+6
| | | | | | | | | | | | | | | | | | | | | | This patch enables the mvpp2 port 0 usage on the Armada 7k DB by setting the correct PHY type (KR / SFI) for the COMPHY driver and enabling the ethernet0 device node in the dts. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com>
* | arm64: mvebu: armada37xx: add pinctrl definitionGregory CLEMENT2017-05-312-0/+39
| | | | | | | | | | | | | | | | | | | | | | Start to populate the device tree of the Armada 37xx with the pincontrol configuration used on the board providing a dts. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Konstantin Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com>
* | arm64: mvebu: Add pinctrl nodes for Armada 3700Gregory CLEMENT2017-05-311-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the nodes for the two pin controller present in the Armada 37xx SoCs. Initially the node was named gpio1 using the same name that for the register range in the datasheet. However renaming it pinctr_nb (nb for North Bridge) makes more sens. Minor changes for U-Boot because of the slightly different dts version done by Stefan Roese. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Konstantin Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com>
* | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-05-263-1/+121
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| * armv8: ls2080ardb: Add LS2081ARDB board supportPriyanka Jain2017-05-232-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | LS2081ARDB board is similar to LS2080ARDB board with few differences It hosts LS2081A SoC Default boot source is QSPI-boot It does not have IFC interface RTC and QSPI flash device are different It provides QIXIS access via I2C Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls2080ardb: Add QSPI-boot supportPriyanka Jain2017-05-232-1/+61
| | | | | | | | | | | | | | | | | | | | QSPI-boot is supported on LS2088ARDB RevF board with LS2088A SoC. LS2088ARDB RevF Board has limitation that QIXIS can not be accessed. CONFIG_FSL_QIXIS is not enabled. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2017-05-187-252/+1514
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