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* misc: scu_api: Add SCFW API to get the index of boot container setYe Li2020-07-162-0/+2
| | | | | | | | | | Add SCFW API sc_misc_get_boot_container to get current boot container set index. The index value returns 1 for primary container set, 2 for secondary container set. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* imx8m: power down fused coresPeng Fan2020-07-141-0/+158
| | | | | | | For non-Quad SoCs, the fused cpu cores could be powered down in SPL to save power. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8mp: Add fused parts supportYe Li2020-07-142-1/+13
| | | | | | | | | | | | | | | | | | | iMX8MP has 6 fused parts in each qualification tier, with core, VPU, ISP, NPU or DSP fused respectively. The configuration tables for enabled modules: MIMX8ML8DVNLZAA Quad Core, VPU, NPU, ISP, DSP MIMX8ML7DVNLZAA Quad Core, NPU, ISP MIMX8ML6DVNLZAA Quad Core, VPU, ISP MIMX8ML5DVNLZAA Quad Core, VPU MIMX8ML4DVNLZAA Quad Lite MIMX8ML3DVNLZAA Dual Core, VPU, NPU, ISP, DSP Add the support in U-Boot Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* drivers: ddr: imx Workaround for i.MX8M DDRPHY rank to rank issueOliver Chen2020-07-141-0/+3
| | | | | | | | | | Add logic to automatically update umctl2's setting based on phy training CDD value for rank to rank space issue Acked-by: Ye Li <ye.li@nxp.com> Signed-off-by: Oliver Chen <Oliver.Chen@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* drivers: ddr: imx8mp: Add inline ECC feature supportSherry Sun2020-07-141-0/+7
| | | | | | | | | | | | | | | | | | the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* arm: provide a function for boards init code to modify MMU virtual-physical mapMarek Szyprowski2020-07-102-0/+21
| | | | | | | | Provide function for setting arbitrary virtual-physical MMU mapping and cache settings for the given region. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: update comments to the common styleMarek Szyprowski2020-07-101-9/+14
| | | | | | | Update the comments in include/asm/system.h to the common style. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: use correct argument size of special registersHeinrich Schuchardt2020-07-071-4/+6
| | | | | | | | | | | | | | | | | Compiling with clang on ARMv8 shows errors like: ./arch/arm/include/asm/system.h:162:32: note: use constraint modifier "w" asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); ^~ %w0 These errors are due to using an incorrect size for the variables used for writing to and reading from special registers which have 64 bits on ARMv8. Mask off reserved bits when reading the exception level. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* arm: remove outdated comment concerning -ffixed-x18Heinrich Schuchardt2020-07-071-4/+0
| | | | | | | Clang 9 supports -ffixed-x18. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* net: designware: s700: Add glue code for S700 macAmit Singh Tomar2020-07-071-0/+6
| | | | | | | | | | | | This patchs adds glue logic to enable designware mac present on Action Semi based S700 SoC, Configures SoC specific bits. Undocumented bit that programs the PHY interface select register comes from vendor source. It has been tested on Cubieboard7-lite based on S700 SoC. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
* clk: actions: Add Ethernet clocksAmit Singh Tomar2020-07-072-0/+6
| | | | | | | This commit adds clocks needed for ethernet operations for Actions OWL family of SoCs (S700 and S900). Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
* ARM: imx: ddr: Fill in missing DDRC ZQCTLx on i.MX7Marek Vasut2020-06-221-1/+3
| | | | | | | | | | | | | | | | The iMX7 defines further DDRC ZQCTLx registers, however those were thus far missing from the list of registers and not programmed. On systems with LPDDR2 or DDR3, those registers must be programmed with correct values, otherwise the DRAM may not work. However, existing systems which worked without programming these registers before are now setting those registers to 0, which is the default value, so no functional change there. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* ARM: imx: ddr: Add missing PHY resetMarek Vasut2020-06-081-0/+1
| | | | | | | | | | | | | | | | | The iMX7D RM 9.2.4.9.3 Power removal flow Table 9-11. Re-enabling power explicitly says both the DDR controller and the PHY must be reset in the correct sequence. Currently the code only resets the controller. This leads to a misbehavior where the system brings the DRAM up after reboot, but the DRAM is unstable. Add the missing reset. The easiest way to trigger this is by triggering WDT without having the WDT assert WDOG_B signal, i.e. mw.w 0x30280000 0x25 . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* Merge tag 'efi-2020-07-rc4' of ↵WIP/03Jun2020Tom Rini2020-06-031-0/+9
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2020-07-rc4 This patch series addresses the following issues: * allow compiling with clang * add missing function descriptions to the HTML documentation * simplify the validation of UEFI images * validate load options in the UEFI boot manager In a preparatory patch a structure definition is moved.
| * efi_loader: allow compiling with clangHeinrich Schuchardt2020-06-031-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On ARM systems gd is stored in register r9 or x18. When compiling with clang gd is defined as a macro calling function gd_ptr(). So we can not make assignments to gd. In the UEFI sub-system we need to save gd when leaving to UEFI binaries and have to restore gd when reentering U-Boot. Define a new function set_gd() for setting gd and use it in the UEFI sub-system. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Tested-by: Tom Rini <trini@konsulko.com>
* | ARM: add psci_arch_init() declaration for CONFIG_ARMV7_PSCIWIP/2020-06-02-misc-bugfixesMasahiro Yamada2020-06-021-0/+1
|/ | | | | | | | | | arch/arm/include/asm/system.h declares psci_arch_init(), but it is surrounded by #ifdef CONFIG_ARMV8_PSCI. psci_arch_init() is called for CONFIG_ARMV7_PSCI too. Add the missing function declaration. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* usb: ehci-omap: Add Support for DM_USB and OF_CONTROLAdam Ford2020-05-221-0/+2
| | | | | | | | | | | | | | | | | | | The omap3.dtsi file shows the usbhshost node with two sub-nodes for ohci and ehci. This patch file creates the usbhshost, and pulls the portX-mode information. It then locates the EHCI sub-node, and initializes the EHCI controller with the info pulled from the usbhshost node. There is still more to do since there isn't an actual link between the 'phys' reference and the corresponding phy driver, and there is no nop-xceiv driver yet. In the meantime, the older style reference to CONFIG_OMAP_EHCI_PHYx_RESET_GPIO is still needed to pull the phy out of reset until the phy driver is completed and the phandle reference is made. Signed-off-by: Adam Ford <aford173@gmail.com>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqWIP/20May2020Tom Rini2020-05-202-2/+0
|\ | | | | | | | | | | | | - Add DM_ETH support for lx2160aqds, ls2080aqds, ls1088aqds - QSI related fixes on ls1012a, ls2080a, ls1046a, ls1088a, ls1043a based platforms - Bug-fixes/updtaes related to ls1046afrwy, fsl-mc, msi-map property
| * treewide: Remove unused FSL QSPI config options for Layerscape platformsKuldeep Singh2020-05-192-2/+0
| | | | | | | | | | | | | | | | | | | | | | Some of these options are not used by the driver anymore and some of them are obsolete as the information is gathered from the dt. Also consolidating defines in common headers. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | common: Drop linux/bitops.h from common headerWIP/2020-05-18-reduce-size-of-common.hSimon Glass2020-05-1851-4/+187
| | | | | | | | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Use __ASSEMBLY__ as the assembly macrosSimon Glass2020-05-187-7/+7
| | | | | | | | | | | | | | Some places use __ASSEMBLER__ instead which does not work since the Makefile does not define it. Fix them. Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop log.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | | | | | | | Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* | command: Remove the cmd_tbl_t typedefSimon Glass2020-05-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop net.h from common headerSimon Glass2020-05-182-0/+4
| | | | | | | | | | | | | | | | | | | | | | Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Don't include common.h in header filesSimon Glass2020-05-1852-88/+23
|/ | | | | | | | | | | It is bad practice to include common.h in other header files since it can bring in any number of superfluous definitions. It implies that some C files don't include it and thus may be missing CONFIG options that are set up by that file. The C files should include these themselves. Update some header files in arch/arm to drop this. Signed-off-by: Simon Glass <sjg@chromium.org>
* imx: imx8qm/qxp: check whether m4 partition bootedPeng Fan2020-05-101-0/+1
| | | | | | | Add code to check m4 partition booted or not, we will use this to runtime set device tree file that passed to Linux Kernel. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx: imx8qm/imx8qxp: Power down the resources before SPL jump to u-bootPeng Fan2020-05-101-0/+1
| | | | | | | | | | | | Make sure that all devices that are powered up by SPL are powered down before entering into the u-boot. Otherwise the subsystem/device will never be powered down by SCFW, due to SPL and u-boot are in different partitions. Benefiting from power domain driver, this patch implements the function "imx8_power_off_pd_devices" to power off all active devices. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* cmd: nandbcb: Reconstruct the nandbcb tool for all platformsHan Xu2020-05-101-1/+3
| | | | | | | | | | | | | | | | | | | | | | The original nandbcb tool was designed for imx6 only, when trying to leverage it to replace the kobs-ng tool, we found the design is not friendly for supporting all platforms. To support all iMX6/7/8 platforms and for easy further maintain, I reconstruct the structure of the tool. The main changes including: 1. Use platform_data to determine the logic branches rather than simply use SOC name. 2. More data structures as parameter for functions. 3. Global variables to define the FCB/DBBT/FW locations. 4. Implement the kobs-ng default 4 FCB/4 DBBT/2 FW layout. 5. Support Hamming coding/ 40bit BCH/ 62bit BCH coding FCB. 6. Dump and compare all written FCB/DBBT to verify data integrity. The tool has been verified on iMX6Q/DL, 6SX, 7D, 6ULL, iMX8QX, iMX8MM. Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8: power: Add PD device lookup interface to power domain uclassPeng Fan2020-05-101-0/+7
| | | | | | | | | | | | | | | | | Add power_domain_lookup_name interface to power domain uclass to find a power domain device by its DTB node name, not using its associated client device. Through this interface, we can operate the power domain devices directly. This is needed for non-DM drivers. Modified from Ye's NXP downstream patch only for legacy imx8 power domain driver, since we have not migrated to use new power domain driver. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* mtd: nand: support GPMI NAND driver for i.MX8Peng Fan2020-05-103-14/+15
| | | | | | | | | | enable the GPMI NAND driver for i.MX8, i.MX8 use similar controller as i.MX8M - register definition for i.mx8 - DMA structure must be 32bit address Signed-off-by: Peng Fan <peng.fan@nxp.com>
* mtd: mxs_nand: fix the gf_13/14 definition issueHan Xu2020-05-101-4/+4
| | | | | | | gf_13/14 mask was not set correctly in register definition. Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* mxs_nand: Add support for i.MX8MYe Li2020-05-103-6/+6
| | | | | | | Update the gpmi/apbh_dma/bch drivers and relevant registers for i.MX8M. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* nand: mxs: correct bitflip for erased NAND pagePeng Fan2020-05-101-1/+6
| | | | | | | | | | | | | | | | | | | This patch is a porting of http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/ commit/?h=imx_4.1.15_1.0.0_ga&id=e4dacc44d22e9474ec456cb330df525cd805ea38 " i.MX6QP and i.MX7D BCH module integrated a new feature to detect the bitflip number for erased NAND page. So for these two platform, set the erase threshold to gf/2 and if bitflip detected, GPMI driver will correct the data to all 0xFF. Also updated the imx6qp dts file to ditinguish the GPMI module for i.MX6Q with the one for i.MX6QP. " In this patch, i.MX6UL is added and threshold changed to use ecc_strength. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx: regs: add more fuse bank structurePeng Fan2020-05-101-7/+34
| | | | | | Add more fuse bank structure for use. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* fec: Move imx_get_mac_from_fuse declare to imx fileYe Li2020-05-101-0/+2
| | | | | | | | | | imx_get_mac_from_fuse is used to load MAC address from fuse. On imx8mp, we have two different ENET controllers and both need to call this function. So decouple its declare from fec driver. Reviewed-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx: add module fuse supportPeng Fan2020-05-102-0/+128
| | | | | | | | | | | There are different parts from one SoC. Take i.MX6ULL for example, some part might not have ENET, some might have; some might not have USB, some might have. The information could be got from OCOTP, to make one image support the different parts, we need runtime disable linux kernel dts node and uboot driver probe if the corresponding module not exists in the part. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2020-05-102-1/+8
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| * Merge tag 'u-boot-imx-20200502' of ↵Tom Rini2020-05-049-28/+120
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx i.MX for 2020.07 ---------------- - imxrt: fix LCD clock, fix doc - new board: Coral Dev - imx8: enable Cache in SPL. SNVS, update SCFW API - imx8MM: fix reset, 8MQ quand and QuadLite, CPU speed grading - MX6ULL : is_imx6ull to include i.MX6ULZ - Net: add config to enable TXC delay Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/682033914
| * | arm: caches: add DCACHE_DEFAULT_OPTIONPatrick Delaunay2020-05-011-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the new flags DCACHE_DEFAULT_OPTION to define the default option to use according the compilation flags CONFIG_SYS_ARM_CACHE_*. This new compilation flag allows to simplify dram_bank_mmu_setup() and can be used as third parameter (option=dcache option to select) of mmu_set_region_dcache_behaviour function. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | configs: migrate CONFIG_SYS_ARM_CACHE_* in KconfigPatrick Delaunay2020-05-011-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move CONFIG_SYS_ARM_CACHE_WRITETHROUGH and CONFIG_SYS_ARM_CACHE_WRITEALLOC into Kconfig done by moveconfig.py. Kconfig uses a choice between the 3 values supported in U-Boot, including the new configuration CONFIG_SYS_ARM_CACHE_WRITEBACK (the default configuration). The patch also avoids to select simultaneously 2 configurations. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* | | cpu: imx8: show RevC instead of Rev? at boot logFrank Li2020-05-031-0/+1
| |/ |/| | | | | | | | | | | | | Add REVC informaiton. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | imx8: Configure SNVSFranck LENORMAND2020-05-012-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a module to configure the tamper and secure violation of the SNVS using the SCU API. The module also adds some commands: - snvs_cfg: Configure the SNVS HP and LP registers - snvs_dgo_cfg: Configure the SNVS DGO bloc if present (8QXP) - tamper_pin_cfg: Change the configuration of the tamper pins - snvs_clear_status: Allow to write to LPSR and LPTDSR to clear status bits Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | imx8: Update SCFW API to version 1.5Ye Li2020-05-014-21/+76
| | | | | | | | | | | | | | | | | | | | | | Sync the latest SCFW API with below commit 6dcd0242ae7a53ac ("SCF-105: Revert accidental change") to add interfaces for PM resource reset and read/write SNVS security violation and tamper DGO registers. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | imx8: scu api: Add support for SECO manufacturing protection APIsBreno Lima2020-05-011-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | SECO provides APIs to support CAAM manufacturing protection: - sc_seco_get_mp_key() - sc_seco_get_mp_sign() - sc_seco_update_mpmr() Add SCFW APIs support. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Breno Lima <breno.lima@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | imx8mm: clock: fix fracpll decode issueYe Li2020-05-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | The fracpll decoding is using the bit definitions for int pll. Most of them are same, but the CLKE bit is different. Fix the wrong CLKE_MASK for fracpll and correct all bit definitions in fracpll decoding. Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | imx8mq: Set ARM core clock directly from ARM PLLPeng Fan2020-05-011-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For ARM core clock, there are two input branches, and can select via mux: one from ARM PLL directly, second from CCM A53 clock root. Currently we are using second branch. But IC confirmed the CCM A53 root signoff timing is 1Ghz, so we should switch to input from ARM PLL directly. This patch fixes the CORE SEL slice configuration and switch ARM clock to ARM PLL. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | imx8m: update clock root and fix core_selPeng Fan2020-05-011-1/+2
| | | | | | | | | | | | | | | | | | Update clock root table to let it be easy to configure clock at very early stage. Also the core_sel mux parent should be A53 CLK root and ARM PLL. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | imx: update is_imx6ull to include i.MX6ULZPeng Fan2020-05-011-1/+1
| | | | | | | | | | | | | | | | Update is_imx6ull helper to include i.MX6ULZ SoC. i.MX6ULZ could share same macro, then we no need to add is_imx6ulz in various drivers. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | imx: imx8m: add i.MX8MN variants supportPeng Fan2020-05-012-1/+13
| | | | | | | | | | | | | | Add i.MX8MN variants support Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | imx: imx8m: add i.MX8MQ Dual and QuadLite supportPeng Fan2020-05-012-1/+5
| | | | | | | | | | | | | | Add i.MX8MQ Dual and QuadLite variants. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
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