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* arm: Add new config option ARCH_VERY_EARLY_INITPali Rohár2022-05-161-0/+5
| | | | | | | | | | When this option is set then ARM _main() function would call arch_very_early_init() function at the beginning. It would be before calling any other functions like debug_uart_init() and also before initializing C runtime environment. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
* arm: Do not compile vector table when SYS_NO_VECTOR_TABLE is enabledPali Rohár2022-04-211-0/+6
| | | | | | | Vector table is not used when SYS_NO_VECTOR_TABLE is enabled. So do not compile it and reduce image size. Signed-off-by: Pali Rohár <pali@kernel.org>
* arm: init: save previous bootloader dataDzmitry Sankouski2022-04-042-0/+96
| | | | | | | | | | | | | | | | | | | | When u-boot is used as a chain-loaded bootloader (replacing OS kernel), previous bootloader leaves data in RAM, that can be reused. For example, on recent arm linux system, when chainloading u-boot, there are initramfs and fdt in RAM prepared for OS booting. Initramfs may be modified to store u-boot's payload, thus providing the ability to use chainloaded u-boot to boot OS without any storage support. Two config options added: - SAVE_PREV_BL_INITRAMFS_START_ADDR saves initramfs start address to 'prevbl_initrd_start_addr' environment variable - SAVE_PREV_BL_FDT_ADDR saves fdt address to 'prevbl_fdt_addr' environment variable Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Cc: Tom Rini <trini@konsulko.com>
* arm64: Catch non-emulated semihosting callsSean Anderson2022-04-011-0/+47
| | | | | | | | | | | | | | | | | | | | | | | If a debugger is not attached to U-Boot, semihosting calls will raise a synchronous abort exception. Try to catch this and disable semihosting so we can e.g. use another uart if one is available. In the immediate case, we return an error, since it is not always possible to check for semihosting beforehand (debug uart, user-initiated load command, etc.) We handle all possible semihosting instructions, which is probably overkill. However, we do need to keep track of what instruction set we're using so that we don't suppress an actual error. A future enhancement could try to determine semihosting capability by inspecting the processor state. There's an example of this at [1] for RISC-V. The equivalent for ARM would inspect the monitor modei enable/select bits of the DSCR. However, as the article notes, an exception handler is still helpful in order to catch disconnected debuggers. [1] https://tomverbeure.github.io/2021/12/30/Semihosting-on-RISCV.html#avoiding-hangs-when-a-debugger-is-not-connected Signed-off-by: Sean Anderson <sean.anderson@seco.com>
* arm: smh: Add option to detect semihostingSean Anderson2022-04-011-0/+21
| | | | | | | | | | | | | | | | | | | | | | These functions are intended to support detecting semihosting and falling back gracefully to alternative implementations. The test starts by making semihosting call. SYS_ERRNO is chosen because it should not mutate any state. If this semihosting call results in an exception (rather than being caught by the debugger), then the exception handler should call disable_semihosting() and resume execution after the call. Ideally, this would just be part of semihosting by default, and not a separate config. However, to reduce space ARM SPL doesn't include exception vectors by default. This means we can't detect if a semihosting call failed unless we enable them. To avoid forcing them to be enabled, we use a separate config option. It might also be possible to try and detect whether a debugger has enabled (by reading HDE from DSCR), but I wasn't able to figure out a way to do this from all ELs. This patch just introduces the generic code to handle detection. The next patch will implement it for arm64 (but not arm32). Signed-off-by: Sean Anderson <sean.anderson@seco.com>
* arm64: Save esr in pt_regsSean Anderson2022-04-011-16/+17
| | | | | | | | | To avoid passing around an extra register everywhere, save esr in pt_regs like the rest. For proper alignment we need to have a second (unused) register. All the printfs have to be adjusted, since it's now an unsigned long and not an int. Signed-off-by: Sean Anderson <sean.anderson@seco.com>
* arm: smh: Add some functions for working with the host consoleSean Anderson2022-04-011-0/+18
| | | | | | | | This adds three wrappers around the semihosting commands for reading and writing to the host console. We use the more standard getc/putc/puts names instead of readc/writec/write0 for familiarity. Signed-off-by: Sean Anderson <sean.anderson@seco.com>
* arm: smh: Remove smhload commandSean Anderson2022-04-011-76/+0
| | | | | | | | This command's functionality is now completely implemented by the standard fs load command. Convert the vexpress64 boot command (which is the only user) and remove the implementation. Signed-off-by: Sean Anderson <sean.anderson@seco.com>
* cmd: fdt: Use start/size for chosen instead of start/endSean Anderson2022-04-011-8/+8
| | | | | | | | | | Most U-Boot command deal with start/size instead of start/end. Convert the "fdt chosen" command to use these semantics as well. The only user of this subcommand is vexpress, so convert the smhload command to use this as well. We don't bother renaming the variable in vexpress64's bootcommand, since it will be rewritten in the next commit. Signed-off-by: Sean Anderson <sean.anderson@seco.com>
* spl: Add semihosting boot methodSean Anderson2022-04-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a boot method for loading the next stage from the host. It is mostly modeled off of spl_load_image_ext. I am not really sure why/how spl_load_image_fat uses three different methods to load the image, but the simple case seems to work OK for now. To control the presence of this boot method, we add a config symbol. While we're at it, we update the original semihosting config symbol. I think semihosting has some advantages of other forms of JTAG boot. Common other ways to boot from JTAG include: - Implementing DDR initialization through JTAG (typically with dozens of lines of TCL) and then loading U-Boot. The DDR initialization typically uses hard-coded register writes, and is not easily adapted to different boards. BOOT_DEVICE_SMH allows booting with SPL, leveraging U-Boot's existing DDR initialization code. This is the method used by NXP's CodeWarrior IDE on Layerscape processors (see AN12270). - Loading a bootloader into SDRAM, waiting for it to initialize DDR, and then loading U-Boot. This is tricky, because the debugger must stop the boot after the bootloader has completed its work. Trying to load U-Boot too early can cause failure to boot. This is the method used by Xilinx with its Zynq(MP) processors. - Loading SPL with BOOT_DEVICE_RAM and breaking before SPL loads the image to load U-Boot at the appropriate place. This can be a bit tricky, because the load address is dependent on the header size. An elf with symbols must also be used in order to stop at the appropriate point. BOOT_DEVICE_SMH can be viewed as an extension of this process, where SPL automatically stops and tells the host where to place the image. Signed-off-by: Sean Anderson <sean.anderson@seco.com>
* arm: smh: Add some file manipulation commandsSean Anderson2022-04-011-11/+56
| | | | | | | In order to add filesystem support, we will need to be able to seek and write files. Add the appropriate helper functions. Signed-off-by: Sean Anderson <sean.anderson@seco.com>
* arm: smh: Document functions in headerSean Anderson2022-04-011-9/+0
| | | | | | This adds some documentation for semihosting functions in the header. Signed-off-by: Sean Anderson <sean.anderson@seco.com>
* arm: smh: Return errno on errorSean Anderson2022-04-011-31/+36
| | | | | | | | | Instead of printing in what are now library functions, try to return a numeric error code. This also adjust some functions (such as read) to behave more similarly to read(2). For example, we now return the number of bytes read instead of failing immediately on a short read. Signed-off-by: Sean Anderson <sean.anderson@seco.com>
* arm: smh: Use numeric modes for smh_openSean Anderson2022-04-011-18/+3
| | | | | | | | | | There's no point in using string constants for smh_open if we are just going to have to parse them. Instead, use numeric modes. The user needs to be a bit careful with these, since they are much closer semantically to string modes used by fopen(3) than the numeric modes used with open(2). Signed-off-by: Sean Anderson <sean.anderson@seco.com>
* arm: smh: Export semihosting functionsSean Anderson2022-04-011-5/+6
| | | | | | | | | | | This exports semihosting functions for use in other files. The header is in include/ and not arm/include/asm because I anticipate that RISC-V may want to add their own implementation at some point. smh_len_fd has been renamed to smh_flen to more closely match the semihosting spec. Signed-off-by: Sean Anderson <sean.anderson@seco.com>
* efi_loader: fix SectionAlignment, FileAlignmentHeinrich Schuchardt2022-01-154-8/+10
| | | | | | | | | | | | | | | The alignment of sections in the EFI binaries generated by U-Boot is incorrect. According to the PE-COFF specification [1] the minimum value for FileAlignment is 512. If the value of SectionAlignment is less then the page size, it must equal FileAlignment. Let's set both values to 512 for the ARM and RISC-V architectures. [1] https://docs.microsoft.com/en-us/windows/win32/debug/pe-format Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
* Merge tag 'v2022.01-rc3' into nextTom Rini2021-11-292-1/+5
|\ | | | | | | | | | | Prepare v2022.01-rc3 Signed-off-by: Tom Rini <trini@konsulko.com>
| * arm64: Add missing GD_FLG_SKIP_RELOC handlingMarek Vasut2021-11-181-0/+4
| | | | | | | | | | | | | | | | | | | | In case U-Boot enters relocation with GD_FLG_SKIP_RELOC, skip the relocation. The code still has to set up new_gd pointer and new stack pointer. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
| * arm: Fix bad memcpy.S str8w macro argument countPierre-Clément Tosi2021-11-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the extra (empty) argument passed to str8w, causing the following error: <instantiation>:40:47: error: too many positional arguments str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f ^ u-boot/arch/arm/lib/memcpy.S:240:5: note: while in macro instantiation 17: forward_copy_shift pull=16 push=16 ^ Note: no functional change intended. Fixes: d8834a1323af ("arm: Use optimized memcpy and memset from linux") Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
* | arm: Init the debug UARTSimon Glass2021-11-172-0/+8
|/ | | | | | | | | | | | At present we don't init the debug UART in the generic ARM code, but instead leave it to individual machines to handle. This is not the way it is supposed to work. Add the required init to the crt files. This ensures that the UART is available as early as possible and that the announcement appears when it should, if enabled. Signed-off-by: Simon Glass <sjg@chromium.org>
* spl: Make use of CONFIG_IS_ENABLED(OS_BOOT) in SPL/TPL common code pathsTom Rini2021-11-051-1/+1
| | | | | | | | | | | When building a system that has both TPL and SPL_OS_BOOT, code which tests for CONFIG_SPL_OS_BOOT will be built and enabled in TPL, which is not correct. While there is no CONFIG_TPL_OS_BOOT symbol at this time (and likely will not ever be) we can use CONFIG_IS_ENABLED(OS_BOOT) in these common paths to ensure we only compile these parts in the SPL case. Signed-off-by: Tom Rini <trini@konsulko.com>
* Revert "arch: arm: use dt and UCLASS_SYSCON to get gic lpi details"Michael Walle2021-10-311-58/+8
| | | | | | | | | | Stop using the device tree as a source for ad-hoc information. This reverts commit 2ae7adc659f7fca9ea65df4318e5bca2b8274310. Signed-off-by: Michael Walle <michael@walle.cc> [trini: Also make board/broadcom/bcmns3/ns3.c fail clearly now] Signed-off-by: Tom Rini <trini@konsulko.com>
* arm: spl: prepare for jumping to OPTEERicardo Salveti2021-10-251-0/+11
| | | | | | | | | | | Make sure to (if applicable) flush the D-cache, invalidate I-cache, and disable MMU and caches before jumping to OPTEE. This fixes the SDP->SPL->OPTEE boot flow on iMX6Q and most likely on some other ARM SoCs. Signed-off-by: Ricardo Salveti <ricardo@foundries.io> Co-developed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
* image: Drop IMAGE_ENABLE_OF_LIBFDTSimon Glass2021-10-081-2/+2
| | | | | | | | | Add a host Kconfig for OF_LIBFDT. With this we can use CONFIG_IS_ENABLED(OF_LIBFDT) directly in the tools build, so drop the unnecessary indirection. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* arm: Remove zmx25 board and ARCH_MX25Tom Rini2021-10-011-37/+1
| | | | | | | | | | This board has not been converted to CONFIG_DM by the deadline. Remove it. As this is the last ARCH_MX25 platform, remove those references as well. Cc: Matthias Weisser <weisserm@arcor.de> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
* arm: Remove flea3 boardTom Rini2021-10-011-51/+1
| | | | | | | | | | This board has not been converted to CONFIG_DM by the deadline. Remove it. As this is the last mx35 platform, remove that support as well. Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Stefano Babic <sbabic@denx.de>
* WS cleanup: remove SPACE(s) followed by TABWIP/2021-09-30-whitespace-cleanupsWolfgang Denk2021-09-302-6/+6
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* WS cleanup: remove trailing white spaceWolfgang Denk2021-09-301-3/+3
| | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* WS cleanup: remove trailing empty linesWolfgang Denk2021-09-301-1/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* arm64: memset-arm64: Use simple memset when cache is disabledStefan Roese2021-09-241-0/+32
| | | | | | | | | The optimized memset uses the dc opcode, which causes problems when the cache is disabled. This patch adds a check if the cache is disabled and uses a very simple memset implementation in this case. Otherwise the optimized version is used. Signed-off-by: Stefan Roese <sr@denx.de>
* arm64: arch/arm/lib: Add optimized memset/memcpy/memmove functionsStefan Roese2021-09-244-0/+461
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Ported from https://github.com/ARM-software/optimized-routines These files are included from this repository, including the latest git commit ID: string/aarch64/memcpy.S: afd6244a1f8d string/aarch64/memset.S: e823e3abf5f8 string/asmdefs.h: e823e3abf5f8 Note that memmove is also handled by the memcpy function. Please note that when adding these optimized functions as default memset memcpy functions in U-Boot, U-Boot fails to boot on the LX2160ARDB. After the initial ATF output, no U-Boot output is shown on the serial console. Some exception is triggered here in the very early boot process as some of the assembler opcodes need the caches to be enabled. Because of this, a follow-up patch will add a check to use a simple non-optimized memset for the "cache disabled" case. Note: I also integrated and tested with the Linux versions of these optimized functions. They are similar to the ones now integrated but these ARM versions are still a small bit faster. Signed-off-by: Stefan Roese <sr@denx.de>
* lmb: arm: Increase LMB alignment to 16k in arch_lmb_reserve_generic()Marek Vasut2021-09-231-1/+1
| | | | | | | | | | | | | | | | | | | | According to input NXP, the 4k alignment is not always sufficient. Currently iMX works around this problem by implementing board specific LMB reservation, however it is likely this could also occur on other systems. Increase the LMB reservation alignment to 16k by default. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Alexey Brodkin <alexey.brodkin@synopsys.com> Cc: Angelo Dureghello <angelo@sysam.it> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Cc: Hai Pham <hai.pham.ud@renesas.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Ye Li <ye.li@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* lmb: Switch to generic arch_lmb_reserve_generic()Marek Vasut2021-09-231-32/+1
| | | | | | | | | | | | | | | | | Switch arc/arm/m68k/microblaze/mips/ppc arch_lmb_reserve() to arch_lmb_reserve_generic(). Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Alexey Brodkin <alexey.brodkin@synopsys.com> Cc: Angelo Dureghello <angelo@sysam.it> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Cc: Hai Pham <hai.pham.ud@renesas.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Wolfgang Denk <wd@denx.de>
* lmb: Always compile arch_lmb_reserve() into U-Boot on armMarek Vasut2021-09-232-45/+45
| | | | | | | | | | | | | | | | | | | The arch_lmb_reserve() is called by lib/lmb.c lmb_reserve_common() even if CMD_BOOT{I,M,Z} is not enabled. However, the arm32/arm64 variant of arch_lmb_reserve() is only compiled in if CMD_BOOT{I,M,Z} is enabled. This currently does not trigger build error, because there is an empty weak implementation of arch_lmb_reserve(), however that is not the function that should be used on arm32/arm64. Fix this by moving the arch_lmb_reserve() implementation into common code and always compile it in. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tom Rini <trini@konsulko.com>
* Revert most of the series for adding vexpress_aemv8r supportWIP/03Sep2021-nextTom Rini2021-09-031-25/+15
| | | | | | | | | | | | | | | | Per a request from Andre Przywara and agreed with by Peter Hoyes, the vexpress aemv8r support wasn't quite ready to be merged, but the discussion had moved off list. We should keep the first patch in the series for now, but revert the rest. This reverts the following commits: e0bd6f31ce41 doc: Add documentation for the Arm vexpress board configs 30e5a449e8c7 arm: Use armv8_switch_to_el1 env to switch to EL1 b53bbca63bf4 vexpress64: Add BASER_FVP vexpress board variant 2f5b7b74903f armv8: Add ARMv8 MPU configuration logic 37a757e227cc armv8: Ensure EL1&0 VMSA is enabled Signed-off-by: Tom Rini <trini@konsulko.com>
* arm: Use armv8_switch_to_el1 env to switch to EL1Peter Hoyes2021-09-021-15/+25
| | | | | | | | | | | | | | | Use the environment variable armv8_switch_to_el1 to determine whether to switch to EL1 at runtime. This is an alternative to the CONFIG_ARMV8_SWITCH_TO_EL1 compile-time option. The environment variable will be ineffective if the ARMV8_MULTIENTRY config is used. This is required by the Armv8r64 architecture, which must be able to boot at S-EL1 for Linux but may need to boot at other ELs for other systems. Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
* armv7: Add Position Independent Execution supportChia-Wei Wang2021-09-022-10/+36
| | | | | | | | | | | | | | | | | | | A U-Boot image could be loaded and executed at a different location than it was linked at. For example, Aspeed takes a stable release version of U-Boot image as the golden one for recovery purposes. When the primary storage such as flash is corrupted, the golden image would be loaded to any SRAM/DRAM address on demands through ethernet/UART/etc and run for rescue. To deal with this condition, the PIE is needed as there is only one signed, golden image, which could be however executed at different places. This patch adds the PIE support for ARMv7 platform. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
* Revert "arm: bootm: Disable LMB reservation for command line and board info ↵Jan Kiszka2021-08-081-2/+0
| | | | | | | | | | | | | | | | | | on arm64" This reverts commit 2359fa7a87848626bcbd3399e92c657595880cd7. While the goal is valid and there is surely unused memory in that area, we also have a lot of crucial things still located at the top-of-memory while running lmb_alloc_base. Such things are the page table (tlb_addr), relocated U-Boot and the active stack. Possibly more. So this patch was premature, we will need relocations of those things first if we want to use the range. Fixes booting on the IOT2050, but likely also on other boards. It got stuck on relocating the FDT - over the relocated U-Boot code. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
* global: Convert simple_strtoul() with hex to hextoul()Simon Glass2021-08-021-1/+1
| | | | | | | | | It is a pain to have to specify the value 16 in each call. Add a new hextoul() function and update the code to use it. Add a proper comment to simple_strtoul() while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: bootm: Disable LMB reservation for command line and board info on arm64Marek Vasut2021-07-091-0/+2
| | | | | | | | | | | | | | | | | On arm64, board info is not applicable and kernel command line patched into the DT, so the LMB reservation here makes no sense anymore. On legacy arm32, this might still be necessary on systems which do not use DT or use legacy ATAGS. Disable this LMB reservation on arm64. This also permits Linux DT to specify reserved memory node at address close to the end of DRAM bank, i.e. overlaping with U-Boot location. Since after boot, U-Boot will be no more, this is OK. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Hai Pham <hai.pham.ud@renesas.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Tom Rini <trini@konsulko.com>
* arch: cache: cp15: Add mmu_set_region_dcache_behaviour() when SYS_DCACHE_OFF ↵Patrice Chotard2021-07-091-6/+12
| | | | | | | | | | | | | | is enable Fix following compilation issue when SYS_DCACHE_OFF is enable: drivers/misc/scmi_agent.c:128: undefined reference to `mmu_set_region_dcache_behaviour' when SYS_DCACHE_OFF is enable, mmu_set_region_dcache_behaviour() must be defined. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
* arm64: Fix relocation of env_addr if POSITION_INDEPENDENT=yKunihiko Hayashi2021-06-281-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If both POSITION_INDEPENDENT and SYS_RELOC_GD_ENV_ADDR are enabled, wherever original env is placed anywhere, it should be relocated to the right address. Relocation offset gd->reloc_off is calculated with SYS_TEXT_BASE in setup_reloc() and env address gd->env_addr is relocated by the offset in initr_reloc_global_data(). gd->env_addr = (orig env) + gd->reloc_off = (orig env) + (gd->relocaddr - SYS_TEXT_BASE) However, SYS_TEXT_BASE isn't always runtime base address when POSITION_INDEPENDENT is enabled. So the relocated env_addr might point to wrong address. For example, if SYS_TEXT_BASE is zero, gd->env_addr is out of memory location and memory exception will occur. There is a difference between linked address such as SYS_TEXT_BASE and runtime base address. In _main, the difference is calculated as "run-vs-link" offset. The env_addr should also be added to the offset to fix the address. gd->env_addr = (orig env) + ("run-vs-link" offset) + gd->reloc_off = (orig env) + (SYS_TEXT_BASE - _start) + (gd->relocaddr - SYS_TEXT_BASE) = (orig env) + (gd->relocaddr - _start) Cc: Marek Vasut <marex@denx.de> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Marek Vasut <marex@denx.de>
* ARM: make LTO availableMarek Behún2021-05-241-0/+2
| | | | | | | Make LTO available for ARM architecture. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: fix LTO build for some thumb-interwork casesMarek Behún2021-05-241-0/+1
| | | | | | | | | | | | Fix LTO build for some thumb-interwork usecases (such as for da850evm_defconfig), where inline assmebly such as mrc p15,0,r2,c1,c0,0 causes the compiler to fail during LTO linking with Error: selected processor does not support `mrc p15,0,r2,c1,c0,0' in Thumb mode Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org>
* treewide: Convert macro and uses of __section(foo) to __section("foo")Marek Behún2021-05-242-16/+17
| | | | | | | | | | | | | | | | | This commit does the same thing as Linux commit 33def8498fdd. Use a more generic form for __section that requires quotes to avoid complications with clang and gcc differences. Remove the quote operator # from compiler_attributes.h __section macro. Convert all unquoted __section(foo) uses to quoted __section("foo"). Also convert __attribute__((section("foo"))) uses to __section("foo") even if the __attribute__ has multiple list entry forms. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: zimage: Use correct symbol to hide messages in SPLSamuel Holland2021-04-271-7/+5
| | | | | | | | | | | | When zImage support was added to SPL, the messages were hidden to reduce code size. However, the wrong config symbol was used. Since this file is only built when CONFIG_SPL_FRAMEWORK=y, the messages were always hidden. Use the correct symbol so the messages are printed in U-Boot proper. Also use IS_ENABLED to drop the #ifdef. Fixes: 431889d6ad9a ("spl: zImage support in Falcon mode") Signed-off-by: Samuel Holland <samuel@sholland.org>
* arm64: gic-v3-its: Clear the Pending table before enabling LPIsHou Zhiqiang2021-04-201-1/+11
| | | | | | | | | | | | | | | | | | | | | | | The GICv3 RM requires "The first 1KB of memory for the LPI Pending tables must contain only zeros on initial allocation, and this must be visible to the Redistributors, or else the effect is UNPREDICTABLE". And as the following statement, we here clear the whole Pending tables instead of the first 1KB. "An LPI Pending table that contains only zeros, including in the first 1KB, indicates that there are no pending LPIs. The first 1KB of the LPI Pending table is IMPLEMENTATION DEFINED. However, if the first 1KB of the LPI Pending table and the rest of the table contain only zeros, this must indicate that there are no pending LPIs." And there isn't any pending LPI under U-Boot, so it's unnecessary to load the contents of the Pending table during the enablement, then set the GICR_PENDBASER.PTZ flag. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> # NXP LS1028A Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* bootm: do not hang on failureHeinrich Schuchardt2021-04-121-5/+2
| | | | | | | | | | | | | | | | | | | On ARMv8 systems load mmc 0:1 $loadaddr vmlinuz-5.10.0-3-arm64 booti leads to a hanging system requiring to physically reset the system: FDT and ATAGS support not compiled in - hanging ### ERROR ### Please RESET the board ### For systems where physical access is difficult hanging is a poor choice. It is preferable to reset the system when U-Boot reaches a state that is not recoverable. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: cp15: remove weak function arm_init_domainsPatrick Delaunay2021-03-021-6/+0
| | | | | | | Remove the unused weak function arm_init_domains used to change the DACR value. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
* arm: cp15: update DACR value to activate access controlPatrick Delaunay2021-03-021-2/+5
| | | | | | | | | | | | | | | | | | | | | | | Update the initial value of Domain Access Control Register (DACR) and set by default the access permission to client (DACR_Dn_CLIENT = 1U) for each of the 16 domains and no more to all-supervisor (DACR_Dn_MANAGER = 3U). This patch allows to activate the domain checking in MMU against the permission bits in the translation tables and avoids prefetching issue on ARMv7 [1]. Today it was already done for OMAP2 architecture ./arch/arm/mach-omap2/omap-cache.c::arm_init_domains introduced by commit de63ac278cba ("ARM: mmu: Set domain permissions to client access") which fixes lot of speculative prefetch aborts seen on OMAP5 secure devices. [1] https://developer.arm.com/documentation/ddi0406/b/System-Level-Architecture/Virtual-Memory-System-Architecture--VMSA-/Memory-access-control/The-Execute-Never--XN--attribute-and-instruction-prefetching Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reported-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
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