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path: root/arch/arm/mach-socfpga/include
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* arm: socfpga: fix SPL booting from fpga OnChip RAMSimon Goldschmidt2018-11-292-0/+10
* arm: socfpga: Remove unused function socfpga_emac_manage_reset()Ley Foon Tan2018-10-031-2/+0
* socfpga: stratix10: fix sdram_calculate_sizeDalon Westergreen2018-09-151-1/+1
* ARM: socfpga: Reorder Arria10 SPLMarek Vasut2018-08-242-1/+7
* arm: socfpga: Fix SYSMGR_FPGAINTF_EMACx bit maskLey Foon Tan2018-08-151-3/+3
* ARM: socfpga: clk: Convert to clock frameworkMarek Vasut2018-08-131-6/+0
* ARM: socfpga: Zap unused reset codeMarek Vasut2018-08-131-3/+0
* ARM: socfpga: Zap all the UART handling complexityMarek Vasut2018-08-132-7/+0
* arm: socfpga: gen5: combine some init code for SPL and U-BootSimon Goldschmidt2018-08-131-0/+4
* ddr: altera: stratix10: Add DDR support for Stratix10 SoCLey Foon Tan2018-07-121-0/+183
* arm: socfpga: stratix10: Add SPL driver for Stratix10 SoCLey Foon Tan2018-07-121-0/+120
* arm: socfpga: stratix10: Add mailbox support for Stratix10 SoCLey Foon Tan2018-07-121-0/+144
* arm: socfpga: misc: Move bridge command to misc commonLey Foon Tan2018-07-121-0/+2
* SPDX: Fixup SPDX tags in a few new filesTom Rini2018-05-201-2/+1
* arm: socfpga: stratix10: Add pinmux support for Stratix10 SoCLey Foon Tan2018-05-182-1/+180
* arm: socfpga: stratix10: Add reset manager driver for Stratix10 SoCLey Foon Tan2018-05-182-0/+118
* arm: socfpga: stratix10: Add clock manager driver for Stratix10 SoCLey Foon Tan2018-05-183-0/+246
* arm: socfpga: stratix10: Add watchdog and firewall base addressesLey Foon Tan2018-05-181-0/+11
* ARM: socfpga: Fix Documentation errors in scu_registersBen Kalo2018-05-181-2/+2
* ARM: socfpga: Add DDR driver for Arria 10Tien Fong Chee2018-05-182-0/+4
* ARM: socfpga: Rename the gen5 sdram driver to more specific nameTien Fong Chee2018-05-182-429/+445
* ARM: socfpga: Repair A10 EMAC reset handlingMarek Vasut2018-05-181-0/+2
* ARM: socfpga: Sync A10 clock manager binding parserMarek Vasut2018-05-181-1/+1
* ARM: socfpga: Zap CONFIG_SOCFPGA_VIRTUAL_TARGETMarek Vasut2018-05-181-4/+0
* ARM: socfpga: Add boot trampoline for Arria10Marek Vasut2018-05-081-2/+2
* SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini2018-05-0726-52/+26
* arm: socfpga: stratix10: Add base address map for Statix10 SoCChin Liang See2018-04-171-0/+33
* socfpga: boot0 hook: adjust to unified boot0 semanticsPhilipp Tomsich2017-11-211-0/+3
* arm: socfpga: Add FPGA driver support for Arria 10Tien Fong Chee2017-07-262-0/+102
* arm: socfpga: Restructure FPGA driver in the preparation to support A10Tien Fong Chee2017-07-262-56/+80
* arm: socfpga: Remove unused passing parameter of socfpga_bridges_resetTien Fong Chee2017-07-261-1/+1
* arm: socfpga: Add misc support for Arria 10Ley Foon Tan2017-05-181-0/+6
* arm: socfpga: Add pinmux for Arria 10Ley Foon Tan2017-05-181-0/+17
* arm: socfpga: Add sdram header file for Arria 10Ley Foon Tan2017-05-181-0/+380
* arm: socfpga: Add system manager for Arria 10Ley Foon Tan2017-05-182-11/+144
* arm: socfpga: Add clock driver for Arria 10Ley Foon Tan2017-05-182-0/+227
* arm: socfpga: Add reset driver support for Arria 10Ley Foon Tan2017-05-182-0/+149
* arm: socfpga: Add A10 macrosLey Foon Tan2017-05-181-1/+7
* arm: socfpga: Restructure misc driverLey Foon Tan2017-05-181-0/+25
* arm: socfpga: Restructure system managerLey Foon Tan2017-05-182-118/+132
* arm: socfpga: Restructure reset manager driverLey Foon Tan2017-05-182-41/+57
* arm: socfpga: Restructure clock manager driverLey Foon Tan2017-05-182-307/+331
* ARM: socfpga: boot0 hook: remove macro from boot0 header fileChee, Tien Fong2017-04-141-14/+10
* arm: socfpga: set the mpuclk divider in the Altera group registerDinh Nguyen2017-02-081-0/+3
* ARM: socfpga: Add boot0 hook to prevent SPL corruptionMarek Vasut2016-12-061-0/+28
* ddr: altera: Configuring SDRAM extra cycles timing parametersChin Liang See2016-10-271-1/+7
* arm: socfpga: Nuke useless includeMarek Vasut2016-04-101-12/+0
* arm: socfpga: Define NAND reset bitMarek Vasut2015-12-221-1/+2
* arm: socfpga: fix up a questionable macro for SDMMCDinh Nguyen2015-12-201-3/+7
* ARM: socfpga: rename the cyclone5 and arria5 base address fileDinh Nguyen2015-11-301-0/+0
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