| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | sunxi: add LPDDR3 DRAM type support for DesignWare-like DRAM controller | Icenowy Zheng | 2017-06-08 | 1 | -0/+2 |
| * | sunxi: add support for V3s DRAM controller | Icenowy Zheng | 2017-06-08 | 1 | -0/+3 |
| * | sunxi: add support for the DDR2 in V3s SoC | Icenowy Zheng | 2017-06-08 | 1 | -0/+2 |
| * | sunxi: enable dual rank detection in DesignWare-like DRAM code | Icenowy Zheng | 2017-06-08 | 1 | -1/+3 |
| * | sunxi: Add selective DRAM type and timing | Icenowy Zheng | 2017-06-08 | 1 | -113/+6 |
| * | sunxi: add bank detection code to H3 DRAM initialization code | Icenowy Zheng | 2017-06-08 | 1 | -4/+15 |
| * | sunxi: add option for 16-bit DW DRAM controller | Icenowy Zheng | 2017-06-08 | 1 | -4/+29 |
| * | sunxi: Rename bus-width related macros in H3 DRAM code | Icenowy Zheng | 2017-06-08 | 1 | -5/+6 |
| * | sunxi: makes an invisible option for H3-like DRAM controllers | Icenowy Zheng | 2017-06-08 | 1 | -0/+829 |
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index : delta/u-boot.git | |
| gitlab.denx.de: u-boot/u-boot.git |
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