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* arm64: versal: Disable DDR cache mapping if DDR is not enabledMichal Simek2020-04-061-0/+6
| | | | | | | Similar change was done in past by commit 3b644a3c2f69 ("arm64: zynqmp: Provide a config to not map DDR region in MMU table"). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: versal: Move common board dtb searchIbai Erkiaga2019-10-081-5/+0
| | | | | | | | Move the exisiting function of getting board dtb from versal to a common Xilinx folder. Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Provide a Kconfig option to disable OCM and TCM MMU mappingMichal Simek2019-10-081-0/+7
| | | | | | | | | | This patch provides an option to enable/disable OCM and TCM memory into MMU table with corresponding memory attributes. The same change was done for ZynqMP by commit 189bec47ab1f ("arm64: zynqmp: Provide a Kconfig option to define OCM and TCM in MMU") Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: versal: Move IOU_SWITCH_DIVISOR0 to KconfigMichal Simek2019-02-141-0/+6
| | | | | | | Move hardcoded IOU_SWITCH_DIVISOR0 to Kconfig to be able to set it up for different platforms. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: versal: Add new Kconfig SYS_MEM_RSVD_FOR_MMUSiva Durga Prasad Paladugu2019-02-141-0/+7
| | | | | | | | | This patch adds new config option which is used for reserving a specific memory for MMU Table and in this case we are using TCM for that purpose. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: versal: Add Xilinx Versal Virtual QEMU boardMichal Simek2018-10-161-0/+5
| | | | | | | | | Virtual QEMU board is generating DTB self and putting it to VERSAL_QEMU_DTB_ADDR address. Board is using CONFIG_OF_BOARD which ensures that u-boot is aligned with board created by QEMU. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: versal: Add support for new Xilinx Versal ACAPsMichal Simek2018-10-161-0/+39
Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The Versal AI Core series has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex™-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency. The patch is adding necessary infrastructure in place without enabling platform which is done in separate patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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