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* dt: bcm63158: watchdog should use a 50Mhz clockPhilippe Reynes2019-05-181-2/+8
| | | | | | | | | | The watchdog should use a clock at 50 Mhz, so instead of using the clock osc (200 Mhz), we define a reference clock at 50Mhz and use it for both watchdog. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Stefan Roese <sr@denx.de>
* dt: bcm6858: watchdog should use a 50Mhz clockPhilippe Reynes2019-05-181-2/+8
| | | | | | | | | | The watchdog should use a clock at 50 Mhz, so instead of using the clock osc (200 Mhz), we define a reference clock at 50Mhz and use it for both watchdog. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Stefan Roese <sr@denx.de>
* CONFIG_SPL_SYS_[DI]CACHE_OFF: addTrevor Woerner2019-05-1840-73/+87
| | | | | | | | | | | | | While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com>
* CONFIG_SYS_[DI]CACHE_OFF: convert to KconfigTrevor Woerner2019-05-182-6/+12
| | | | | | | | | | | | | | | | | | | | CONFIG_SYS_[DI]CACHE_OFF had been partially converted to Kconfig parameters; only for the ARC architecture. This patch turns these two parameters into Kconfig items everywhere else they are found. All of the include/configs/* and defconfig changes in this patch are for arm machines only. The Kconfig changes for arc, nds32, riscv, and xtensa have been included since these symbols are found in code under arch/{arc,nds32,riscv,xtensa}, however, no currently-defined include/configs/* or defconfigs for these architectures exist which include these symbols. These results have been confirmed with tools/moveconfig.py. Acked-by: Alexey Brodkin <abrodkin@snopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Re-migrate for a few more boards] Signed-off-by: Tom Rini <trini@konsulko.com>
* CONFIG_SYS_[ID]CACHE_OFF: unify the 'any' caseTrevor Woerner2019-05-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to De Morgan's Law[1]: !(A && B) = !A || !B !(A || B) = !A && !B There are 5 places in the code where we find: #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) and 4 places in the code where we find: #if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)) In words, the construct: !defined(CONFIG_SYS_[DI]CACHE_OFF) means: "is the [DI]CACHE on?" and the construct: defined(CONFIG_SYS_[DI]CACHE_OFF) means: "is the [DI]CACHE off?" Therefore !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) means: "the opposite of 'are they both off?'" in other words: "are either or both on?" and: (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF) means: "are either or both on?" As a result, I've converted the 4 instances of '(!A || !B)' to '!(A && B)' for consistency. [1] https://en.wikipedia.org/wiki/De_Morgan%27s_laws Signed-off-by: Trevor Woerner <trevor@toganlabs.com>
* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2019-05-1614-41/+241
|\ | | | | | | - SoCFPGA DT and reset cleanup, AE MCVEVK board support.
| * ARM: dts: socfpga: Keep FPGA bridge entries in SPL DTMarek Vasut2019-05-141-0/+24
| | | | | | | | | | | | | | | | | | | | | | Keep the FPGA bridge entries in SPL DT to let do_bridge_reset() toggle the bridges on/off as needed according to the handoff file. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * ARM: dts: socfpga: Factor out U-Boot specifics from A10 handoff filesMarek Vasut2019-05-144-18/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull out the u-boot,dm-pre-reloc from socfpga_arria10_socdk_sdmmc_handoff.dtsi into separate dtsi header file to make it easier to patch in custom handoff dtsi files, without having to manually add the U-Boot bits. Shuffle the include clauses in the A10 DT files to make it obvious what gets included where without having to follow confusing long chain of includes, i.e. board DT file includes everything it needs. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * arm: socfpga: Re-add support for Aries MCV SoM and MCVEV[KP] boardWolfgang Grandegger2019-05-145-0/+145
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Re-add support for Aries Embedded MCV SoM, which is CycloneV based and the associated MCVEVK and MCVEVP baseboard. The board can boot from eMMC. Ethernet and USB is supported. The Aries Embedded boards have been removed with commit 03b54997d568 ("board/aries: Remove"). I will now take care of them. The device-tree files are from mainline Linux commit e93c9c99a629 ("Linux v5.1)". Signed-off-by: Wolfgang Grandegger <wg@aries-embedded.de> CC: Marek Vasut <marex@denx.de> CC: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * arm: sofcpga: s10: remove unused ad-hoc reset codeSimon Goldschmidt2019-05-142-12/+0
| | | | | | | | | | | | | | | | | | The stratix 10 reset manager ad-hoc code in arch/arm contains an unused function 'reset_deassert_peripherals_handoff' that has been added from the beginning. As this is probably a result of copying the gen5 reset manager and this function has never been used, remove it. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * arm: socfpga: remove re-added ad-hoc reset codeSimon Goldschmidt2019-05-143-11/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | commit c5de2b7eae68 ("arm: socfpga: implement proper peripheral reset") has removed the call to 'reset_deassert_peripherals_handoff()' from socfpga gen5 SPL since the reset driver now handles resets. However, commit c1d4b464c8b8 ("ARM: socfpga: Disable bridges in SPL unless booting from FPGA") has re-added this ad-hoc reset code, so that all peripherals were now again enabled instead of letting the drivers enable them by request. While at it, remove this function for gen5 as it should not be used. Fixes: commit c1d4b464c8b8 ("ARM: socfpga: Disable bridges in SPL unless booting from FPGA") Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* | Merge tag 'u-boot-stm32-mcu-20190514' of https://github.com/pchotard/u-bootTom Rini2019-05-155-6/+53
|\ \ | |/ |/| | | | | | | | | | | STM32 MCUs update: _ Add MPU region for SPI NOR memory mapped region _ Add missing QSPI flash compatible for STM32 F7 boards _ Update spi-tx-bus-width and spi-rx-bus-width properties _ Add QSPI support for STM32F469 Discovery board
| * ARM: dts: stm32: Add qspi support for stm32f469-disco boardPatrice Chotard2019-05-061-0/+39
| | | | | | | | | | | | Add device tree nodes to support qspi for stm32f469-disco board. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
| * ARM: dts: stm32: Set spi-rx/tx-bus-width to 4 for stm32f769-discoPatrice Chotard2019-05-061-0/+1
| | | | | | | | | | | | | | | | As mx66l512 qspi flash supports quad input fast program and quad input fast read, set spi-tx_bus-width and spi-rx_bus-width to 4. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
| * ARM: dts: stm32: Remove useless spi-nor compatible stringPatrice Chotard2019-05-061-1/+1
| | | | | | | | | | | | Compatible string "micron,n25q128a13" is useless, remove it. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
| * ARM: dts: stm32: Set spi-rx/tx-bus-width to 4 for stm32f746-discoPatrice Chotard2019-05-061-2/+2
| | | | | | | | | | | | | | | | As n25q128 qspi flash supports quad input fast program and quad input fast read, set spi-tx_bus-width and spi-rx_bus-width to 4. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
| * ARM: dts: stm32: Set spi-rx/tx-bus-width to 4 for stm32f746-evalPatrice Chotard2019-05-061-2/+2
| | | | | | | | | | | | | | | | As n25q512a qspi flash supports quad input fast program and quad input fast read, set spi-tx_bus-width and spi-rx_bus-width to 4. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
| * ARM: dts: stm32: add qspi flash compatible string for stm32f746-evalPatrice Chotard2019-05-061-0/+1
| | | | | | | | | | | | | | Add missing flash compatible string to be able to read/write into qspi flash. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
| * ARM: dts: stm32: add qspi flash compatible string for stm32f769-discoPatrice Chotard2019-05-061-0/+1
| | | | | | | | | | | | | | Add missing flash compatible string to be able to read/write into qspi flash. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
| * ARM: dts: stm32: Fix qspi memory map size for stm32f7 boardsPatrice Chotard2019-05-063-1/+3
| | | | | | | | | | | | | | | | | | | | stm32f746-disco embeds a 16Mb qspi flash, stm32f746-eval and stm32f769-disco embeds a 64Mb qspi flash. Update the reg property accordingly Remove deprecated memory-map property. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
| * mach-stm32: Add MPU region for spi-nor memory mapped regionPatrice Chotard2019-05-061-0/+3
| | | | | | | | | | | | | | | | | | | | | | The Quad-SPI interface is able to manage up to 256Mbytes Flash memory starting from 0x90000000 to 0x9FFFFFFF in the memory mapped mode. Add a dedicated MPU region into stm32_region_config. See application note AN4760 available at www.st.com Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | spl: socfpga: Implement fpga bitstream loading with socfpga loadfsTien Fong Chee2019-05-102-1/+31
| | | | | | | | | | | | | | | | Add support for loading FPGA bitstream to get DDR up running before U-Boot is loaded into DDR. Boot device initialization, generic firmware loader and SPL FAT support are required for this whole mechanism to work. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
* | ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loadingTien Fong Chee2019-05-102-2/+54
| | | | | | | | | | | | | | | | | | Add FPGA driver to support program FPGA with FPGA bitstream loading from filesystem. The driver are designed based on generic firmware loader framework. The driver can handle FPGA program operation from loading FPGA bitstream in flash to memory and then to program FPGA. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
* | arm: k3: config.mk: Use k3_gen_x509_cert.sh to generate boot imagesLokesh Vutla2019-05-091-29/+4
| | | | | | | | | | | | | | Instead of overlading makefile, use the k3_gen_x509_cert.sh script to generate boot images. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | arm: zimage: add barebox image magic numberChristoph Fritz2019-05-091-2/+4
| | | | | | | | | | | | | | For chainboot configurations or test environments, this patch allows booting barebox images by using command bootz. Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
* | Merge tag 'rockchip-for-v2019.07-rc1' of git://git.denx.de/u-boot-rockchipTom Rini2019-05-0958-73/+1621
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Improvements and new features: - split more rockchip pinctrl_core feature into per SoC - enable TPL for evb-rk3399 board - enable TPL/SPL for evb-px5 board - enable TPL and OP-TEE support for evb-rk3229 - update fix in arm common assembly start code for rockchip header file - update default SPL_FIT_GENERATOR for rockchip - rk3399 boards update to use '-u-boot.dtsi' - add new rk3399 boards: Nanopi M4, Nanopc T4 - enable sound for chromebook_minnie
| * | rockchip: rk3399: Add Nanopc T4 board supportJagan Teki2019-05-093-0/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial support for Nanopc T4 board. Specification - Rockchip RK3399 - Dual-Channel 4GB LPDDR3-1866 - SD card slot - 16GB eMMC - RTL8211E 1Gbps - AP6356S WiFI/BT - HDMI In/Out, DP, MIPI DSI/CSI, eDP - USB 3.0, 2.0 - USB Type C power and data - GPIO expansion ports - DC 12V/2A Commit details of rk3399-nanopc-t4.dts sync from Linux 5.1-rc2: "arm64: dts: rockchip: Add NanoPC-T4 IR receiver" (sha1: 95658e21b1707ad7844f873db2fdaa295109a5a3) Tested-by: Daniel Gröber <dxld@darkboxed.org> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: rk3399: Add Nanopi M4 board supportJagan Teki2019-05-094-0/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial support for Nanopi M4 board. Specification - Rockchip RK3399 - Dual-Channel 4GB LPDDR3-1866 - SD card slot - eMMC socket - RTL8211E 1Gbps - AP6356S WiFI/BT - HDMI In/Out, DP, MIPI DSI/CSI - USB 3.0 x4 - USB Type C power and data - GPIO1, GPIO2 expansion ports - DC5V/3A Commit details of rk3399-nanopi-m4.dts sync from Linux 5.1-rc2: "arm64: dts: rockchip: Refine nanopi4 differences" (sha1: c62ffaf5026d0b7633e62b2cea8450b5543c349a) Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * | rockchip: dts: rk3399: nanopi4: Use CD pin as RK_FUNC_1Jagan Teki2019-05-091-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Attaching GPIO functionality to SDMMC0_DET pin (which does in Linux base dts) make dwmmc driver "fail to detect the card". Card did not respond to voltage select! It may be because the existing driver can't support gpio card detection. So, change the pinctrl functionality from RK_FUNC_GPIO to RK_FUNC_1 like other rk3399 dts does via sdmmc_cd pin. Cc: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: dts: rk3399: Sync rk3399-nanopi4.dtsi from LinuxJagan Teki2019-05-081-0/+703
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sync rk3399-nanopi4.dtsi from Linux 5.1-rc2 tag. Linux commit details about the rk3399-nanopi4.dtsi sync: "arm64: dts: rockchip: Add nanopi4 bluetooth" (sha1: 3e2f0bb72be36aa6c14ee7f11ac4dd8014801030) Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | arm: rockchip: rk3399: Move common configs in KconfigJagan Teki2019-05-081-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Few SPL and U-Boot proper configs are common to all rk3399 target defconfigs, move them and select it from platform kconfig. Moved configs: - SPL_ATF - SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF - SPL_LOAD_FIT - SPL_CLK if SPL - SPL_PINCTRL if SPL - SPL_RAM if SPL - SPL_REGMAP if SPL - SPL_SYSCON if SPL - CLK - FIT - PINCTRL - RAM - REGMAP - SYSCON - DM_PMIC - DM_REGULATOR_FIXED Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: dts: rk3399: Sync pwm2_pin_pull_down from Linux 5.1-rc2Jagan Teki2019-05-081-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To make successful build with dts(i) files syncing from Linux 5.1-rc2 the rk3399.dtsi would require pwm2_pin_pull_down. So, sync the pwm2_pin_pull_down node from Linux 5.1-rc2. Since this node is strictly not part of any commit alone, I have mentioned Linux 5.1-rc2 tag for future reference of where would this sync coming from. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | arm64: rockchip: dts: rk3399: Use rk3399-u-boot.dtsiJagan Teki2019-05-087-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now we have - board specific -u-boot.dtsi files for board specific u-boot dts changes. - soc specific rk3399-u-boot.dtsi for soc specific u-boot dts changes. So, include the rk3399-u-boot-dtsi on respective board -u-boot.dtsi and drop the properties which are globally available in rk3399-u-boot.dtsi Right now rk3399-u-boot.dtsi has sdmmc, spi1 u-boot,dm-pre-reloc property and more properties and nodes can be move further based on the requirements. This would fix, the -u-boot.dtsi inclusion for evb, firefly, puma boards that was accidentally merged on below commit. "rockchip: dts: rk3399: Create initial rk3399-u-boot.dtsi" (sha1: e05b4a4fa84b65a0c8873e8f34721741fe2bc09d) Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: dts: rk3399-u-boot: Add u-boot, dm-pre-reloc for spi1Jagan Teki2019-05-081-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add u-boot,dm-pre-reloc property for spi1, so-that the subsequent rk3399 boards which boot from SPI. This help to separate the u-boot specific properties away from base dts files so-that the Linux sync become easy and meaningful. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | arm64: rockchip: dts: rk3399: Add board -u-boot.dtsi filesJagan Teki2019-05-0810-5/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Devicetree files in RK3399 platform is synced from Linux, like other platforms does. Apart from these u-boot in rk3399 would also require some u-boot specific node like dmc. dmc node has big chunk of DDR timing parameters which are specific to specific board, and maintained with rk3399-sdram*.dtsi. So, create board specific -u-boot.dtsi files and move these sdram dtsi files accordingly. This would help of maintain u-boot specific changes separately without touching Linux dts(i) files which indeed easy for syncing from Linux between releases. These board specific -u-boot.dtsi can be extendible to add more u-boot specific nodes or properties in future. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | dts: Makefile: Build rockchip dtbs based on SoC typesJagan Teki2019-05-081-9/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Sometimes u-boot specific dtsi files are included automatically which would build for entire rockchip SoC, even-though the respective dtsi should used it for specific family of rockchip SoC. - Sometimes u-boot specific dts nodes or properties can use config macros from respective rockchip family include/configs files, example CONFIG_SPL_PAD_TO. So, it's better to compile the dtbs based on the respective rockchip family types rather than rockchip itself to avoid compilation issues. This patch organize the existing dtb's based on the rockchip family types. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: chromebook_minnie: Enable soundSimon Glass2019-05-081-0/+12
| | | | | | | | | | | | | | | | | | | | | Enable sound for this board, which has the same codec as jerry. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: rk3399: add tpl supportKever Yang2019-05-083-1/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | Rockchip platform suppose to use TPL(run in SRAM) as dram init and SPL(run in DDR SDRAM) as pre-loader, so that the SPL would not be limited by SRAM size. This patch add rk3399-board-tpl.c and its common configs. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: add u-boot-tpl-v8.ldsKever Yang2019-05-081-0/+94
| | | | | | | | | | | | | | | | | | | | | | | | We don't have both sram and sdram in TPL, so update from: arch/arm/cpu/armv8/u-boot-spl.lds Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | rockchip: px5: add timer0 dts node as tick timerKever Yang2019-05-081-0/+7
| | | | | | | | | | | | | | | | | | Let's use rockchip timer before stimer patches can be merged. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: rk3368: remove uart iomux init in SPLKever Yang2019-05-081-15/+0
| | | | | | | | | | | | | | | | | | | | | The iomux should have been set in board_debug_uart_init(), do not set in board_init_f(), remove it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: boot0: update CONFIG_ROCKCHIP_SPL_RESERVE_IRAM for SPL onlyKever Yang2019-05-081-1/+2
| | | | | | | | | | | | | | | | | | | | | The CONFIG_ROCKCHIP_SPL_RESERVE_IRAM is for SPL only, add condition to limit it not affect TPL. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: px5 update dts for spl/tplKever Yang2019-05-081-0/+29
| | | | | | | | | | | | | | | | | | | | | TPL need dmc to init ddr sdram, and emmc, boot-order. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
| * | rockchip: rk3368: support UART2/4 in board_debug_uart_init()Kever Yang2019-05-081-0/+40
| | | | | | | | | | | | | | | | | | | | | evb-rk3368 is using UART2 and PX5 evb is using UART4 Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
| * | rockchip: rk322x: dts: enable uart2 for SPL/TPLKever Yang2019-05-081-0/+1
| | | | | | | | | | | | | | | | | | | | | When we use DM_SERIAL for serial driver, we need enable the dts node for the debug console. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | sysreset: enable driver support in SPL/TPLKever Yang2019-05-081-0/+1
| | | | | | | | | | | | | | | | | | SPL/TPL also need use sysreset for some feature like panic callback. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: rk322x: add tpl supportKever Yang2019-05-085-30/+110
| | | | | | | | | | | | | | | | | | | | | Move original spl to tpl, and add spl to load next stage firmware, adapt all the address and option for them. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | arm: add a separate stack for TPLKever Yang2019-05-081-1/+3
| | | | | | | | | | | | | | | | | | | | | TPL stack may different from SPL and sys stack, add support for separate one when the board defines it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | arm: add option for TPL support in arm 32bitKever Yang2019-05-081-0/+29
| | | | | | | | | | | | | | | | | | | | | Some options like TPL_SYS_THUMB_BUILD, TPL_USE_ARCH_MEMCPY and TPL_USE_ARCH_MEMCPY are needed for TPL build in 32bit arm. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | arm: remove ARCH_ROCKCHIP macro in common codeKever Yang2019-05-082-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is fix to: e2a12f590d rockchip: use 'arch-rockchip' as header file path The V2 of origin patch set has fix this, but we merge V1 by mistake, so lets correct it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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