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* ti816x: Import dts files from Linux Kernel v4.11Tom Rini2017-06-054-0/+944
| | | | | | | This brings in the required dts/dtsi files for the TI8168-EVM from the Linux Kernel v4.11 release. Signed-off-by: Tom Rini <trini@konsulko.com>
* ti816x: Rework DDR initialization sequenceTom Rini2017-06-058-96/+218
| | | | | | | | | | | | | | | | | | The ti816x/am389x SoC is the first generation in what U-Boot calls the "am33xx" family. In the first generation of this family the DDR initialization sequence is quite different from all of the subsequent generations. Whereas with ti814x (second generation) we can easily work the minor differenced between that and am33xx (third generation), our attempts to do this for ti816x weren't sufficient. Rather than add a large amount of #ifdef logic to make this different sequence work we add a new file, ti816x_emif4.c to handle the various required undocumented register writes and sequence and leverage what we can from arch/arm/mach-omap2/am33xx/ddr.c still. As DDR2 has similar problems today but I am unable to test it, we drop the DDR2 defines from the code rather than imply that it works by leaving it. We also remove a bunch of other untested code about changing the speed the DDR runs at. Signed-off-by: Tom Rini <trini@konsulko.com>
* armv7: Mark the default lowlevel_init function as weakTom Rini2017-06-052-3/+9
| | | | | | | | | | Rather than have a long and if check in the Makefile, mark the default lowlevel_init function as weak (as we do on armv8) so that SoCs can override it if needed, and it will still be discarded if unused. Provide a weak s_init as well to allow for this to link and be discarded. Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-06-0310-13/+109
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| * armv8: layerscape: Enabling loading PPA during SPL stageYork Sun2017-06-013-1/+54
| | | | | | | | | | | | | | | | Loading PPA in SPL puts the rest of U-Boot (including RAM version loaded later) in EL2 with MMU and cache enabled. Once PPA is loaded, PSCI is available. Signed-off-by: York Sun <york.sun@nxp.com>
| * armv8: layerscape: Make U-Boot EL2 safeYork Sun2017-06-016-5/+48
| | | | | | | | | | | | | | | | | | When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com>
| * armv8: ls2080aqds: Add support for SD bootSantan Kumar2017-06-012-6/+6
| | | | | | | | | | | | | | Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls2080a: Reorganise NAND_BOOT code in config flagSantan Kumar2017-06-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add CONFIG_NAND_BOOT config flag to organise NAND_BOOT specific code in config flag like -nand-boot specfic errata errata_rcw_src() -CONFIG_SYS_NAND_U_BOOT_DST,etc Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge git://git.denx.de/u-boot-sunxiTom Rini2017-06-0312-603/+731
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| * | sun50i: h5: Add initial Orangepi Prime supportJagan Teki2017-06-022-1/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Orangepi Prime is an open-source single-board computer using the Allwinner h5 SOC. H5 Orangepi Prime has - Quad-core Cortex-A53 - 2GB DDR3 - Debug TTL UART - 1000M/100M Ethernet RJ45 - Three USB 2.0 - HDMI - Audio and MIC - Wifi + BT - IR receiver - HDMI - Wifi + BT Boot from MMC: ------------- U-Boot SPL 2017.05-00662-ga3f4c05-dirty (May 25 2017 - 13:30:14) DRAM: 2048 MiB Trying to boot from MMC1 NOTICE: BL3-1: Running on H5 (1718) in SRAM A2 (@0x44000) NOTICE: Configuring SPC Controller NOTICE: BL3-1: v1.0(debug):aa75c8d NOTICE: BL3-1: Built : 18:28:27, May 24 2017 INFO: BL3-1: Initializing runtime services INFO: BL3-1: Preparing for EL3 exit to normal world INFO: BL3-1: Next image address: 0x4a000000, SPSR: 0x3c9 U-Boot 2017.05-00662-ga3f4c05-dirty (May 25 2017 - 13:30:14 +0000) Allwinner Technology CPU: Allwinner H5 (SUN50I) Model: OrangePi Prime DRAM: 2 GiB MMC: SUNXI SD/MMC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: phy interface7 eth0: ethernet@1c30000 starting USB... USB0: USB EHCI 1.00 USB1: USB OHCI 1.0 scanning bus 0 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found Hit any key to stop autoboot: 0 Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | arm64: dts: sun50i: h5: orangepi-pc2: Use GPIO flag binding macroJagan Teki2017-06-011-1/+3
| | | | | | | | | | | | | | | | | | | | | Instead of defining numerical value on GPIO flag better to use existing binding macro. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | arm64: dts: sun50i: Add sun50i-h5.dtsiJagan Teki2017-06-012-33/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner H5 SoC is pin-compatible to the H3 SoC, but uses Cortex-A53 cores instead. So move the shared cpu based and peripherals nodes into sun50i-h5.dtsi so, that it can shared among the sun50i-h5 board dts files. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sun50i: a64: Add initial Banana Pi M64 supportJagan Teki2017-06-012-0/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BPI-M64 is a 64-bit quad-core mini single board computer using the Allwinner A64 SOC. BPI-M64 features - 1.2 Ghz Quad-Core ARM Cortex A53 - 2GB DDR3 SDRAM with 733MHz - MicroSD/eMMC(8GB) - 10/100/1000Mbps ethernet (Realtek RTL8211E/D) - Wifi + BT - IR receiver - Audio In/Out - Video In/Out - 5V 2A DC power-supply For dts file, Sync with Linux commit 4879b7ae("Merge tag 'dmaengine-4.12-rc1'"). Boot from MMC: ------------- U-Boot SPL 2017.05-00667-g85dd258-dirty (May 29 2017 - 13:07:31) DRAM: 2048 MiB Trying to boot from MMC1 NOTICE: BL3-1: Running on A64/H64 (1689) in SRAM A2 (@0x44000) NOTICE: Configuring SPC Controller NOTICE: BL3-1: v1.0(debug):aa75c8d NOTICE: BL3-1: Built : 18:28:27, May 24 2017 NOTICE: Configuring AXP PMIC NOTICE: PMIC: setup successful INFO: BL3-1: Initializing runtime services INFO: BL3-1: Preparing for EL3 exit to normal world INFO: BL3-1: Next image address: 0x4a000000, SPSR: 0x3c9 U-Boot 2017.05-00667-g85dd258-dirty (May 29 2017 - 13:07:31 +0000) Allwinner Technology CPU: Allwinner A64 (SUN50I) Model: BananaPi-M64 DRAM: 2 GiB MMC: SUNXI SD/MMC: 0, SUNXI SD/MMC: 1 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: No ethernet found. starting USB... No controllers found Hit any key to stop autoboot: 0 Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | sunxi: A64/Pine64: update device tree from LinuxAndre Przywara2017-06-015-569/+298
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Linux device tree for the Allwinner A64 SoC has changed a lot since the U-Boot version was merged. Let's replace the current DT with a exact copy of the Linux one as of: commit c6778ff813d2ca3e3c8733c87dc8b6831a64578b Merge: 0ff4c01 3c0e3abd Author: Linus Torvalds <torvalds@linux-foundation.org> Date: Tue May 9 10:07:33 2017 -0700 This is the DT used in Linux 4.12-rc1. Since U-Boot has an Ethernet driver (while Linux does not yet), we provide the required DT nodes for it in an ...-u-boot.dtsi file, to both mark them as U-Boot specific and to allow easier upgrading once Linux gets the driver and its own binding later. Compared to the existing Ethernet DT nodes we just slightly tweak the clock and reset nodes in there to match the new bindings used by Linux for those. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sunxi: Update NanoPi Neo to use dtsiMylene JOSSERAND2017-05-301-78/+1
| | | | | | | | | | | | | | | | | | | | | Update the NanoPi Neo device tree file to use the NanoPi dtsi. Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sunxi: Add support for NanoPi M1Mylene JOSSERAND2017-05-303-0/+202
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NanoPi M1 is a board based on Allwinner H3 CPU. This commit adds the support for this platform with: - an include device tree which enables UART, LEDs, GPIO key switch, 1 USB host ports and the SD-card as a dtsi file. - a device tree specific to this board that enables the 2 additional USB ports - a defconfig file for minimal support - a section in MAINTAINERS (add myself) Synchronized with the kernel device tree, from commits: sun8i-nanopi.dtsi: 85d2913614d9ab899d23b7ab7d22d23cf45bd1de sun8i-h3-nanopi-m1.dts: 10efbf5f16336b7540ad6a16aa1cb0b26bab033b Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | | Kconfig: Migrate FS_FAT / FAT_WRITETom Rini2017-06-031-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | Now that these symbols are in Kconfig, migrate all users. Use imply on a number of platforms that default to having this enabled. As part of this we must migrate some straglers for CMD_FAT and DOS_PARTITION. Signed-off-by: Tom Rini <trini@konsulko.com>
* | | fdt: Rename a few functions in fdt_supportSimon Glass2017-06-012-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These two functions have an of_ prefix which conflicts with naming used in of_addr. Rename them: fdt_read_number fdt_support_bus_default_count_cells Signed-off-by: Simon Glass <sjg@chromium.org>
* | | dm: core: Replace of_offset with accessor (part 2)Simon Glass2017-06-012-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | dm: Fix up inclusion of common.hSimon Glass2017-06-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is good practice to include common.h as the first header. This ensures that required features like the DECLARE_GLOBAL_DATA_PTR macro, configuration options and common types are available. Fix up some files which currently don't do this. This is necessary because driver model will soon start using global data and configuration in the dm/read.h header file, included via dm.h. The gd->fdt_blob value will be used to access the device tree and CONFIG options will be used to determine whether to support inline functions in the header file. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | dm: Rename dev_addr..() functionsSimon Glass2017-06-013-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | dm: Use dm.h header when driver mode is usedSimon Glass2017-06-012-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | This header includes things that are needed to make driver build. Adjust existing users to include that always, even if other dm/ includes are present Signed-off-by: Simon Glass <sjg@chromium.org>
* | | Merge git://www.denx.de/git/u-boot-marvellTom Rini2017-05-314-64/+91
|\ \ \ | | | | | | | | | | | | Mostly including the Armada 37xx pinctrl / gpio driver.
| * | | arm64: mvebu: Replace board specific with generic memory bank decodingStefan Roese2017-05-311-62/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dram_init and dram_init_banksize functions were using a board specific implementation for decoding the memory banks from the fdt. This change makes the dram_init* functions use a generic implementation of decoding and populating memory bank and size data. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nathan Rossi <nathan@nathanrossi.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | arm64: mvebu: armada-7040-db: Enable 10GB port 0 / SFI (KR)Stefan Roese2017-05-311-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the mvpp2 port 0 usage on the Armada 7k DB by setting the correct PHY type (KR / SFI) for the COMPHY driver and enabling the ethernet0 device node in the dts. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com>
| * | | arm64: mvebu: armada37xx: add pinctrl definitionGregory CLEMENT2017-05-312-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Start to populate the device tree of the Armada 37xx with the pincontrol configuration used on the board providing a dts. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Konstantin Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com>
| * | | arm64: mvebu: Add pinctrl nodes for Armada 3700Gregory CLEMENT2017-05-311-0/+42
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the nodes for the two pin controller present in the Armada 37xx SoCs. Initially the node was named gpio1 using the same name that for the register range in the datasheet. However renaming it pinctr_nb (nb for North Bridge) makes more sens. Minor changes for U-Boot because of the slightly different dts version done by Stefan Roese. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Konstantin Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com>
* | | Kconfig: Finish migration of hashing commandsDaniel Thompson2017-05-313-0/+8
|/ / | | | | | | | | | | | | | | | | | | | | | | Currently these (board agnostic) commands cannot be selected using menuconfig and friends. Fix this the obvious way. As part of this, don't muddle the meaning of CONFIG_HASH_VERIFY to mean both 'hash -v' and "we have a hashing command" as this makes the Kconfig logic odd. Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> [trini: Re-apply, add imply for a few cases, run moveconfig.py, also migrate CRC32_VERIFY] Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-05-2611-7/+166
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| * | armv8: ls2080ardb, ls2080aqds: Adjust memory map for NOR-bootSantan Kumar2017-05-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adjusts memory map for images on LS2080ARDB and LS2080AQDS NOR flash as below Image Flash Offset RCW+PBI 0x00000000 Boot firmware (U-Boot) 0x00100000 Boot firmware Environment 0x00300000 PPA firmware 0x00400000 PHY firmware 0x00980000 DPAA2 MC 0x00A00000 DPAA2 DPL 0x00D00000 DPAA2 DPC 0x00E00000 Kernel.itb 0x01000000 Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: layerscape: Adjust memory mapping for Flash/SD card on LS1043AAlison Wang2017-05-231-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to adjust the memory mapping for FLash/SD card on LS1043AQDS and LS1043ARDB, such as PPA firmware load address, FMAN firmware load address, QE firmware load address, U-Boot start address on serial flash and environment address. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080ardb: Add LS2081ARDB board supportPriyanka Jain2017-05-234-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS2081ARDB board is similar to LS2080ARDB board with few differences It hosts LS2081A SoC Default boot source is QSPI-boot It does not have IFC interface RTC and QSPI flash device are different It provides QIXIS access via I2C Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC supportPriyanka Jain2017-05-234-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080ardb: Add QSPI-boot supportPriyanka Jain2017-05-233-1/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QSPI-boot is supported on LS2088ARDB RevF board with LS2088A SoC. LS2088ARDB RevF Board has limitation that QIXIS can not be accessed. CONFIG_FSL_QIXIS is not enabled. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | board: freescale: ls2080ardb: Enable SD interface for RevF boardPriyanka Jain2017-05-231-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS2080ARDB/LS2088ARDB RevF board has smart voltage translator which needs to be programmed to enable high speed SD interface by setting GPIO4_10 output to zero. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2017-05-2313-761/+7337
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| * | ARM: rmobile: Move address of IICDVFS(I2C) to rcar-gen3-base.hNobuhiro Iwamatsu2017-05-222-3/+3
| | | | | | | | | | | | | | | | | | | | | The IICDVFS(I2C) set in r8a7796.h is common in rcar-gen3. This moves CONFIG_SYS_I2C_SH_BASE0 in rcar-gen3-base.h. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | ARM: rmobile: Allow R8A7796 Salvator-X configurationMarek Vasut2017-05-221-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The Salvator-X can have both H3 and M3 CPU on it, drop the select R8A7795 to allow both configurations. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | ARM: rmobile: Add R8A7796 supportMarek Vasut2017-05-225-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | Add Kconfig entry for the R8A7796 RCar M3 SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | ARM: rmobile: Handle R8A7796 r1.1 in the PRR codeMarek Vasut2017-05-221-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | The R8A7796 r1.1 reports itself as r2.0 , add quirk into the PRR code to fix this report. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | ARM: rmobile: Add R8A7796 into the CPU tableMarek Vasut2017-05-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add entry for the R8A7796 RCar M3 SoC into the CPU info table. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | ARM: rmobile: Add R8A7795 into the CPU tableMarek Vasut2017-05-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add entry for the R8A7795 RCar H3 SoC into the CPU info table. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | ARM: rmobile: Make the Gen3 SoC configurableMarek Vasut2017-05-221-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Allow selecting the Gen3 SoC in preparation for RCar M3 . No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | ARM: rmobile: Zap RCAR_GEN3_EXTRAM_BOOTMarek Vasut2017-05-221-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | This Kconfig option is not used on any board, so drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | ARM: rmobile: Import R8A7796 PFC and GPIO tablesMarek Vasut2017-05-223-0/+6340
| | | | | | | | | | | | | | | | | | | | | | | | | | | Import the R8A7796 PFC and GPIO tables from the latest 3.5.3 release from Renesas . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | ARM: rmobile: Update R8A7795 PFC and GPIO tablesMarek Vasut2017-05-222-750/+897
| | | | | | | | | | | | | | | | | | | | | | | | | | | Sync the PFC and GPIO tables with the latest 3.5.3 release from Renesas . This adds ES2.0 support. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | | Merge git://git.denx.de/u-boot-sunxiTom Rini2017-05-223-4/+23
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | trini: Make Kconfig SPL_xxx entires only show if SPL, so that we don't get Kconfig errors on platforms without SPL, ie sandbox (without SPL). Signed-off-by: Tom Rini <trini@konsulko.com>
| * | | sunxi: Store the device tree name in the SPL headerSiarhei Siamashka2017-05-171-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the mksunxiboot tool to optionally add the default device tree name string to the SPL header. This information can be used by the firmware upgrade tools to protect users from harming themselves by trying to upgrade to an incompatible bootloader. The primary use case here is a non-removable bootable media (such as NAND, eMMC or SPI flash), which already may have a properly working, but a little bit outdated bootloader installed. For example, the user may download or build a new U-Boot image for "Cubieboard", and then attemept to install it on a "Cubieboard2" hardware by mistake as a replacement for the already existing bootloader. If this happens, the flash programming tool can identify this problem and warn the user. The size of the SPL header is also increased from 64 bytes to 96 bytes to provide enough space for the device tree name string. [Andre: split patch to remove OF_LIST hash feature] Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | sunxi: enable automatic FIT build for 64-bit SoCsAndre Przywara2017-05-171-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner SoCs with 64-bit cores use an ARM Trusted Firmware binary, which needs to be loaded alongside U-Boot proper. Set the respective Kconfig options to let them select this feature and also automatically build the FIT image. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> [Rename Kconfig path to arch/arm/mach-sunxi/Kconfig] Signed-off-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | | armv8: fsl: move ccn504 code into FSL MakefileAndre Przywara2017-05-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The generic ARMv8 assembly code contains routines for setting up a CCN interconnect, though the Freescale SoCs are the only user. Link this code only for Freescale targets, this saves some precious bytes in the chronically tight SPL. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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