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* mips: octeon: Add bootoctlinux commandAaron Williams2020-10-073-0/+716
* mips: octeon: Add bootmem supportAaron Williams2020-10-073-0/+1994
* mips: octeon: Add coremask supportAaron Williams2020-10-073-0/+1119
* mips: octeon: Add header cvmx-bootinfo.hAaron Williams2020-10-071-0/+350
* mips: octeon: Add header cvmx-fuse.hAaron Williams2020-10-071-0/+71
* mips: octeon: Add header octeon-feature.hAaron Williams2020-10-071-0/+442
* mips: octeon: Add header cvmx-regs.hAaron Williams2020-10-071-0/+144
* mips: octeon: lowlevel_init.S: Add NMI handling code for SMP Linux bootingStefan Roese2020-10-071-0/+76
* mips: octeon: octeon-model.h: Enable inclusion from assembler filesStefan Roese2020-10-071-0/+4
* mips: octeon: Add USB DT nodesStefan Roese2020-10-072-0/+84
* mips: octeon: cache.c: Flush all pending writes in flush_dcache_range()Stefan Roese2020-10-071-6/+6
* mips: octeon: Add mangle-port.hStefan Roese2020-10-071-0/+56
* mips: octeon: cpu.c: Add table for selective swappingStefan Roese2020-10-071-0/+21
* mips: octeon: dram.c: Add RAM driver supportStefan Roese2020-10-071-8/+64
* mips: octeon: Add octeon_ddr.h headerAaron Williams2020-10-071-0/+982
* mips: octeon Add cvmx/cvmx-lmcx-defs.h headerAaron Williams2020-10-071-0/+4574
* mips: octeon: Add octeon-model.h headerAaron Williams2020-10-071-0/+313
* mips: octeon: dts: mrvl, cn73xx.dtsi: Add memory controller DT nodeStefan Roese2020-10-071-0/+17
* Merge branch 'next'Tom Rini2020-10-052-2/+2
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| * global: Move from bi_memstart/memsize -> gd->ram_base/ram_sizeStefan Roese2020-08-262-2/+2
* | mips: vocore2: fix various issuesMauro Condarelli2020-09-231-1/+1
* | mips: dts: Fix PIC32MZDA GPIO register definitionsJohn Robertson2020-09-231-2/+2
* | mips: dts: Fix PIC32MZDA GPIO register definitionsJohn Robertson2020-09-231-23/+22
* | mips: dts: Fix device tree warnings for PIC32MZDAJohn Robertson2020-09-231-0/+11
* | mips: pic32mzdask: disable SDHCI SDCD signal workaroundJohn Robertson2020-09-231-0/+1
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* Merge tag 'mips-pull-2020-08-03' of https://gitlab.denx.de/u-boot/custodians/...Tom Rini2020-08-043-3/+90
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| * mips: octeon: Update Octeon KconfigStefan Roese2020-08-031-2/+4
| * mips: octeon: mrvl, octeon-ebb7304.dts: Add SPI flash DT nodeStefan Roese2020-08-031-0/+9
| * mips: octeon: mrvl,cn73xx.dtsi: Add SPI DT nodeStefan Roese2020-08-031-0/+10
| * mips: octeon: dts: Add Octeon clock driver DT nodesStefan Roese2020-08-032-1/+11
| * mips: octeon: dts: Add I2C DT nodesStefan Roese2020-08-032-0/+30
| * mips: octeon: mrvl,cn73xx.dtsi: Add GPIO DT nodesStefan Roese2020-08-031-0/+26
* | mscc: Drop dm.h header fileSimon Glass2020-08-035-15/+0
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* mips: octeon: Add minimal Octeon 3 EBB7304 EVK supportStefan Roese2020-07-183-0/+111
* mips: octeon: use mips_mach_early_init() to copy to L2 cacheStefan Roese2020-07-182-0/+51
* mips: octeon: dts: Add Octeon 3 cn73xx base dtsi fileStefan Roese2020-07-181-0/+64
* mips: octeon: Initial minimal support for the Marvell Octeon SoCAaron Williams2020-07-1812-0/+312
* mips: Add CONFIG_MIPS_MACH_EARLY_INIT for very early mach init codeStefan Roese2020-07-182-0/+14
* mips: sync asm/mipsregs.h with Linux 5.7Daniel Schwierzeck2020-07-185-196/+1103
* mips: sync asm/addrspace.h with Linux 5.7Daniel Schwierzeck2020-07-181-12/+2
* mips: sync asm/asm.h with Linux 5.7Daniel Schwierzeck2020-07-181-120/+10
* mips: remove deprecated UNCACHED_SDRAM() macroDaniel Schwierzeck2020-07-182-15/+2
* mips: add config options for generic cache setup codeDaniel Schwierzeck2020-07-182-1/+29
* mips: refactor disabling of cachesDaniel Schwierzeck2020-07-182-5/+10
* mips: add KSEG1 wrapper for change_k0_ccaDaniel Schwierzeck2020-07-181-14/+18
* mips: start.S: remove dead codeDaniel Schwierzeck2020-07-181-9/+0
* mips: cache: Make invalidate_dcache_range() weak to enable overwriteStefan Roese2020-07-181-1/+1
* mips: cache: Make flush_cache() weak to enable overwriteStefan Roese2020-07-181-1/+1
* mips: cache: Allow using CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CMStefan Roese2020-07-182-2/+12
* mips: reloc: Change R_MIPS_NONE to catch pre-reloc BSS usageStefan Roese2020-07-182-4/+5
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