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* riscv: sifive: fu540: add SPL configurationPragnesh Patel2020-06-042-0/+27
* riscv: cpu: fu540: Add support for cpu fu540Pragnesh Patel2020-06-044-0/+82
* riscv: Add _image_binary_end for SPLPragnesh Patel2020-06-041-0/+1
* common: Drop linux/bitops.h from common headerWIP/2020-05-18-reduce-size-of-common.hSimon Glass2020-05-181-0/+1
* common: Drop init.h from common headerSimon Glass2020-05-181-0/+1
* common: Drop net.h from common headerSimon Glass2020-05-182-0/+2
* riscv: Provide a mechanism to fix DT for reserved memoryAtish Patra2020-04-231-0/+1
* riscv: Introduce SPL_SMP Kconfig option for U-Boot SPLBin Meng2020-04-231-7/+7
* riscv: Merge unnecessary SMP ifdefs in start.SBin Meng2020-04-231-4/+0
* riscv: qemu: Remove the simple-bus driver for the SoC nodeBin Meng2020-04-231-14/+0
* riscv: ax25: cache: Remove SPL_RISCV_MMODE config checkPragnesh Patel2020-04-231-8/+8
* riscv: Remove unnecessary instructionSean Anderson2020-02-101-3/+2
* riscv: Add option to print registers on exceptionSean Anderson2020-02-101-1/+2
* riscv: Fix breakage caused by linker relaxationSean Anderson2020-02-101-1/+0
* common: Move relocate_code() to init.hSimon Glass2020-01-171-1/+1
* riscv: add option to wait for ack from secondary harts in smp functionsLukas Auer2019-12-101-0/+2
* riscv: Fix clear bss loop in the start-up codeRick Chen2019-12-103-4/+4
* riscv: ax25: cache: Add SPL_RISCV_MMODE for SPLRick Chen2019-12-101-14/+46
* riscv: ax25: add SPL supportRick Chen2019-12-101-1/+3
* common: Move board_get_usable_ram_top() out of common.hSimon Glass2019-12-021-0/+1
* common: Move enable/disable_interrupts out of common.hSimon Glass2019-12-021-0/+1
* common: Move ARM cache operations out of common.hSimon Glass2019-12-021-0/+1
* common: Move some cache and MMU functions out of common.hSimon Glass2019-12-022-0/+2
* riscv: cache: use CCTL to flush d-cacheRick Chen2019-09-031-9/+13
* riscv: cache: Flush L2 cache before jump to linuxRick Chen2019-09-031-0/+17
* riscv: ax25: add imply v5l2 cache controllerRick Chen2019-09-031-0/+1
* riscv: update fix_rela_dynMarcus Comstedt2019-09-031-5/+5
* riscv: support SPL stack and global data relocationLukas Auer2019-08-261-1/+34
* riscv: add SPL supportLukas Auer2019-08-263-1/+107
* riscv: add run mode configuration for SPLLukas Auer2019-08-264-10/+10
* riscv: Access CSRs using CSR numbersBin Meng2019-08-152-7/+5
* CONFIG_SPL_SYS_[DI]CACHE_OFF: addTrevor Woerner2019-05-181-4/+4
* riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is ena...Rick Chen2019-05-092-0/+4
* riscv: Introduce CONFIG_XIP to support booting from flashRick Chen2019-05-092-0/+8
* riscv: ax25: Andes specific cache shall only support in M-modeRick Chen2019-04-081-0/+1
* riscv: ax25: Add platform-specific Kconfig optionsRick Chen2019-04-081-0/+6
* riscv: hang if relocation of secondary harts failsLukas Auer2019-04-081-1/+12
* riscv: do not rely on hart ID passed by previous boot stageLukas Auer2019-04-081-0/+4
* riscv: add support for multi-hart systemsLukas Auer2019-04-082-2/+141
* riscv: save hart ID in register tp instead of s0Lukas Auer2019-04-081-2/+2
* riscv: delay initialization of caches and debug UARTLukas Auer2019-04-081-8/+8
* riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systemsAnup Patel2019-02-271-0/+20
* riscv: Rename cpu/qemu to cpu/genericAnup Patel2019-02-274-1/+1
* riscv: move the AX25-specific implementation of flush_dcache_allLukas Auer2019-01-151-0/+22
* riscv: Save boot hart id to the global dataBin Meng2018-12-181-0/+4
* riscv: Return to previous privilege level after trap handlingBin Meng2018-12-181-8/+0
* riscv: Fix context restore before returning from trap handlerBin Meng2018-12-181-1/+1
* riscv: Move trap handler codes to mtrap.SBin Meng2018-12-183-90/+112
* riscv: Do some basic architecture level cpu initializationBin Meng2018-12-181-1/+26
* riscv: Update supports_extension() to use desc from cpu driverBin Meng2018-12-181-0/+26
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