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* Convert CONFIG_SYS_BOOT_RAMDISK_HIGH to KconfigTom Rini2022-07-071-2/+0
| | | | | | | This converts the following to Kconfig: CONFIG_SYS_BOOT_RAMDISK_HIGH Signed-off-by: Tom Rini <trini@konsulko.com>
* linker_lists: Rename sections to remove . prefixAndrew Scull2022-06-232-4/+4
| | | | | | | | | | | | | | | | Rename the sections used to implement linker lists so they begin with '__u_boot_list' rather than '.u_boot_list'. The double underscore at the start is still distinct from the single underscore used by the symbol names. Having a '.' in the section names conflicts with clang's ASAN instrumentation which tries to add redzones between the linker list elements, causing expected accesses to fail. However, clang doesn't try to add redzones to user sections, which are names with all alphanumeric and underscore characters. Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Migrate CUSTOM_SYS_INIT_SP_ADDR to Kconfig using system-constants.hTom Rini2022-06-061-1/+2
| | | | | | | | | | | | | | - Make all users of CUSTOM_SYS_INIT_SP_ADDR reference SYS_INIT_SP_ADDR - Introduce HAS_CUSTOM_SYS_INIT_SP_ADDR to allow for setting the stack pointer directly, otherwise we use the common calculation. - On some platforms that were using the standard calculation but did not set CONFIG_SYS_INIT_RAM_SIZE / CONFIG_SYS_INIT_RAM_ADDR, set them. - On a small number of platforms that were not subtracting GENERATED_GBL_DATA_SIZE do so now via the standard calculation. - CONFIG_SYS_INIT_SP_OFFSET is now widely unused, so remove it from most board config header files. Signed-off-by: Tom Rini <trini@konsulko.com>
* riscv: Clean up asm/io.hLeo Yu-Chi Liang2022-05-261-116/+0
| | | | | | | | | | | | | | | | Clean up asm/io.h by - removing commented code - removing outdated comments - removing unused definitions (for mem_isa, mem_pci) This massively improves the readability of the file. Suggested by commits: 7ab2e47d27c9 ("arm: Clean up asm/io.h") 909d0399a519 ("ARM: asm/io.h: kill off confusing #ifdef __mem_pci block") Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: remove CONFIG_ARCH_MAP_SYSMEM from io.hMichal Simek2022-05-261-22/+0
| | | | | | | | | | | Commit ba1ed5b022c6 ("Convert CONFIG_ARCH_MAP_SYSMEM to Kconfig") clearly defined that this option is available for SANDBOX (was also for already removed NDS32). That's why there is no way how this code can be enabled with current Kconfig layout for riscv. Based on this removing this code. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: alloc space exhaustedHeinrich Schuchardt2022-04-061-3/+0
| | | | | | | | | | | | | | | | | | When trying to run qemu-riscv64_smode_defconfig with 32 harts booting fails. The debug UART shows a message alloc space exhausted 32 is the current maximum number of harts for machine virt in QEMU 7.0. Raise the default for SYS_MALLOC_F_LEN to 16 KiB. Move the setting to /Kconfig where we define SYS_MALLOC_F_LEN for other architectures too. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
* riscv: provide missing base extension functionsHeinrich Schuchardt2022-04-062-0/+68
| | | | | | | | | | | Provide library functions to read: * machine vendor ID * machine architecture ID * machine implementation ID Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
* cmd: sbi: add Performance Monitoring Unit ExtensionHeinrich Schuchardt2022-04-061-0/+1
| | | | | | | | | | Version 1.0-rc3 of the RISC-V Supervisor Binary Interface Specification has added the Performance Monitoring Unit Extension. The sbi command should be able to detect it. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge tag 'v2022.04-rc5' into nextTom Rini2022-03-282-75/+105
|\ | | | | | | Prepare v2022.04-rc5
| * k210: dts: align plic node with LinuxNiklas Cassel2022-03-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Linux PLIC interrupt-controller driver actually initializes the hart context registers in the PLIC driver exactly in the same order as specified in the interrupts-extended device tree property. See the device tree binding [1]. The ordering of the interrupts is therefore essential in order to configure the PLIC correctly. Fix the order so that we will have sane IRQ behavior when booting Linux with the u-boot device tree. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
| * k210: dts: align fpioa node with LinuxDamien Le Moal2022-03-151-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux kernel fpioa pinctrl driver expects the sysctl phandle and the power bit offset of the fpioa device to be specified as a single property "canaan,k210-sysctl-power". Replace the "canaan,k210-sysctl" and "canaan,k210-power-offset" properties with "canaan,k210-sysctl-power" to satisfy the Linux kernel requirements. This new property is parsed using the existing function dev_read_phandle_with_args(). Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
| * k210: dts: add missing power bus clocksDamien Le Moal2022-03-151-23/+53
| | | | | | | | | | | | | | | | | | | | Linux drivers for many of the K210 peripherals depend on the power bus clock to be specified. Add the missing clocks and their names to avoid problems when booting Linux using u-boot DT. Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
| * k210: use the board vendor name rather than the marketing nameDamien Le Moal2022-03-152-50/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | "kendryte" is the marketing name for the K210 RISC-V SoC produced by Canaan Inc. Rather than "kendryte,k210", use the usual "canaan,k210" vendor,SoC compatibility string format in the device tree files and use the SoC name for file names. With these changes, the device tree files are more in sync with the Linux kernel DTS and drivers, making uboot device tree usable by the kernel. Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* | event: Convert arch_cpu_init_dm() to use eventsSimon Glass2022-03-103-2/+11
|/ | | | | | | Instead of a special function, send an event after driver model is inited and adjust the boards which use this function. Signed-off-by: Simon Glass <sjg@chromium.org>
* dts: automatically build necessary .dtb filesRasmus Villemoes2022-02-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | When building for a custom board, it is quite common to maintain a private branch which include some defconfig and .dts files. But to hook up those .dts files requires modifying a file "belonging" to upstream U-Boot, the arch/*/dts/Makefile. Forward-porting that branch to a newer upstream then often results in a conflict which, while it is trivial to resolve by hand, makes it harder to have a CI do "try to build our board against latest upstream". The .config usually includes information on precisely what .dtb(s) are needed, so to avoid having to modify the Makefile, simply add the files in (SPL_)OF_LIST to dtb-y. A technicality is that (SPL_)OF_LIST is not always defined, so rework the Kconfig symbols so that (SPL_)OF_LIST is always defined (when (SPL_)OF_CONTROL), but only prompted for in the cases which used to be their "depends on". nios2 and microblaze already have something like this in their dts/Makefile, and the rationale in commit 41f59f68539 is similar to the above. So this simply generalizes existing practice. Followup patches could remove the logic in those two makefiles, just as there's potential for moving some common boilerplate from all the arch/*/dts/Makefile files to the new scripts/Makefile.dts. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Simon Glass <sjg@chromium.org>
* doc: replace @return by Return:Heinrich Schuchardt2022-01-192-6/+6
| | | | | | | | | | | | Sphinx expects Return: and not @return to indicate a return value. find . -name '*.c' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; find . -name '*.h' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
* efi_loader: fix SectionAlignment, FileAlignmentHeinrich Schuchardt2022-01-153-6/+7
| | | | | | | | | | | | | | | The alignment of sections in the EFI binaries generated by U-Boot is incorrect. According to the PE-COFF specification [1] the minimum value for FileAlignment is 512. If the value of SectionAlignment is less then the page size, it must equal FileAlignment. Let's set both values to 512 for the ARM and RISC-V architectures. [1] https://docs.microsoft.com/en-us/windows/win32/debug/pe-format Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
* riscv: revert Complete efi header for RV32/64Heinrich Schuchardt2022-01-151-10/+0
| | | | | | | | | | | | | | EDK II refuses to load the EFI binaries created by U-Boot. The reason is an incorrect PE-COFF header. The number of data directories does not match NumberOfRvaAndSizes. This leads to a failed consistency check in PeCoffLoaderGetPeHeader(): SizeOfOptionalHeader - HeaderWithoutDataDir) != NumberOfRvaAndSizes * sizeof(DATA_DIRECTORY)) Fixes: 9afaeec6ef8b ("riscv: Complete efi header for RV32/64") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
* riscv: qemu: Split devicetree files for qemu_riscv32/64Simon Glass2021-12-233-1/+15
| | | | | | | | | | | This uses QEMU virt which creates its own devicetree. Copy the existing empty version of this file, so splitting the existing qemu-virt into two, since anyone actually trying to use this will need a different devicetree for 32- and 64-bit machines. Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canaonical.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* riscv: Enable SPI flash env for SiFive Unmatched.Thomas Skibo2021-12-021-0/+13
| | | | | | | | Enable saving environment to SPI flash memory on SiFive Unmatched. Signed-off-by: Thomas Skibo <thomas-git@skibo.net> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* riscv: Support booting SiFive Unmatched from SPI.Thomas Skibo2021-12-021-0/+11
| | | | | | | | Configure SPI flash devices into SPL. Add SPI boot option to spl.c. Document how to format flash for booting. Signed-off-by: Thomas Skibo <thomas-git@skibo.net> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* riscv: dts: Split Microchip device treePadmarao Begari2021-12-022-389/+700
| | | | | | | | | | The device tree split into .dtsi and .dts files, common device node for eMMC/SD, enable I2C1, UART1 for console instead of UART0, enable the DDR 2GB memory and in that 288MB memory is reserved for fabric buffer. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* riscv: add #define in asm/io.h for some device driversWei Fu2021-11-081-0/+4
| | | | | | | | This patch adds memcpy_fromio and memcpy_toio definitions for some device drivers which have these definitions, like cadence_qspi_apb.c Signed-off-by: Wei Fu <wefu@redhat.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: function to retrieve SBI implementation versionHeinrich Schuchardt2021-11-082-0/+20
| | | | | | | | | Provide function sbi_get_impl_version() to retrieve the SBI implementation version. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
* riscv: Avoid io read/write cause wrong resultNick Hu2021-10-201-9/+9
| | | | | | | | | io read/write may cause wrong result because they may read/write data from/to register instead of memory. Add 'volatile' to avoid it. Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: Remove OF_PRIOR_STAGE from RISC-V boardsIlias Apalodimas2021-10-183-11/+3
| | | | | | | | | | | | | | | | | | At some point back in 2018 prior_stage_fdt_address and OF_PRIOR_STAGE got introduced, in order to support a DTB handed over by an earlier stage boo loader. However we have another option in the Kconfig (OF_BOARD) which has identical semantics. On RISC-V some of the boards pick up the DTB from a1 and copy it in their private gd_t. Apart from that they copy it to prior_stage_fdt_address, if the Kconfig option is selected, which is unnecessary. So let's switch the config option for those boards to OF_BOARD and define the required board_fdt_blob_setup() for them. Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* fdtdec: Support reserved-memory flagsThierry Reding2021-10-131-1/+1
| | | | | | | | | | | | | Reserved memory nodes can have additional flags. Support reading and writing these flags to ensure that reserved memory nodes can be properly parsed and emitted. This converts support for the existing "no-map" flag to avoid extending the argument list for fdtdec_add_reserved_memory() to excessive length. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* fdtdec: Support compatible string list for reserved memoryThierry Reding2021-10-131-1/+1
| | | | | | | | | | Reserved memory nodes can have a compatible string list to identify the type of reserved memory that they represent. Support specifying an optional compatible string list when creating these nodes. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* image: Drop IMAGE_ENABLE_OF_LIBFDTSimon Glass2021-10-081-2/+2
| | | | | | | | | Add a host Kconfig for OF_LIBFDT. With this we can use CONFIG_IS_ENABLED(OF_LIBFDT) directly in the tools build, so drop the unnecessary indirection. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* riscv: ae350: enable Coherence Manager for ae350Leo Yu-Chi Liang2021-10-071-0/+42
| | | | | | | | | | If Coherence Manager were not set in the beginning, u-boot-spl would sometimes fail to boot to u-boot proper. Enable CM and I/D cache at the same time in harts_early_init Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
* sysreset: provide SBI based sysreset driverHeinrich Schuchardt2021-10-073-1/+25
| | | | | | | | | Provide sysreset driver using the SBI system reset extension. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Samuel Holland <samuel@sholland.org>
* riscv: add missing SBI extension definitionsHeinrich Schuchardt2021-10-071-2/+37
| | | | | | | | | | | | | | | | | Add the System Reset Extension and the Hart State Management Extension definitions. Add missing RFENCE Extension enum values. The SBI 0.1 extension constants are needed for the sbi command. Remove an #ifdef. Cf. https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: Fix setting no-map in reserved memory nodesSamuel Holland2021-10-071-4/+1
| | | | | | | | | | | | The no-map property is wrongly skipped if a no-map reserved memory node follows one without that property. Fix this by not remembering the absence of a no-map property across loop iterations. Fixes: d4ea649f179a ("riscv: Provide a mechanism to fix DT for reserved memory") Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
* lmb: riscv: Add arch_lmb_reserve()Marek Vasut2021-09-231-0/+13
| | | | | | | | | | | | | | Add arch_lmb_reserve() implemented using arch_lmb_reserve_generic(). It is rather likely this architecture also needs to cover U-Boot with LMB before booting Linux. Reviewed-by: Rick Chen <rick@andestech.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Atish Patra <atish.patra@wdc.com> Cc: Leo <ycliang@andestech.com> Cc: Rick Chen <rick@andestech.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tom Rini <trini@konsulko.com>
* Merge tag 'v2021.10-rc4' into nextTom Rini2021-09-1614-141/+75
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prepare v2021.10-rc4 Signed-off-by: Tom Rini <trini@konsulko.com> # gpg: Signature made Tue 14 Sep 2021 06:58:32 PM EDT # gpg: using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C # gpg: Good signature from "Thomas Rini <trini@konsulko.com>" [ultimate] # Conflicts: # board/Arcturus/ucp1020/spl.c # cmd/mvebu/Kconfig # common/Kconfig.boot # common/image-fit.c # configs/UCP1020_defconfig # configs/sifive_unmatched_defconfig # drivers/pci/Kconfig # include/configs/UCP1020.h # include/configs/sifive-unmatched.h # lib/Makefile # scripts/config_whitelist.txt
| * riscv: lib: modify the indentZong Li2021-09-071-1/+1
| | | | | | | | | | | | | | | | We usually use a space in function declaration, rather than a tab. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
| * board: sifive: use ccache driver instead of helper functionZong Li2021-09-078-140/+4
| | | | | | | | | | | | | | | | Invokes the common cache_init function to initialize ccache. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
| * riscv: lib: implement enable_caches for sifive cacheZong Li2021-09-073-0/+33
| | | | | | | | | | | | | | | | | | | | | | The enable_caches is a generic hook for architecture-implemented, we define this function to enable composable cache of sifive platforms. In sifive_cache, it invokes the generic cache_enable interface of cache uclass to execute the relative implementation in SiFive ccache driver. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
| * common: board_r: support enable_caches for RISC-VZong Li2021-09-071-0/+4
| | | | | | | | | | | | | | | | The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
| * riscv: show code leading to exceptionHeinrich Schuchardt2021-09-071-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To make analyzing exceptions easier output the code that leads to it. We already do the same on the ARM platform. Here is an example: => exception ebreak Unhandled exception: Breakpoint EPC: 000000008ff5d50e RA: 000000008ff5d62c TVAL: 0000000000000000 EPC: 000000008020b50e RA: 000000008020b62c reloc adjusted Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002) To disassemble the code we can use the decodecode script: $ echo 'Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002)' | \ CROSS_COMPILE=riscv64-linux-gnu- scripts/decodecode Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002) All code ======== 0: 2785 addiw a5,a5,1 2: 07a00693 li a3,122 6: fef6dce3 bge a3,a5,0xfffffffffffffffe a: 47a5 li a5,9 c: 00e7d563 bge a5,a4,0x16 10:* 9002 ebreak <-- trapping instruction ... Code starting with the faulting instruction =========================================== 0: 9002 ebreak ... As it is not always clear if the first 16 bits are at the start or in the middle of a 32bit instruction it may become necessary to strip the first u16 from the output before calling decodecode to get the correct disassembled code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
* | Kconfig: Remove all default n/no optionsMichal Simek2021-08-311-2/+0
| | | | | | | | | | | | | | | | default n/no doesn't need to be specified. It is default option anyway. Signed-off-by: Michal Simek <michal.simek@xilinx.com> [trini: Rework FSP_USE_UPD portion] Signed-off-by: Tom Rini <trini@konsulko.com>
* | Finish converting CONFIG_SYS_CACHELINE_SIZE to KconfigTom Rini2021-08-311-0/+2
|/ | | | | | | | | | | | | | | | | | | | | | | We move the SYS_CACHE_SHIFT_N options from arch/arm/Kconfig to arch/Kconfig, and introduce SYS_CACHE_SHIFT_4 to provide a size of 16. Introduce select statements for other architectures based on current usage. For MIPS, we take the existing arch-specific symbol and migrate to the generic symbol. This lets us remove a little bit of otherwise unused code. Cc: Alexey Brodkin <alexey.brodkin@synopsys.com> Cc: Anup Patel <anup.patel@wdc.com> Cc: Atish Patra <atish.patra@wdc.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Leo <ycliang@andestech.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Sean Anderson <seanga2@gmail.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
* riscv: cpu: fu740: Fix typo of dateZong Li2021-08-171-1/+1
| | | | | | | Fixed the typo of date of copyright declaration. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* efi_loader: add Linux magic to RISC-V crt0Heinrich Schuchardt2021-08-141-2/+5
| | | | | | | | | | | Add the Linux magic to the EFI file header to allow running our test programs with GRUB's linux command. MajorImageVersion = 1 indicates a kernel that can consume the EFI_LOAD_FILE2_PROTOCOL. This allows to dump the GRUB provided intird with our initrddump.efi tool. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* i2c: Rename SPL/TPL_I2C_SUPPORT to I2CSimon Glass2021-07-281-1/+1
| | | | | | | Rename these options so that CONFIG_IS_ENABLED can be used with them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
* board: sifive: drop stuff related to unmatched revision 1Zong Li2021-07-214-1501/+1
| | | | | | | | | | | | | | | | This patch reverts the following commits: - 4b4159d0f3 ("riscv: dts: add dts for unmatched rev1") - ffe9a394df ("board: sifive: support spl multi-dtb on unmatched board") We won't plan to support unmatched that the revision below 3 in u-boot, so they can be dropped because they might be useless. Changed in v2: - rebase codebase to the latest master branch Signed-off-by: Zong Li <zong.li@sifive.com> Suggested-by: David Abdurachmanov <david.abdurachmanov@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* riscv: booti: do not force relocation if force_reloc is not setVitaly Wool2021-07-211-1/+6
| | | | | | | | | If force_reloc flag is not set and booti is called for an address ouside RAM (i. e. QSPI NOR flash), we should honor that and not try to force relocation in a bogus fashion. Signed-off-by: Vitaly Wool <vitaly.wool@konsulko.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* riscv: dts: add OpenPiton RISC-V board dts supportTianrui Wei2021-07-071-2/+2
| | | | | | | | | | Previous device tree for OpenPiton emits a warning during compilation. This commit fixes the previous warning adds dts to the OpenPiton RISC-V board and added the device tree to MAINTAINER file. Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com> Reported-by: Tom Rini <trini@konsulko.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* riscv: dts: add dts for unmatched rev1Zong Li2021-07-064-1/+1501
| | | | | | | | The difference between unmatched rev3 and rev1 is DDR timing, the rev3 uses 1866 MT/s for 16GiB, and rev1 uses 2133 MT/s for 8GiB. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* board: sifive: Add an interface to get PCB revisionZong Li2021-07-061-0/+15
| | | | | | | | | There are different DDR parameter settings for different board revisions. Add a new interface to get the PCB revision to determine which DT should be selected at runtime. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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