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* x86: apl: Re-enable loading of SPLSimon Glass2020-07-091-1/+1
| | | | | | | | | At present the SPL loader is not included in the TPL image so SPL cannot be loaded. Fix it by including this file for both SPL and TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Fixes: c87f9ce2273 ("x86: Don't build some unused objects in TPL") Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Don't build some unused objects in TPLTom Rini2020-06-291-1/+1
| | | | | | | | | | | | In the future if we have separate symbols for DM_SPI_FLASH and SPL_DM_SPI_FLASH we will not always have function declarations available for some DM calls. This in turn leads to build warnings but not failures as the code isn't used and is discarded at link time. Restructure things to not build code we won't use for TPL anyways. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* x86: apl: Use devicetree for FSP-S configurationBernhard Messerklinger2020-05-272-380/+1195
| | | | | | | | | | | | | | | A the moment the FSP-S configuration is a mix of hard coded values and devicetree properties. This patch makes FSP-S full configurable from devicetree by adding binding properties for all FSP-S parameters. Co-developed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> (Tested on coral) Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Use devicetree for FSP-M configurationBernhard Messerklinger2020-05-273-163/+623
| | | | | | | | | | | | | | | | | | A the moment the FSP-M configuration is a mix of hard coded values and devicetree properties. This patch makes FSP-M full configurable from devicetree by adding binding properties for all FSP-M parameters. Co-developed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> (Tested on coral) [sjg: Fix a build error for coral] Signed-off-by: Simon Glass <sjg@chromium.org> [bmeng: Add __maybe_unused to fsp_update_config_from_dtb()] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabledBernhard Messerklinger2020-05-271-21/+25
| | | | | | | | | | Only load VBT if it's present in the u-boot.rom. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> (Tested on coral) Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* common: Drop linux/bitops.h from common headerWIP/2020-05-18-reduce-size-of-common.hSimon Glass2020-05-182-0/+2
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop linux/delay.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop log.h from common headerSimon Glass2020-05-187-0/+7
| | | | | | Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop init.h from common headerSimon Glass2020-05-182-0/+2
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop image.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop bootstage.h from common headerSimon Glass2020-05-182-0/+2
| | | | | | Move this fairly uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Skip init code when chain loadingSimon Glass2020-04-301-0/+2
| | | | | | | | When U-Boot is not the first-stage bootloader the FSP-S init must be skipped. Update it to add a check. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move acpi_s3.h to include/acpi/Simon Glass2020-04-163-3/+3
| | | | | | | | | | | | | This header relates to ACPI and we are about to add some more ACPI headers. Move this one into a new directory so they are together. The header inclusion in pci_rom.c is not specific to x86 anymore, so drop the #ifdef CONFIG_X86. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Use cpu_x86_get_count() for cpu_ops.get_countWolfgang Wallner2020-03-051-6/+1
| | | | | | | | | | | | | Use cpu_x86_get_count() to read the number of cores. cpu_x86_get_count() reads the number of CPUs from the device tree. Using this function we can support multiple Apollo Lake variants, e.g.: E3940 (4 cores) and E3930 (2 cores). This was tested on the E3940 and E3930 Apollo Lake variants. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge tag 'dm-pull-6feb20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dmTom Rini2020-02-113-0/+3
|\ | | | | | | | | | | | | sandbox conversion to SDL2 TPM TEE driver Various minor sandbox video enhancements New driver model core utility functions
| * dm: core: Create a new header file for 'compat' featuresSimon Glass2020-02-053-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
* | x86: coral: Add I2C and TPM device-tree definitionsSimon Glass2020-02-071-0/+1
| | | | | | | | | | | | | | | | Add nodes to the device tree for Cr50 and other available I2C ports. Also enable the ACPI interrupt driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Give each driver an IRQ typeSimon Glass2020-02-071-2/+2
| | | | | | | | | | | | | | | | Add an IRQ type to each driver and use irq_first_device_type() to find and probe the correct one. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: apl: Drop the I2C config in FSP-SSimon Glass2020-02-071-58/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This config is not actually used here and in U-Boot it seems better to set this using the device tree for each individual controller. The monolithic config of the FSP-S is only necessary if the FSP is actually configuring something, but here it is not. The FSP-S does enable/disable the various I2C ports. It might be nice to handle this using the okay/disabled property of each port, but that can be considered later. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: apl: Use the clock driverSimon Glass2020-02-071-0/+3
| | | | | | | | | | | | | | Enable the Intel clock driver and modify coral's device tree to use it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Move P2SB from Apollo Lake to a more generic locationWolfgang Wallner2020-02-073-171/+1
|/ | | | | | | | The Primary to Sideband Bridge (P2SB) is not specific to Apollo Lake, so move its driver to a common location within arch/x86. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: itss: Add a Kconfig option to enable/disable ITSS driverWolfgang Wallner2020-02-041-0/+1
| | | | | | | | | | | | | Add a Kconfig option to support enabling/disabling the inclusion of the ITSS driver depending on the platform. Atuomatically select the ITSS driver when building for Apollo Lake. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232761/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move itss.c from Apollo Lake to a more generic locationWolfgang Wallner2020-02-042-215/+0
| | | | | | | | | | | The Interrupt Timer Subsystem (ITSS) is not specific to Apollo Lake, so move it to a common location within arch/x86. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: conditionally build itss.c] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move itss.h from Apollo Lake to the generic x86 include directoryWolfgang Wallner2020-02-041-1/+1
| | | | | | | | | | | | | The code in this file is not specific to Apollo Lake. According to coreboot sources (where this code comes from), it is common to at least: * Apollo Lake * Cannon Lake * Ice Lake * Skylake Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add the term "Interrupt Timer Subsystem" to ITSS filesWolfgang Wallner2020-02-041-1/+1
| | | | | | | | | ITSS stands for "Interrupt Timer Subsystem", so add that term to the description of the relevant files. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Avoid accessing the PCI bus before it is probedSimon Glass2020-01-072-11/+29
| | | | | | | | The PCI bus is not actually probed by the time the ofdata_to_platdata() method is called since that happens in the uclass's post_probe() method. Update the PMC and P2SB drivers to access the bus in its probe() method. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Add FSP supportSimon Glass2019-12-153-0/+877
| | | | | | | | The memory and silicon init parts of the FSP need support code to work. Add this for Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add Kconfig and MakefileSimon Glass2019-12-151-0/+96
| | | | | | | Add basic plumbing to allow Apollo Lake support to be used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add P2SB driverSimon Glass2019-12-152-0/+167
| | | | | | | | Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add SPL/TPL initSimon Glass2019-12-152-0/+272
| | | | | | | | Add code to init the system both in TPL and SPL. Each phase has its own procedure. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add a CPU driverSimon Glass2019-12-153-0/+60
| | | | | | | Add a bare-bones CPU driver so that CPUs can be probed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add SPL loadersSimon Glass2019-12-152-0/+180
| | | | | | | | Add loaders for SPL and TPL so that the next stage can be loaded from memory-mapped SPI or, failing that, the Fast SPI driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add PUNIT driverSimon Glass2019-12-152-0/+97
| | | | | | | | Add a driver for the Apollo Lake P-unit (power unit). It is modelled as a syscon driver since it only needs to be probed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add PCH driverSimon Glass2019-12-152-0/+37
| | | | | | | | Add a driver for the Apollo Lake Platform Controller Hub. It does not have any functionality and is just a placeholder for now. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add LPC driverSimon Glass2019-12-152-0/+123
| | | | | | | | | This driver the LPC and provides a few functions to set up LPC features. These should probably use ioctls() or perhaps, better, have specific uclass methods. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add ITSS driverSimon Glass2019-12-152-0/+215
| | | | | | | | | This driver models some sort of interrupt thingy but there are so many abreviations that I cannot find out what it stands for. Possibly something to do with interrupts. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add hostbridge driverSimon Glass2019-12-152-0/+180
| | | | | | | | This driver models the hostbridge as a northbridge. It simply sets up the graphics BAR. It supports of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add systemagent driverSimon Glass2019-12-152-0/+25
| | | | | | | | This driver handles communication with the systemagent which needs to be told when U-Boot has completed its init. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add UART driverSimon Glass2019-12-152-0/+134
| | | | | | | | | Add a driver for the Apollo Lake UART. It uses the standard ns16550 device but also sets up the input clock with LPSS and supports configuration via of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add PMC driverSimon Glass2019-12-152-0/+221
Add a driver for the Apollo Lake SoC. It supports the basic operations and can use device tree or of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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