summaryrefslogtreecommitdiff
path: root/arch/x86/cpu
Commit message (Expand)AuthorAgeFilesLines
* common: Move hang() to the same header as panic()Simon Glass2020-01-172-0/+2
* common: Move RAM-sizing functions to init.hSimon Glass2020-01-171-0/+1
* common: Move ll_boot_init() to init.hSimon Glass2020-01-175-0/+5
* x86: apl: Avoid accessing the PCI bus before it is probedSimon Glass2020-01-072-11/+29
* x86: apl: Add FSP supportSimon Glass2019-12-153-0/+877
* x86: apl: Add Kconfig and MakefileSimon Glass2019-12-152-0/+97
* x86: apl: Add P2SB driverSimon Glass2019-12-152-0/+167
* x86: apl: Add SPL/TPL initSimon Glass2019-12-152-0/+272
* x86: apl: Add a CPU driverSimon Glass2019-12-153-0/+60
* x86: apl: Add SPL loadersSimon Glass2019-12-152-0/+180
* x86: apl: Add PUNIT driverSimon Glass2019-12-152-0/+97
* x86: apl: Add PCH driverSimon Glass2019-12-152-0/+37
* x86: apl: Add LPC driverSimon Glass2019-12-152-0/+123
* x86: apl: Add ITSS driverSimon Glass2019-12-152-0/+215
* x86: apl: Add hostbridge driverSimon Glass2019-12-152-0/+180
* x86: apl: Add systemagent driverSimon Glass2019-12-152-0/+25
* x86: apl: Add UART driverSimon Glass2019-12-152-0/+134
* x86: apl: Add PMC driverSimon Glass2019-12-152-0/+221
* x86: Move qemu CPU fixup function into its own fileSimon Glass2019-12-153-68/+79
* x86: Add low-power subsystem (lpss) supportSimon Glass2019-12-152-0/+45
* x86: Add support for newer CAR schemesSimon Glass2019-12-153-0/+543
* x86: Allow interrupt to happen onceSimon Glass2019-12-152-9/+1
* x86: Update mrccache to support multiple cachesSimon Glass2019-12-153-9/+15
* x86: Define the SPL image startSimon Glass2019-12-151-1/+4
* x86: Move UCLASS_IRQ into a separate fileSimon Glass2019-12-151-5/+0
* x86: Drop unnecessary interrupt code for TPLSimon Glass2019-12-151-0/+2
* x86: Drop unnecessary cpu code for TPLSimon Glass2019-12-152-4/+41
* x86: timer: use a timer base of 0Simon Glass2019-12-152-0/+2
* x86: spi: Add helper functions for Intel Fast SPISimon Glass2019-12-152-0/+74
* x86: simplify ljmp to 32-bit codeMasahiro Yamada2019-12-081-3/+1
* x86: use data32 directive instead of macro for operand-size prefixMasahiro Yamada2019-12-081-5/+3
* common: Move board_get_usable_ram_top() out of common.hSimon Glass2019-12-029-0/+9
* common: Move interrupt functions into a new headerSimon Glass2019-12-022-0/+2
* common: Move ARM cache operations out of common.hSimon Glass2019-12-021-0/+1
* common: Move some cache and MMU functions out of common.hSimon Glass2019-12-023-0/+3
* common: Move checkcpu() out of common.hSimon Glass2019-12-0210-0/+10
* x86: Move CPU init to before spl_init()Simon Glass2019-11-031-0/+1
* x86: Add a CPU init function for TPLSimon Glass2019-11-031-0/+8
* x86: Reduce resetvec sizeSimon Glass2019-10-111-3/+0
* x86: Drop RESET_SEG_SIZESimon Glass2019-10-111-1/+0
* x86: Drop RESET_BASESimon Glass2019-10-111-1/+0
* x86: cpu: Don't include the cpu driver in TPLSimon Glass2019-10-081-1/+4
* x86: Add a function to set variable MTRRsSimon Glass2019-10-081-0/+38
* x86: Refactor mtrr_commit() to allow for shared codeSimon Glass2019-10-081-7/+12
* x86: Add new common CPU functions for turbo/burst modeSimon Glass2019-10-081-0/+61
* x86: Tidy up some duplicate MSR definesSimon Glass2019-10-083-11/+11
* x86: Add common functions for TDP and perf controlSimon Glass2019-10-085-32/+33
* x86: Use a common bus clock for Intel CPUsSimon Glass2019-10-083-5/+5
* x86: Add a common function to set CPU thermal targetSimon Glass2019-10-083-41/+26
* x86: Use a common definition of MSR_IA32_PERF_CTLSimon Glass2019-10-083-3/+3
View Lorry Controller Status