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* ARM: uniphier: replace <common.h> with <linux/delay.h> in pll settingsMasahiro Yamada2017-08-302-2/+2
| | | | | | | | | | The #include <common.h> was added for mdelay(). Later, the declaration of mdelay was moved to <linux/delay.h> by commit 5bc516ed661a ("delay: collect {m, n, u}delay declarations to include/linux/delay.h"). There is no need to include <common.h> now. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge git://git.denx.de/u-boot-shTom Rini2017-08-261-4/+5
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| * arch/sh: don't bring common/env_embedded.o into the linkThomas Petazzoni2017-08-261-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The linker script for SuperH brings the .ppcenv and .ppcenvr section of common/env_embedded.o into the .text section. However, the .ppcenv section is only ever filled in by env_embedded.o when CONFIG_SYS_USE_PPCENV is defined, but no platforms in mainline U-Boot use this. In addition, common/env_embedded.o is not always built (when you use CONFIG_ENV_IS_NOWHERE for example), which causes the following build failure: Fixes: LD u-boot /home/thomas/sh4aeb-linux-musl/bin/sh4aeb-linux-ld.bfd: cannot find common/env_embedded.o We fix this by no longer adding the .ppcenv and .ppcenvr sections from common/env_embedded.o into the .text section. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * arch/sh: allow building in big-endian modeThomas Petazzoni2017-08-261-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | The SuperH architecture allows to be run in either little or big endian mode. Some SuperH SoCs get the little vs. big endian decision through mode pins sampled at reset, so if big endian has been choosen by HW designers, it cannot be easily changed. Therefore, it makes sense to allow building U-Boot for SuperH in big endian mode. To allow this, the only change needed is to adjust the OUTPUT_FORMAT() in the linker script. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* | Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2017-08-262-0/+8
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| * | ARM: rmobile: Add u-boot, dm-pre-reloc to clock nodes on Gen3Marek Vasut2017-08-262-0/+8
| |/ | | | | | | | | | | | | | | | | We need the clock available very early, add the u-boot,dm-pre-reloc DT property on those nodes, so they come up very in the process. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | Merge git://git.denx.de/u-boot-x86Tom Rini2017-08-266-1/+47
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| * | x86: tangier: kconfig: Guard tangier-specific optionsBin Meng2017-08-241-0/+4
| | | | | | | | | | | | | | | | | | | | | These options should not be exposed to other platforms. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| * | x86: baytrail: Fix turbo enableBin Meng2017-08-241-0/+1
| | | | | | | | | | | | | | | | | | CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED must be turned on for Baytrail. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Convert CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED to KconfigBin Meng2017-08-242-1/+8
| | | | | | | | | | | | | | | | | | This converts CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED to a Kconfig option. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: kconfig: Imply CMD_PCIBin Meng2017-08-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Let's imply the 'pci' command to access the de facto interconnect bus in an x86 system. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | x86: fsp: Configure SPI opcode registers before SPI is locked downBin Meng2017-08-242-0/+33
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some Intel FSP (like Braswell) does SPI lock-down during the call to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done, it's bootloader's responsibility to configure the SPI controller's opcode registers properly otherwise SPI controller driver doesn't know how to communicate with the SPI flash device. This introduces a Kconfig option CONFIG_FSP_LOCKDOWN_SPI for such FSPs. When it is on, U-Boot will configure the SPI opcode registers before the lock-down. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
* | spl: stm32: make falcon mode activation configurableVikas Manocha2017-08-261-1/+1
| | | | | | | | | | | | | | | | | | With this change, it will be possible to de-select falcon mode & spl will only boot U-Boot. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Suggested-by: Bo Shen <voice.shen@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARMv8/sec_firmware : Update chosen/kaslr-seed with random numberRuchika Gupta2017-08-263-3/+142
| | | | | | | | | | | | | | | | | | | | | | kASLR support in kernel requires a random number to be passed via chosen/kaslr-seed propert. sec_firmware generates this random seed which can then be passed in the device tree node. sec_firmware reserves JR3 for it's own usage. Node for JR3 is removed from device-tree. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
* | arch/arm/cpu/arm926ejs/spear/cpu.c: guard do_switch_ecc() with CONFIG_NAND_FSMCThomas Petazzoni2017-08-261-1/+1
| | | | | | | | | | | | | | | | | | do_switch_ecc() calls fsmc_nand_switch_ecc(), which is a direct function call into drivers/mtd/nand/fsmc_nand.c. However, this function is not guarded by CONFIG_NAND_FSMC, which results to a build failure if CONFIG_NAND_FSMC is disabled. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* | board/spear/common: move code to arch/arm/cpu/arm926ejs/spear/Thomas Petazzoni2017-08-263-0/+425
| | | | | | | | | | | | | | | | | | | | | | | | | | The code in board/spear/common/ is not board-specific but SoC-specific. Therefore, boards from other vendors than "spear" may want to re-use this code, which is currently difficult with the code being placed in board/spear/common/. Since this code really is SoC-specific, this commit moves it to arch/arm/cpu/arm926ejs/spear/, with the rest of the SPEAr related code. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* | board: atmel: Use the new PIT timer driverWenyou.Yang@microchip.com2017-08-261-0/+28
| | | | | | | | | | | | | | Use the Atmel PIT timer driver which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
* | driver: timer: Add the Atmel PIT timer driverWenyou.Yang@microchip.com2017-08-262-0/+4
| | | | | | | | | | | | | | Add the new Atmel PIT timer driver, which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
* | powerpc: Rework interrupt_init_cpu()Tom Rini2017-08-266-19/+6
| | | | | | | | | | | | | | | | The function interrupt_init_cpu() is given an int return type but does not return anything but 0. Rework this to be a void function. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Mario Six <mario.six@gdsys.cc>
* | arm: dts: am33xx: sync DTS with Linux 4.13-rc4Suniel Mahesh2017-08-261-6/+0
|/ | | | | | | | | | This re-syncs AM33xx DTS file with current file from Linux v4.13-rc4 to ensure a consistent configuration. Upstream Linux removed the redundant Interrupt-parent property from mmc, mac, lcdc and tscadc sub nodes. Signed-off-by: Suniel Mahesh <sunil.m@techveda.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: dts: uniphier: add dr_mode property to dwc3 nodeMasahiro Yamada2017-08-204-0/+7
| | | | | | | Since commit 576e3cc700c5 ("usb: host: xhci-dwc3: Add dual role mode support from DT"), warning is displayed if dr_mode is not specified. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Revert "ARM: uniphier: fix ROM boot mode for PH1-sLD3"Masahiro Yamada2017-08-201-5/+0
| | | | | | | | | | | This reverts commit 82d075e79fa509ffb8ecd8dd2dc216929d6e8289. Commit 82d075e79fa5 ("ARM: uniphier: fix ROM boot mode for PH1-sLD3") was a workaround for sLD3. Now the sLD3 SoC support has been removed. Revert it to allow to simplify the init code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Revert "ARM: uniphier: move lowlevel debug init code after page table switch"Masahiro Yamada2017-08-201-4/+4
| | | | | | | | | | | | This reverts commit bcc51c1512a3deb6a9fdd37362c6dde32ad3da23. Commit bcc51c1512a3 ("ARM: uniphier: move lowlevel debug init code after page table switch") was intended to support lowlevel debug for sLD3. Now the sLD3 SoC support has been removed. Revert it to allow to enable lowlevel debug earlier. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove sLD3 SoC supportMasahiro Yamada2017-08-2035-898/+26
| | | | | | This SoC is too old. It is difficult to maintain any longer. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* clk: uniphier: fix unmet direct dependencies warningMasahiro Yamada2017-08-201-1/+0
| | | | | | | | | | | | | | Since commit f0776a551764 ("spl: dm: Kconfig: SPL_CLK depends on SPL_DM"), the following warning is displayed: $ make uniphier_v8_defconfig warning: (ARCH_ZYNQ && ARCH_ZYNQMP && STM32F7 && CLK_UNIPHIER) selects SPL_CLK which has unmet direct dependencies (CLK && SPL_DM) While I am here, I am removing the prompt to make it user-unconfigurable option so that "select CLK_UNIPHIER" can be omitted. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mmcTom Rini2017-08-185-8/+117
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| * dm: mmc: Drop CONFIG_DM_MMC_OPSSimon Glass2017-08-171-2/+0
| | | | | | | | | | | | | | All boards which use DM_MMC have now been converted to use DM_MMC_OPS. Drop the option and good riddance. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: imx: cm_fx6: Add device tree for cm_fx6Simon Glass2017-08-172-0/+116
| | | | | | | | | | | | | | Add this file so we can use device-tree control for cm_fx6. It comes from linux 4.12. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: sata: imx: Allow driver model to be used for sataSimon Glass2017-08-171-1/+1
| | | | | | | | | | | | Update the sata call to work with driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
| * mmc: sh_sdhi: Fix the ACMD handlingMarek Vasut2017-08-171-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The command handling in this driver is awful, esp. because the driver depends on command numbers to determine whether this is APPCMD or not. Also, handling of command RSP response types is totally wrong. This patch at least plucks out some of the custom command encoding and fixes the APPCMD handling. The RSP handling still needs work, yet that might not be needed as it turns out the uniphier-sd.c driver is in much better shape and supports the same IP, so we might be able to just drop this driver in favor of the uniphier one. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-coldfireTom Rini2017-08-184-184/+32
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| * | m68k: add board stmark2, mcf5441x basedAngelo Dureghello2017-08-181-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sysam stmark2 board is a generic and fully (hw and sw) open board, with a mcf54415 Coldfire CPU, 128MB of DDR2, 16MB of SPI flash and SD card as non volatile memories, and a wifi module included on-board. The board is actually used mainly for Coldfire custodian testing activity related to the mcf5441x Coldfire family. For further information please see: http://sysam.it/cff_stmark2.html Signed-off-by: Angelo Dureghello <angelo@sysam.it> --- Changes in v2: - remove CMD_REGINFO - add board information in commit message
| * | m68k: mcf5445x: allow CS0 to be undefinedAngelo Dureghello2017-08-182-0/+6
| | | | | | | | | | | | | | | | | | | | | On some boards, CONFIG_SYS_CS0_BASE can be undefined, since CS0 is not connected to any signal. Signed-off-by: Angelo Dureghello <angelo@sysam.it>
| * | m68k: fix cache.c for Coldfire V4EAngelo Dureghello2017-08-181-12/+13
| | | | | | | | | | | | | | | | | | | | | - fix cache.c CONFIG_CF_V4e to CONFIG_CF_V4E - fix cache.c to properly enable/disable cache for V4E Signed-off-by: Angelo Dureghello <angelo@sysam.it>
| * | m68k: mcf5445x: move early ddr init as board-specificAngelo Dureghello2017-08-181-172/+8
| | | | | | | | | | | | | | | | | | | | | | | | For certain boot types and sbf, for V4 cpu's, an early ddr/sdram init is required. This patch moves this ddr/sdram early initalization away from start.S (to be board related). Signed-off-by: Angelo Dureghello <angelo@sysam.it>
* | | rockchip: rk322x: update MACRO for mmc clksel regKever Yang2017-08-181-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | The description for eMMC/SDIO/SDMMC src is not correct, update the CRU_CLKSEL11_CON value definition according to TRM. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | | rockchip: rk322x: update dram bank sizeKever Yang2017-08-181-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DRAM start address is not 0, so need to update the last bank size as: DRAM start addr + DRAM_SIZE - last bank start addr Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | rockchip: rk3399: spl: remove unused header inclusionPhilipp Tomsich2017-08-181-1/+0
| | | | | | | | | | | | | | | | | | | | | fdtdec.h is included, but not used in rk3399-board-spl.c: remove the '#include'-statement. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | | rockchip: dts: rk3399-evb: remove redundant gmac nodeKever Yang2017-08-181-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | There are two same gmac node, remove one. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | | rockchip: dts: rk3399-firefly: update gmac parameterKever Yang2017-08-171-2/+2
|/ / | | | | | | | | | | | | | | | | | | Update the tx_delay and rx_delay to match the timing for rk3399-firefly board to improve the stability of gmac data transfer. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | Merge git://git.denx.de/u-boot-tegraTom Rini2017-08-164-14/+10
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| * | apalis_t30/tk1, colibri_t20/t30: fix i2c bus frequenciesMarcel Ziswiler2017-08-154-10/+10
| | | | | | | | | | | | | | | Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | apalis-tk1: remove duplicate hdmi_ddc device tree nodeMarcel Ziswiler2017-08-151-4/+0
| |/ | | | | | | | | Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Merge git://git.denx.de/u-boot-sunxiTom Rini2017-08-167-1/+236
|\ \ | | | | | | | | | | | | | | | Update A20-OLinuXino-Lime2-eMMC_defconfig to include CONFIG_SCSI Signed-off-by: Tom Rini <trini@konsulko.com>
| * | sun50i: a64: Add A64-OLinuXino initial supportJagan Teki2017-08-152-0/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OLimex A64-OLinuXino is an open-source hardware board using the Allwinner A64 SOC. OLimex A64-OLinuXino has - A64 Quad-core Cortex-A53 64bit - 1GB or 2GB RAM DDR3L @ 672Mhz - microSD slot and 4/8/16GB eMMC - Debug TTL UART - HDMI - LCD - IR receiver - 5V DC power supply Tested-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sun50i: a64: Add initial NanoPi A64 supportJagan Teki2017-08-152-0/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NanoPi A64 is a new board of high performance with low cost designed by FriendlyElec., using the Allwinner A64 SOC. Nanopi A64 features - Allwinner A64, 64-bit Quad-core Cortex-A53@648MHz to 1.152GHz, DVFS - 1GB DDR3 RAM - MicroSD - Gigabit Ethernet (RTL8211E) - Wi-Fi 802.11b/g/n - IR receiver - Audio In/Out - Video In/Out - Serial Debug Port - microUSB 5V 2A DC power-supply Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sun50i: a64: Sync Linux [oe]hci0 nodesJagan Teki2017-08-111-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Synced ohci0 and ehci0 nodes from Linux for sun50i-a64.dtsi Here is the Linux last merge tag details: Merge: 0e91f43d e5770b7 Author: Stephen Rothwell <sfr@canb.auug.org.au> Date: Fri Jun 9 14:59:55 2017 +1000 Merge remote-tracking branch 'staging/staging-next' Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sunxi: switch PRCM to non-secure on H3/H5 SoCsIcenowy Zheng2017-08-111-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PRCM of H3/H5 SoCs have a secure/non-secure switch, which controls the access to some clock/power related registers in PRCM. Current Linux kernel will access the CPUS (AR100) clock in the PRCM block, so the PRCM should be switched to non-secure. Add code to switch the PRCM to non-secure. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | sunxi: add PRCM secure switch register definitionIcenowy Zheng2017-08-111-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some new Allwinner SoCs' PRCM has a secure switch register, which controls the access to some clock and power registers in PRCM block. Add the definition of this register and its bits in the PRCM header file. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Tested-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | ARM: dts: sunxi: Change node name for pwrseq pin on Olinuxino-lime2-emmcEmmanuel Vadot2017-08-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The node name for the power seq pin is mmc2@0 like the mmc2_pins_a one. This makes the original node (mmc2_pins_a) scrapped out of the dtb and result in a unusable eMMC if U-Boot didn't configured the pins to the correct functions. Signed-off-by: Emmanuel Vadot <manu@bidouilliste.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
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