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* video: arm: rpi: Move the video settings out of the driverSimon Glass2017-05-092-0/+78
| | | | | | | | Add a function to set the video parameters to the msg handler and remove it from the video driver. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
* video: arm: rpi: Move the video query out of the driverSimon Glass2017-05-092-0/+35
| | | | | | | | Add a function to get the video size to the msg handler and remove it from the video driver. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
* arm: rpi: Add a function to obtain the MMC clockSimon Glass2017-05-092-0/+35
| | | | | | Move this code into the new message handler file. Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: rpi: Add a file to handle messagesSimon Glass2017-05-093-1/+58
| | | | | | | | | | | | | | | The bcm283x chips provide a way for the ARM core to communicate with the graphics processor, which is in charge of many things. This is handled by way of a message prototcol. At present the code for sending message (and receiving a reply) is spread around U-Boot, primarily in the board file. This means that sending a message from a driver requires duplicating the code. Create a new message implementation with a function to support powering on a subsystem as a starting point. Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: rpi: Drop the GPIO device addressesSimon Glass2017-05-091-5/+0
| | | | | | We can rely on the device tree to provide this information. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-dmTom Rini2017-05-0940-263/+6664
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| * dra7: dtsi: mark ocp2scp bus compatible with "simple-bus"Jean-Jacques Hiblot2017-05-091-0/+4
| | | | | | | | | | | | | | | | This is needed to probe devices under that bus such as the SATA PHY. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * dm: test: Add tests for the generic PHY uclassJean-Jacques Hiblot2017-05-091-0/+17
| | | | | | | | | | | | | | | | | | | | | | Those tests check: - the ability for a phy-user to get a phy based on its name or its index - the ability of a phy device (provider) to manage multiple ports - the ability to perform operations on the phy (init,deinit,on,off) - the behavior of the uclass when optional operations are not implemented Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * ARM: dts: at91: Add dts files for at91sam9263ekWenyou Yang2017-05-093-89/+340
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The device tree source files of at91sam9263ek boards are copied from the Linux v4.10, do the changes as below. - Add the reg property for the pinctrl node. - Move the gpio (pioA, pioB, pioC, pioD, pioE) nodes as the pinctrl's slibling nodes, instead of the child nodes. - Add the "u-boot,dm-pre-reloc" property for the dbgu node are used in board_init_f stage. - Fix the compilation warnings. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * ARM: dts: at91: Add dts files for at91sam9rlekWenyou Yang2017-05-093-0/+1380
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The device tree source files of at91sam9rlek boards are copied from the Linux v4.10, do the changes as below. - Add the reg property for the pinctrl node. - Move the gpio (pioA, pioB, pioC, pioD) nodes as the pinctrl's slibling nodes, instead of the child nodes. - Add the "u-boot,dm-pre-reloc" property for the dbgu node are used in board_init_f stage. - Fix the compilation warnings. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * ARM: dts: at91: Add dts files for at91sam9260ek/9g20ekWenyou Yang2017-05-097-68/+617
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The device tree source files of at91sam9g20ek and at91sam9260ek boards are copied from the Linux v4.10, do the changes below. - Fix the build error for the usb0 node. - Add the reg property for the pinctrl node. - Move the gpio (pioA, pioB, pioC ...) nodes as the pinctrl's slibling nodes, instead of the child nodes. - Add the "u-boot,dm-pre-reloc" property for the dbgu node are used in board_init_f stage. - Add the clk pinctrl of the mmc0 node. - Fix the compilation warnings. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * ARM: dts: at91: Add dts files for at91sam9m10g45ekWenyou Yang2017-05-093-105/+474
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The device tree source files of at91sam9m10g45ek boards are copied from the Linux v4.10, do the changes as below. - Add the reg property for the pinctrl node. - Move the gpio (pioA, pioB, pioC, pioD, pioE) nodes as the pinctrl's slibling nodes, instead of the child nodes. - Add the "u-boot,dm-pre-reloc" property to determine which nodes are used by the board_init_f stage. - Fix the compilation warnings. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * ARM: dts: at91: Add dts files for at91sam9n12ekWenyou Yang2017-05-093-0/+1331
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The device tree source files of at91sam9n12ek boards are copied from the Linux v4.10, do the changes as below. - Add the reg property for the pinctrl node. - Move the gpio (pioA, pioB, pioC, pioD) nodes as the pinctrl's slibling nodes, instead of the child nodes. - Change the compatible of the spi flash to "spi-flash". - Add the spi0 aliases. - Fix the pinctrl-names of mmc0 node. - Add the "u-boot,dm-pre-reloc" property to determine which nodes are used by the board_init_f stage. - Fix the compilation warnings. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * ARM: dts: at91: Add dts files for at91sam9x5ekWenyou Yang2017-05-0921-0/+2461
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The device tree source files of at91sam9x5ek board are copied from the Linux v4.10, do the changes below. - Add the reg property for the pinctrl node. - Move the gpio (pioA, pioB, pioC ...) nodes as the pinctrl's slibling nodes, instead of the child nodes. - Add the "u-boot,dm-pre-reloc" property to determine which nodes are used by the board_init_f stage. - Change the compatible of the spi flash to "spi-flash". - Add the spi0 aliases. - Fix the compilation warnings. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * board: sama5d4ek: fix DD2 configurationWenyou Yang2017-05-091-1/+6
| | | | | | | | | | | | Fix the DDR2 configuration to make SPL work. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
| * ARM: dts: sama5d2_xplained: update for SPLWenyou Yang2017-05-092-0/+32
| | | | | | | | | | | | | | Add the "u-boot,dm-pre-reloc" property to determine which nodes which are needed by SPL and by the board_init_f stage. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
| * ARM: dts: sama5d2: add clock property for uart1 nodeWenyou Yang2017-05-091-0/+2
| | | | | | | | | | | | Add clock property for uart1 node. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
* | Merge git://www.denx.de/git/u-boot-marvellTom Rini2017-05-0914-126/+397
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| * | ARM: mvebu: switch db-88f6820-amc to DM for i2cChris Packham2017-05-091-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move existing configuration from header file to defconfig or dts as appropriate. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
| * | fix: phy: marvell: cp110: update comphy selector optionStefan Roese2017-05-092-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Align PHY selectors register with Armada-CP-110 functional SPEC update all relevant device trees with this change. Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | phy: marvell: cp110: update utmi phy connection typeStefan Roese2017-05-092-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UTMI_PHY_TO_USB_HOST was used in USB3 UTMI dts node only, but there will be USB2 UTMI dts node for some SoCs that have got USB2 controller, so rename TO_USB_HOST to TO_USB3_HOST to distinguish TO_USB2_HOST in later on patches. Signed-off-by: zachary <zhangzg@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | phy: marvell: Replace PHY_TYPE_KR with PHY_TYPE_SFIStefan Roese2017-05-092-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | Use correct naming as done in the latest Marvell U-Boot version as well. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | arm: mvebu: Minor fixes in the AXP / A38x SERDES codeUwe Kleine-König2017-05-094-8/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | - Fix spelling error of SERDES_VERSION - Remove superfluous definition of this macro - Remove unnecessary include of i2c.h Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm64: a8k: dts: Add support for NAND devices on A8K platformKonstantin Porotchkin2017-05-094-0/+239
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add NAND to CP master device tree. Add armada-7040-db-nand device tree for the board configured with NAND boot device. Add comment about boot device ID to armada-7040-db DTS. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | arm64: mvebu: a8k: Add support for NAND clock getKonstantin Porotchkin2017-05-091-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement mvebu_get_nand_clock call for A8K family. This function is used by PXA3XX NAND driver. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | arm64: mvebu: Trigger PCI devices scan at early init stageKonstantin Porotchkin2017-05-091-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PCIe initialization at early init stage. This operation has a side effect of detecting all PCIe plug-in cards, so the operator is not obligated to issue "pci enum" command though CLI for this purpose. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | mvebu: dts: a80x0: Sync the DB DTS with standard config AKonstantin Porotchkin2017-05-091-107/+115
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sync the default configuration of Armada-8040-DB with Marvell u-boot-2015 standard configuration "A" for the same board. The standard configuration "A" enables 2 PCIe slots on CP0 and 3 PCIe slots on CP1. This is the main configuration used for u-boot and Linux tests. This patch also re-arranges the DTS file entries by grouping all nodes related to CP0 and CP1. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
* | ARM: keystone: Enable DM_I2C by defaultCooper Jr., Franklin2017-05-091-0/+4
| | | | | | | | | | | | | | | | | | Enable by default DM_I2C for all Texas Instruments Keystone 2 based evms. Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* | ARM: dts: keystone-k2g-evm: Enable I2C0 and I2C1Cooper Jr., Franklin2017-05-091-0/+8
| | | | | | | | | | | | | | | | Enable I2C0 and I2C1 which is needed to enable usage of DM I2C. Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* | ARM: dts: keystone2: add I2C aliases for davinci I2C nodesCooper Jr., Franklin2017-05-091-0/+3
| | | | | | | | | | | | | | | | | | Add aliases for I2C nodes required for the DM framework to probe the davinci-i2c driver. Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* | ARM: dts: k2g: Add I2C nodes to 66AK2GxCooper Jr., Franklin2017-05-091-0/+32
|/ | | | | | | | Add I2C nodes to the 66AK2Gx dtsi. Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2017-05-087-3/+933
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| * sunxi: add clock configuration of R40 sataIcenowy Zheng2017-05-022-2/+23
| | | | | | | | | | | | | | | | | | | | | | R40 has a similar SATA controller with the ones on A10/A20, but with a reset line added (like other peripherals on sun6i+), and two extra VDD pins added (1.2v and 2.5v). Add clock configuration of R40 SATA. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * ARM: sunxi: use imply instead of bare default y in KconfigMasahiro Yamada2017-05-022-26/+8
| | | | | | | | | | | | | | Fix annoying config redefines in SoC/board level Kconfig. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * ARM: sunxi: move board/sunxi/Kconfig to arch/arm/mach-sunxi/KconfigMasahiro Yamada2017-05-022-1/+794
| | | | | | | | | | | | | | For the consistent location of SoC-level Kconfig. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: video: Add A64/H3/H5 HDMI driverJernej Skrabec2017-04-282-0/+132
| | | | | | | | | | | | | | | | | | This commit adds support for HDMI output. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: i2c: Add support for DM I2CJernej Skrabec2017-04-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds support for DM I2C on sunxi platform. It can coexist with old style sunxi I2C driver, because it is still used in SPL and by some SoCs. Because sunxi platform doesn't yet support DM clk, reset and pinctrl driver, workaround is needed to enable clocks and set resets and pinctrls. This is done by calling i2c_init_board() in board_init(). This means that CONFIG_I2Cx_ENABLE options needs to be correctly set in order to use needed I2C controller. Commit is based on the previous patch made by Philipp Tomsich Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: keystone2: Add support for getting external clock dynamicallyLokesh Vutla2017-05-082-7/+7
| | | | | | | | | | | | | | | | | | | | One some keystone2 platforms like K2G ICE, there is an option to switch between 24MHz or 25MHz as sysclk. But the existing driver assumes it is always 24MHz. Add support for getting all reference clocks dynamically by reading boot pins. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: k2g: Add support for dynamic programming of PLL based on SYSCLKLokesh Vutla2017-05-082-2/+23
| | | | | | | | | | | | | | | | | | | | K2G supports various sysclk frequencies which can be determined using sysboot pins. PLLs should be configured based on this sysclock frequency. Add PLL configurations for all supported sysclk frequencies. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Add ARM errata workaround 852421 and 852423 for Cortex-A17Nisal Menuka2017-05-082-0/+18
| | | | | | | | | | | | | | | | | | ARM errata 852421 and 852423 applies to r1p0, r1p1 and r1p2 revisions of Cortex-A17 processors. These workarounds exist in Linux kernel and I thought it would be better to add them in to U-Boot. Signed-off-by: Nisal Menuka <nisalmenuka23@gmail.com>
* | aspeed: Cleanup ast2500-u-boot.dtsi Device Treemaxims@google.com2017-05-081-20/+21
| | | | | | | | | | | | | | | | Remove unnecessary apb and ahb nodes and just override necessary nodes/values. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | aspeed: Refactor SCU to use consistent mask & shiftmaxims@google.com2017-05-082-9/+8
| | | | | | | | | | | | | | | | | | Refactor SCU header to use consistent Mask & Shift values. Now, consistently, to read value from SCU register, mask needs to be applied before shift. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | aspeed: Add support for Clocks needed by MACsmaxims@google.com2017-05-082-2/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for clocks needed by MACs to ast2500 clock driver. The clocks are D2-PLL, which is used by both MACs and PCLK_MAC1 and PCLK_MAC2 for MAC1 and MAC2 respectively. The rate of D2-PLL is hardcoded to 250MHz -- the value used in Aspeed SDK. It is not entirely clear from the datasheet how this clock is used by MACs, so not clear if the rate would ever need to be different. So, for now, hardcoding it is probably safer. The rate of PCLK_MAC{1,2} is chosen based on MAC speed selected through hardware strapping. So, the network driver would only need to enable these clocks, no need to configure the rate. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | aspeed: Add P-Bus clock in ast2500 clock drivermaxims@google.com2017-05-081-1/+2
| | | | | | | | | | | | | | | | Add P-Bus Clock support to ast2500 clock driver. This is the clock used by I2C devices. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | aspeed: AST2500 Pinctrl Drivermaxims@google.com2017-05-082-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | This driver uses Generic Pinctrl framework and is compatible with the Linux driver for ast2500: it uses the same device tree configuration. Not all pins are supported by the driver at the moment, so it actually compatible with ast2400. In general, however, there are differences that in the future would be easier to maintain separately. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | aspeed: Refactor AST2500 RAM Driver and Sysreset Drivermaxims@google.com2017-05-084-99/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change switches all existing users of ast2500 Watchdog to Driver Model based Watchdog driver. To perform system reset Sysreset Driver uses first Watchdog device found via uclass_first_device call. Since the system is going to be reset anyway it does not make much difference which watchdog is used. Instead of using Watchdog to reset itself, SDRAM driver now uses Reset driver to do that. These were the only users of the old Watchdog API, so that API is removed. This all is done in one change to avoid having to maintain dual API for watchdog in between. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | aspeed: Device Tree configuration for Reset Drivermaxims@google.com2017-05-082-0/+25
| | | | | | | | | | | | | | | | Add Reset Driver configuration to ast2500 SoC Device Tree and bindings for various reset signals Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | aspeed: Reset Drivermaxims@google.com2017-05-081-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Reset Driver for ast2500 SoC. This driver uses Watchdog Timer to perform resets and thus depends on it. The actual Watchdog device used needs to be configured in Device Tree using "aspeed,wdt" property, which must be WDT phandle, for example: rst: reset-controller { compatible = "aspeed,ast2500-reset"; aspeed,wdt = <&wdt1>; } Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | aspeed: Make SCU lock/unlock functions part of SCU APImaxims@google.com2017-05-082-0/+29
| | | | | | | | | | | | | | | | | | Make functions for locking and unlocking SCU part of SCU API. Many drivers need to modify settings in SCU and thus need to unlock it first. This change makes it possible. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | aspeed: Watchdog Timer Drivermaxims@google.com2017-05-082-13/+80
| | | | | | | | | | | | | | | | | | This driver supports ast2500 and ast2400 SoCs. Only ast2500 supports reset_mask and thus the option of resettting individual peripherals using WDT. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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