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* ARM: DRA7: Cleanup old pinctrl macrosSuman Anna2017-09-141-14/+0
| | | | | | | | | Commit 6ae4c3efbd62 ("ARM: DRA7: Add pinctrl register definitions") has added new macros for pinmux configuration in line with the kernel definitions. Cleanup the old pinctrl macros from the common header file so that they are not used by any new boards. Signed-off-by: Suman Anna <s-anna@ti.com>
* ARM: at91: spl: Add macro CONFIG_XXXX_BOOT supportWenyou Yang2017-09-141-6/+10
| | | | | | | | Use the CONFIG_XXXX_BOOT to indicate the boot media, instead of the CONFIG_SYS_USE_XXXX option, which is declared by CONFIG_SYS_EXTRA_OPTIONS option. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
* ARM: at91: Remove hardware.h included in configsWenyou Yang2017-09-143-0/+3
| | | | | | | | | | As said in READRE.kconfig, include/configs/*.h will be removed after all options are switched to Kconfig. As the first step, remove the follow line from include/configs/*.h. #include <asm/hardware.h> Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
* ARM: at91: Add the SoC options to KconfigWenyou Yang2017-09-141-27/+79
| | | | | | | | To prepare to remove the SoCs options such as SAMA5D2, SAMA5D3 and SAMA5D4 from the CONFIG_SYS_EXTRA_OPTIONS option which is deprecated, add the SoC options to Kconfig. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
* ARM: at91: Move CONFIG_AT91FAMILY option to KconfigWenyou Yang2017-09-1411-43/+3
| | | | | | | Move the CONFIG_AT91FAMILY option from include/mach/<soc>.h header file to Kconfig. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
* board: atmel: Add SAMA5D27 SOM1 EK boardWenyou Yang2017-09-145-0/+411
| | | | | | | | | | | The SAMA5D27-SiP (System in Package) integrates the SAMA5D2 with 1Gbit DDR2-SDRAM in a single package. The SAMA5D27 SOM1 embeds a 64Mbit QSPI flash, KSZ8081 Phy and Mac-address EEPROM. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: at91: Get the Chip ID of SAMA5D2 SiPWenyou Yang2017-09-142-3/+30
| | | | | | | | The SAMA5D2 SiP(System in Package) has different Chip IDs in the CHIPID and CHIP_EXID registers. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: at91: mach: Add missing defines of MPDDRCWenyou Yang2017-09-141-0/+4
| | | | | | | Add missing defines of Multiport DDR-SDRAM Controller (MPDDRC). Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: at91: spl: Add boot device for boot from QSPIWenyou Yang2017-09-141-0/+2
| | | | | | | Add the boot device for booting from the QSPI flash. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: at91: spl: Add mck function to lower rate while switchingWenyou Yang2017-09-142-0/+43
| | | | | | | | | | | | | | | Refer to the commit 70f8c8316ad(PMC: add new mck function to lower rate while switching) from AT91Bootstrap. While switching to a lower clock source, we must switch the clock source first instead of last. Otherwise, we could end up with too high frequency on internal bus and peripherals. This happens on SAMA5D2 as exitting from the ROM code. Add a function pmc_mck_init_down() to allow this sequence. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: at91: spl: Adjust switching to oscillator for SAMA5D2Wenyou Yang2017-09-142-1/+19
| | | | | | | | | As said in 29.5.7 section of SAMA5D2 datasheet, before switching to the crystal oscillator, a check must be carried out to ensure that the oscillator is present and that its freqency is valid. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* atmel: common: Add function to display via DM_VIDEO's APIWenyou Yang2017-09-141-0/+1
| | | | | | | | | Add a function to display the company's logo and board information via the API from DM_VIDEO. This function can be shared by other atmel boards, so locate it in board/atmel/common folder. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: dts: at91: sama5: Add the sfr nodeWenyou Yang2017-09-142-0/+8
| | | | | | | | | | For sama5d2, add the sfr node with syscon support. In order to access the SFR_UTMICKTRIM register for the utmi clock driver, add the phandle property for the utmi node to point to the sfr node. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
* clk: at91: utmi: Set the reference clock frequencyWenyou Yang2017-09-141-0/+5
| | | | | | | | | | | | | | | | | | | By default, it is assumed that the UTMI clock is generated from a 12 MHz reference clock (MAINCK). If it's not the case, the FREQ field of the SFR_UTMICKTRIM has to be updated to generate the UTMI clock in the proper way. The UTMI clock has a fixed rate of 480 MHz. In fact, there is no multiplier we can configure. The multiplier is managed internally, depending on the reference clock frequency, to achieve the target of 480 MHz. The patch is cloned from the patch of mailing-list: [PATCH v2] clk: at91: utmi: set the mainck rate Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> [trini: Depend on SPL_DM] Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_EMIF4 et al to KconfigAdam Ford2017-09-131-0/+15
| | | | | | | | | | This converts the following to Kconfig: CONFIG_EMIF4 CONFIG_SDRC Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefano Babic <sbabic@denx.de>
* arm: dts: omap3: Re-sync DTS files with Linux 4.13-RC5Adam Ford2017-09-1313-3284/+3382
| | | | | | | | | | | | | | | | The DTS files had some spacing issues and they needed fixing. This pull re-sync's the OMAP3xx related DTS files with Linux 4.13-RC5. To keep the DTS and DTSI files clean and in sync with Linux, new u-boot.dtsi files are added. Signed-off-by: Adam Ford <aford173@gmail.com> V3: The resync broke card detect on MMC1 on Logic PD's Torpedo, so we add the cd-invert to the Torpedo's -u-boot.dtsi file. V2: Add the u-boot.dtsi files for OMAP3, OMAP36xx, and Torpedo Remove the need for the second patch in the series
* ARM: dts: ethernut5: Fix the build warningWenyou Yang2017-09-131-0/+2
| | | | | | | | | | | | Fix the building warning as below: ---8<---- Warning (reg_format): "reg" property in /i2c-gpio-0/pcf8563@50 has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) Warning (avoid_default_addr_size): Relying on default #address-cells value for /i2c-gpio-0/pcf8563@50 Warning (avoid_default_addr_size): Relying on default #size-cells value for /i2c-gpio-0/pcf8563@50 --->8---- Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA72x: Add support for detection of DRA71x SR 2.1Vishal Mahaveer2017-09-125-0/+9
| | | | | | | | | DRA71x processors are reduced pin and software compatible derivative of DRA72 processors. Add support for detection of SR2.1 version of DRA71x family of processors. Signed-off-by: Vishal Mahaveer <vishalm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* dma: import linux/dma-direction.h to consolidate enum dma_data_directionMasahiro Yamada2017-09-123-17/+5
| | | | | | | | Import include/linux/dma-direction.h from Linux 4.13-rc7 and delete duplicated definitions of enum dma_data_direction. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* armv8: mmu: add space around operatorAndy Yan2017-09-121-1/+1
| | | | | | | | | Add space around operator "+", make it match the coding style. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: mmu: remove unused macro definitionAndy Yan2017-09-121-9/+0
| | | | | | | | | Macro VA_BITS and PTE_BLOCK_BITS are not used in the code, so remove them. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-09-1227-164/+978
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| * armv8: fsl-layerscape: Add back L3 flushing for all exception levelsYork Sun2017-09-111-4/+0
| | | | | | | | | | | | | | | | | | CCN-504 HPF registers were believed to be accessible only from EL3. However, recent tests proved otherwise. Remove checking for exception level to re-enable L3 cache flushing for all levels. Signed-off-by: York Sun <york.sun@nxp.com> Tested-by: Zhao Qiang <qiang.zhao@nxp.com>
| * armv8: ls1088a: add PCIe dts nodeHou Zhiqiang2017-09-111-0/+48
| | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1088a: fix the MMU table for pcie config spaceHou Zhiqiang2017-09-111-0/+6
| | | | | | | | | | | | | | The pcie config space of ls1088a is different from ls2080a. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: Fix MC reserved memory calculationYork Sun2017-09-111-3/+12
| | | | | | | | | | | | | | | | | | In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com>
| * armv7: Add workaround for USB erratum A-009007Ran Wang2017-09-113-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rx Compliance tests may fail intermittently at high jitter frequencies using default register values Program register USB_PHY_RX_OVRD_IN_HI in certain sequence to make the Rx compliance test pass. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
| * armv7: Add workaround for USB erratum A-008997Ran Wang2017-09-113-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Low Frequency Periodic Singaling (LFPS) Peak-to-Peak Differential Output Voltage Test Compliance fails using default transmitter settings Change config of transmitter signal swings by setting register PCSTXSWINGFULL to 0x47 to pass compliance tests. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
| * armv7: Add workaround for USB erratum A-009798Ran Wang2017-09-113-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The default setting for USB High Speed Squelch Threshold results in a threshold close to or lower than 100mV. This leads to Receive Compliance test failure for a 100mV threshold. Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
| * armv7: Add workaround for USB erratum A-009008Ran Wang2017-09-113-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with the default value at many corners, particularly at a high temperature Optimal eye at TXREFTUNE value to 0x9 is observed, change set the same value. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: Add workaround for USB erratum A-009007Ran Wang2017-09-114-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rx Compliance tests may fail intermittently at high jitter frequencies using default register values. Program register USB_PHY_RX_OVRD_IN_HI in certain sequence to make the Rx compliance test pass. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: Add workaround for USB erratum A-008997Ran Wang2017-09-113-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Low Frequency Periodic Signaling(LFPS) Peak-to-Peak Differential Output Voltage Test Compliance fails using default transmitter settings Change config of transmitter signal swings by setting register PCSTXSWINGFULL to 0x47 to pass compliance tests. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: Add workaround for USB erratum A-009798Ran Wang2017-09-114-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The default setting for USB High Speed Squelch Threshold results in a threshold close to or lower than 100mV. This leads to Receiver Compliance test failure for a 100mV threshold. Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: Add workaround for USB erratum A-009008Ran Wang2017-09-114-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with the default value at many corners, particularly at a high temperature Optimal eye at TXREFTUNE value to 0x9 is observed, change set the same value. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: Add scfg_clrsetbits_32(), scfg_clrbits_32()Ran Wang2017-09-111-0/+4
| | | | | | | | | | | | | | Some erratum patch might need it to program registers. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: Support to add RGMII for ls1088aqdsAshish Kumar2017-09-114-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1088aqds: Add support of LS1088AQDSAshish Kumar2017-09-114-2/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch add support of LS1088AQDS platform. The LS1088A QorIQTM Development System (QDS) is a high-performance computing, evaluation, and development platform that supports the LS1088A QorIQ Architecture processor. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1088ardb: Add support for LS1088ARDB platformAshish Kumar2017-09-115-1/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1088A is an ARMv8 implementation. The LS1088ARDB is an evaluatoin platform that supports the LS1088A family SoCs. This patch add basic support of the platform. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> [YS: Disabled NAND in board header file] Reviewed-by: York Sun <york.sun@nxp.com> WIP: disable NAND for LS1088ARDB
| * armv8: ls1088a: Add NXP LS1088A SoC supportAshish Kumar2017-09-1113-11/+393
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1088A is compliant with the Layerscape Chassis Generation 3 with eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4 SDRAM memory controller with ECC, Data path acceleration architecture 2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs), QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> [YS: Revised commit message] Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: Fix final MMU table for QSPI and IFCSuresh Gupta2017-09-111-2/+4
| | | | | | | | | | | | | | | | | | For QSPI and IFC addresses execution shouldn't be allowed when u-boot running from DDR. Revise the MMU final table to enforce execute-never bits. Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl: Use correct conditional compile for ls1012aRan Wang2017-09-111-1/+1
| | | | | | | | | | | | | | | | | | | | According current code base, CONFIG_LS1012A should be CONFIG_ARCH_LS1012A, or function fsl_fdt_disable(blob) will be wrongly called to disable all dwc3 USB nodes on LS1012A, which cause Linux USB function stop working at all. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-lsch3: Make CCN-504 related code conditionalAshish Kumar2017-09-112-3/+9
| | | | | | | | | | | | | | | | | | | | LS2080 family has CCN-504 cache coherent interconnet. Other SoCs in LSCH3 family may have differnt interconnect. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message] Reviewed-by: York Sun <york.sun@nxp.com>
| * LS2080ARDB: QSPI boot: Secure Boot image validationUdit Agarwal2017-09-112-1/+7
| | | | | | | | | | | | | | | | | | | | Adds header address for PPA to be validated during ESBC phase for ARCH_LS2088 and QSPI_BOOT. Moves sec_init prior to ppa_init(). It must be initialized before the PPA. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> [YS: revised commit message] Reviewed-by: York Sun <york.sun@nxp.com>
| * SECURE_BOOT: Unify memory map for Layerscape based platformsSumit Garg2017-09-112-38/+28
| | | | | | | | | | | | | | | | | | | | Unify memory map for Layerscape based platforms. This patch includes changes in bootscript, bootscript header and PPA header addresses change as per unified memory map. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl-layerscape: Consolidate registers space defination for CCI-400 busAshish Kumar2017-09-118-101/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge git://git.denx.de/u-boot-dmTom Rini2017-09-123-10/+30
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| * | dm: test: replace dm_scan_dt() by of dm_extended_scan_fdt() in dm_do_testPatrice Chotard2017-09-111-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows to scan the DT including all "clocks" node's sub-nodes in which fixed-clock are defined. All fixed-clock should be defined inside a clocks node which collect all external oscillators. Until now, all clocks sub-nodes can't be binded except if the "simple-bus" compatible string is added which is a hack. Update test.dts by moving clk_fixed node inside clocks. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | dm: core: Add ofnode_for_each_subnode()Simon Glass2017-09-111-6/+2
| | | | | | | | | | | | | | | | | | | | | Add a convenience macro to iterate over subnodes of a node. Make use of this where appropriate in the code. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | sandbox: Convert SANDBOX_BITS_PER_LONG to KconfigBin Meng2017-09-111-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Convert SANDBOX_BITS_PER_LONG to Kconfig and assign it a correct number depending on which host we are going to build and run. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | sandbox: Introduce Kconfig option for 32/64 bit hostBin Meng2017-09-111-0/+17
| |/ | | | | | | | | | | | | | | It seems most of the time we are building and running sandbox on 64-bit host. But we do support 32-bit host as well. Introduce Kconfig option for this. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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