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* bootm: fix 'memory-fixup' for vxWorks bootHannes Schmelzer2018-05-101-1/+1
| | | | | | | The check for having a memory node within the fdt blob is made wrong, we fix this here. Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
* Merge git://git.denx.de/u-boot-sunxiTom Rini2018-05-097-168/+379
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| * board: sunxi: sun8i-v40: Add Bananapi M2 Berry supportJagan Teki2018-05-072-1/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Banana Pi BPI-M2 Berry is a quad-core mini single board computer built with Allwinner V40 SoC. It features - Quad Core ARM Cortex A7 CPU V40 - 1GB of RAM . - microSD/SATA port.. - onboard WiFi and BT - 4 USB A 2.0 ports - 1 USB OTG port - 1 HDMI port - 1 audio jack - DC power port Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
| * ARM: dts: sun8i: Sync r40 dtsi from LinuxJagan Teki2018-05-071-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | Sync sun8i-r40.dtsi changes from Linux with Merge: a406778618d0 088345fc3553 Author: Stephen Rothwell <sfr@canb.auug.org.au> Date: Tue Apr 24 14:15:02 2018 +1000 Merge branch 'akpm/master' Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: Sort dts Makefile entries for H3Chen-Yu Tsai2018-05-011-5/+5
| | | | | | | | | | | | | | | | | | The dts Makefile entries for the H3 are not ordered correctly. Move the Nano Pi entries before the Orange Pi so they are. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: Add Libre Computer Board ALL-H3-CC H5 ver.Chen-Yu Tsai2018-05-012-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a device tree file for the H5 version of the Libre Computer Board ALL-H3-CC. It is the same board first introduced in commit afe27544125e ("sunxi: Add support for Libre Computer Board ALL-H3-CC H3 ver."), with the H3 SoC replaced with the H5 SoC, and has 4Gb DDR3 chips instead of 2Gb ones. The device tree utilizes the common board design file for ALL-H3-CC, providing just the model strings and SoC specifics. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: Add Libre Computer Board ALL-H3-CC H2+ ver.Chen-Yu Tsai2018-05-012-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a device tree file for the H2+ version of the Libre Computer Board ALL-H3-CC. It is the same board first introduced in commit afe27544125e ("sunxi: Add support for Libre Computer Board ALL-H3-CC H3 ver."), with the H3 SoC replaced with the H2+ SoC, and has only two 2Gb DDR3 chips instead of four. The device tree utilizes the common board design file for ALL-H3-CC, providing just the model strings and SoC specifics. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: Split out common board design for ALL-H3-CC device treeChen-Yu Tsai2018-05-012-164/+170
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Libre Computer Project ALL-H3-CC has three models, all using the same board design, but with different pin compatible SoCs and amount of DRAM. Currently only the H3 1GB DRAM variant is supported. To support the two other variants, first split the original device tree into a common board design part and an SoC specific part. The SoC part only defines which SoC is used and model name, and includes the SoC specific dtsi file and the common design dtsi file. Also fix up the SPDX identifier line to use the correct comment style, and place it on the first line. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | arm: bitops: fix find_next_zero_bit() for case size < 32Grygorii Strashko2018-05-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | find_next_zero_bit() incorrectly handles cases when: - total bitmap size < 32 - rest of bits to process static inline int find_next_zero_bit(void *addr, int size, int offset) { unsigned long *p = ((unsigned long *)addr) + (offset >> 5); unsigned long result = offset & ~31UL; unsigned long tmp; if (offset >= size) return size; size -= result; offset &= 31UL; if (offset) { tmp = *(p++); tmp |= ~0UL >> (32-offset); if (size < 32) [1] goto found_first; if (~tmp) goto found_middle; size -= 32; result += 32; } while (size & ~31UL) { tmp = *(p++); if (~tmp) goto found_middle; result += 32; size -= 32; } [2] if (!size) return result; tmp = *p; found_first: [3] tmp |= ~0UL >> size; ^^^ algo can reach above line from from points: [1] offset > 0 and size < 32, tmp[offset-1..0] bits set to 1 [2] size < 32 - rest of bits to process in both cases bits to search are tmp[size-1..0], but line [3] will simply set all tmp[31-size..0] bits to 1 and ffz(tmp) below will fail. example: bitmap size = 16, offset = 0, bitmap is empty. code will go through the point [2], tmp = 0x0 after line [3] => tmp = 0xFFFF and ffz(tmp) will return 16. found_middle: return result + ffz(tmp); } Fix it by correctly seting tmp[31..size] bits to 1 in the above case [3]. Fixes: 81e9fe5a2988 ("arm: implement find_next_zero_bit function") Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
* | db410c: set clk node to be probed before relocationRamon Fried2018-05-082-1/+12
| | | | | | | | | | | | | | | | | | The clock node is used by the serial driver and it's needed before relocation. This patch ensures that the msm-serial driver can actually use the clock node. Signed-off-by: Ramon Fried <ramon.fried@linaro.org>
* | ARM: dts: sti: Add stih410-b2260-u-boot.dtsiPatrice Chotard2018-05-081-0/+16
| | | | | | | | | | | | | | | | | | | | | | STiH410 has 2 PHYs wired on the DWC3 IP, USB2 and USB3 PHYs. As currently no U-boot driver is available for the USB3 PHY and to avoid issue during DWC3 drive probe, we use DWC3 IP with only USB2 PHY using stih410-b2260-u-boot.dtsi file. Fixes: 2fd4242cc50e ("ubs: xhci-dwc3: Enable USB3 PHY when available") Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | ARM: dts: stm32mp157: Add vrefbuf DT nodePatrice Chotard2018-05-081-0/+9
| | | | | | | | | | | | | | Add vrefbuf device tree node. This allows to get a voltage reference for ADCs. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | ARM: dts: stm32mp157c-ed1: Add regulator nodePatrice Chotard2018-05-081-0/+272
| | | | | | | | | | | | | | | | | | Add regulator nodes needed by stpmu1 regulator driver Add vmmc-supply and vqmmc-supply regulator property for sdmmc1 and sdmmc2. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | ARM: dts: stm32mp157: Add SoC pwr regulator entryPatrice Chotard2018-05-081-0/+33
| | | | | | | | | | | | | | Add SoC power regulator entry for reg11, reg18 and usb33 regulator. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | stm32mp: regulator: add SoC pwr regulator supportPatrick Delaunay2018-05-084-0/+278
| | | | | | | | | | | | | | | | | | | | | | This driver binds and manages the following regulator of SoC's PWR block : - reg11 - reg18 - usb33 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | arm: controlcenterdc: Add spi-flash compatible stringsMario Six2018-05-081-2/+2
| | | | | | | | | | | | | | Since kirkwook SPI was recently converted to DM, add compatible strings to the SPI flash devices to make them work with the new driver. Signed-off-by: Mario Six <mario.six@gdsys.cc>
* | arm: dra76: fastboot: extend cpu type for getvar commandPraneeth Bajjuri2018-05-081-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'commit dda0bd674481 ("arm: dra762: Add support for device package identification")' introduces ABZ and ACD package identification. This patch is to extend usage of "fastboot getvar cpu" for DRA76x ABZ and ACD devices. Helps in fixing the boot warning. Warning: fastboot.cpu: unknown CPU rev: 123863298 on CPU : DRA762-GP ES1.0 ABZ package Model: TI AM5748 IDK Board: AM574x IDK REV 1.0A Signed-off-by: Praneeth Bajjuri <praneeth@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | gpio: atmel_pio4: give a full configuration when muxing pinsLudovic Desroches2018-05-081-8/+8
| | | | | | | | | | | | | | | | When a pin is muxed to a peripheral or as a GPIO, the only configuration that can be set is the pullup. It is too restrictive so this patch allows to give a full configuration. Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
* | gpio: atmel_pio4: add drive strength macrosLudovic Desroches2018-05-081-0/+4
| | | | | | | | | | | | Macros for drive strength configuration were missing. Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
* | ARM64: meson: Sync DT and Bindings with Linux 4.16Neil Armstrong2018-05-088-62/+567
| | | | | | | | | | | | Synchronize the Linux Device Tree for Amlogic Meson GX boards from Linux 4.16.0. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | ARM: meson: rename GXBB to GXNeil Armstrong2018-05-085-96/+96
| | | | | | | | | | | | | | Taking into account the Amlogic Family name starts with GX, including the GXBB, GXL and GXM SoCs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | dm: led: add testcase for "default-state" propertyPatrick Bruenn2018-05-081-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add two more gpio-leds to sandbox test device tree with default-state property set to "on"/"off". Add dm_test_led_default_state() to check that these new LED's are set to LEDST_ON and LEDST_OFF. dm: led: add testcase for "default-state" property Add two more gpio-leds to sandbox test device tree with default-state property set to "on"/"off". Add dm_test_led_default_state() to check that these new LED's are set to LEDST_ON and LEDST_OFF. Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
* | arm: v7R: Add support for enabling cachesLokesh Vutla2018-05-072-1/+22
| | | | | | | | | | | | | | | | | | | | Cache maintenance procedure is same for v7A and v7R processors. So re-use cache-cp15.c file except for mmu parts. Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm: v7R: Add support for MPULokesh Vutla2018-05-078-109/+257
| | | | | | | | | | | | | | | | | | | | | | | | | | The Memory Protection Unit(MPU) allows to partition memory into regions and set individual protection attributes for each region. In absence of MPU a default map[1] will take effect. Add support for configuring MPU on Cortex-R, by reusing the existing support for Cortex-M processor. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460d/I1002400.html Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm: v7R: Add initial supportMichal Simek2018-05-073-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Cortex-R* processors are a mid-range CPUs for use in deeply-embedded, real-time systems. It implements the ARMv7-R architecture, and includes Thumb-2 technology for optimum code density and processing throughput. Except for MPU(Memory Protection Unit) and few CP15 registers, most of the features are compatible with v7 architecture. So,reuse the same armv7 folder and introduce a new config CPU_V7R in order to differentiate from v7 based platforms. Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | arm: v7: Kconfig: Introduce SYS_ARM_CACHE_CP15Lokesh Vutla2018-05-072-5/+8
| | | | | | | | | | | | | | | | | | | | | | Certain ARM architectures like ARMv7-A, ARMv7-R has support for enabling caches using CP15 registers. To have a common support for all these architectures, introduce a Kconfig symbol SYS_ARM_CACHE_CP15 that selects cache-cp15.c Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | arm: v7: Kconfig: Add entry for MMULokesh Vutla2018-05-071-0/+15
| | | | | | | | | | | | | | | | | | | | Add a Kconfig entry for MMU and imply for all platforms using cache-cp15.c containing MMU setup. Using imply instead of select so that MMU can be disabled by defconfigs when not needed. Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | arm: v7: Kconfig: Rename CPU_V7 as CPU_V7ALokesh Vutla2018-05-0721-74/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently CPU_V7 kconfig symbol supports only ARMv7A architectures under armv7 folder. This led to a misconception of creating separate folders for armv7m and armv7r. There is no reason to create separate folder for other armv7 based architectures when it can co-exist with few Kconfig symbols. As a first step towards a common folder, rename CPU_V7 as CPUV7A. Later separate Kconfig symbols can be added for CPU_V7R and CPU_V7M and can co exist in the same folder. Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Suggested-by: Alexander Graf <agraf@suse.de> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | arm: v7: Update VBAR only if availableLokesh Vutla2018-05-071-0/+2
| | | | | | | | | | | | | | | | Not all ARM V7 based cpus has VBAR for remapping vector base address. So, update VBAR only if it available. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | test: regmap: test Linux-compatible syscon_node_to_regmap()Masahiro Yamada2018-05-071-0/+8
| | | | | | | | | | | | | | | | | | Like Linux, syscon_node_to_regmap() allows a node to work as a syscon provider without binding it to a syscon driver. Test this. Requested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | regmap: change regmap_init_mem() to take ofnode instead udeviceMasahiro Yamada2018-05-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Currently, regmap_init_mem() takes a udevice. This requires the node has already been associated with a device. It prevents syscon/regmap from behaving like those in Linux. Change the first argumenet to take a device node. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | regmap: clean up regmap allocationMasahiro Yamada2018-05-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Putting zero length array at the end of struct is a common technique to embed arbitrary length of members. There is no good reason to let regmap_alloc_count() branch by "if (count <= 1)". As far as I understood the code, regmap->base is an alias of regmap->ranges[0].start, but it is not helpful but make the code just ugly. Rename regmap_alloc_count() to regmap_alloc() because the _count suffix seems pointless. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: fixup cpu_info-rcar.c] Signed-off-by: Tom Rini <trini@konsulko.com>
* | psci: arm: remove armv7 function psci_save_target_pcPatrick Delaunay2018-05-072-9/+1
| | | | | | | | | | | | | | | | | | | | This function is no more used, and replaced by psci_save which save also context id as requested by PSCI requirements. Even if the context id is not used by Linux, it should be saved and restored in r0 when the CPU_ON is performed. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* | sunxi: psci: save context id in cpu_on commandPatrick Delaunay2018-05-071-3/+4
| | | | | | | | | | | | | | Replace the psci_save_target_pc call by the new function psci_save(cpu, pc,context_id) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* | uniphier: psci: save context id in cpu_on commandPatrick Delaunay2018-05-071-2/+5
| | | | | | | | | | | | | | | | Replace the psci_save_target_pc call by the new function psci_save(cpu, pc,context_id) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | tegra: psci: save context id in cpu_on commandPatrick Delaunay2018-05-071-1/+2
| | | | | | | | | | | | | | | | Replace the psci_save_target_pc call by the new function psci_save(cpu, pc,context_id) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* | imx7: psci: save context id in cpu_on commandPatrick Delaunay2018-05-071-1/+2
| | | | | | | | | | | | | | Replace the psci_save_target_pc call by the new function psci_save(cpu, pc,context_id) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* | ls102xa: psci: save context id in cpu_on commandPatrick Delaunay2018-05-071-1/+2
| | | | | | | | | | | | | | Replace the psci_save_target_pc call by the new function psci_save(cpu, pc,context_id) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* | arm: stm32mp1: add PSCI supportPatrick Delaunay2018-05-074-0/+186
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PSCI v1.0 support for Linux and manage PSCI state for each CPU (affinity 0 level) with all mandatory functions: - PSCI_VERSION - CPU_SUSPEND - CPU_OFF - CPU_ON - AFFINITY_INFO - SYSTEM_OFF - SYSTEM_RESET - PSCI_FEATURES and 1 optional to avoid Linux warning - MIGRATE_INFO_TYPE Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
* | arm: psci: add a weak function psci_arch_cpu_entryPatrick Delaunay2018-05-071-0/+7
| | | | | | | | | | | | | | | | | | | | The added function psci_arch_cpu_entry() is called during psci_cpu_entry() and can be used by arch to handle PSCI state transition from ON_PENDING to ON. The default weak function is empty: not behavior change. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* | arm: psci: save context id for cpu_on PSCI commandPatrick Delaunay2018-05-073-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Save and use the 3rd parameter of PSCI CPU_ON request: context_id. The context_id parameter is only meaningful to the caller. U-Boot PSCI preserves a copy of the value passed in this parameter. Following wakeup from a powerdown state, U-BOOT PSCI places this value in R0 when it first enters the OS. NB: this context id is not (yet?) used by Linux but it is mandatory to be PSCI compliant. update armv7 psci functions: - psci_save_target_pc(): keep for backward compatibility with current platform (only save PC and force context id to 0) => should be removed when all platform migrate to the new API - psci_save(): new API to use by ARMv7 platform with PSCI, save pc (= entry_point_address) and context_id Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | SPDX: Convert all of our multiple license tags to Linux Kernel styleTom Rini2018-05-0789-177/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have multiple licenses (in these cases, dual license) declared in the SPDX-License-Identifier tag. In this case we change from listing "LICENSE-A LICENSE-B" or "LICENSE-A or LICENSE-B" or "(LICENSE-A OR LICENSE-B)" to "LICENSE-A OR LICENSE-B" as per the Linux Kernel style document. Note that parenthesis are allowed so when they were used before we continue to use them. Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* | SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini2018-05-072823-5871/+2844
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
* | arm: mach-omap2: cache: Explicitly enable I cacheLokesh Vutla2018-05-061-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | omap-common cache enabling sequence relies on cpu_init_cp15() (inside start.S) for enabling I-caches. But cpu_init_cp15() can be skipped if CONFIG_SKIP_LOWLEVEL_INIT is defined. So enable I-caches if not enabled already. Debugged-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Tested-by: Steve Kipisz <s-kipisz2@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: rmobile: Contain CONFIG_ARCH_RMOBILE_BOARD_STRINGMarek Vasut2018-05-022-8/+2
| | | | | | | | | | | | | | | | | | | | Pull the symbol from the boards and zap struct rmobile_sysinfo as they are rather useless. The entire purpose of that whole machinery was to print board name in the CONFIG_ARCH_RMOBILE_BOARD_STRING. Do that in a far simpler and more contained manner. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | ARM: rmobile: Convert CONFIG_ARCH_RMOBILE_BOARD_STRING to KconfigMarek Vasut2018-05-021-0/+4
|/ | | | | | | Convert the symbol to Kconfig, no functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Merge git://git.denx.de/u-boot-imxTom Rini2018-04-3016-61/+51
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| * ARM: mxs: support full SPL frameworkMans Rullgard2018-04-275-3/+16
| | | | | | | | | | | | | | | | This allows using the full SPL framework on mxs devices. In this mode, the u-boot.sb image loaded by the boot ROM contains only the SPL which then loads U-Boot proper or a kernel in falcon mode. Signed-off-by: Mans Rullgard <mans@mansr.com>
| * ARM: mxs: move spl dataMans Rullgard2018-04-273-6/+5
| | | | | | | | | | | | | | With full SPL enabled, the loaded image overwrites the mxs_spl_data location. Moving it a slightly lower address fixes this. Signed-off-by: Mans Rullgard <mans@mansr.com>
| * ARM: spl: include arm/thumb glue sectionsMans Rullgard2018-04-271-0/+1
| | | | | | | | | | | | | | When building in Thumb mode, the linker might generate mode switching stubs in .glue sections. Include these in the final link. Signed-off-by: Mans Rullgard <mans@mansr.com>
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