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* global: Move remaining CONFIG_SYS_NOR_* to CFG_SYS_NOR_*Tom Rini2022-12-054-77/+77
| | | | | | | | | | The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NOR namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* global: Move remaining CONFIG_SYS_NAND_* to CFG_SYS_NAND_*Tom Rini2022-12-0543-153/+153
| | | | | | | | | | The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NAND namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* xilinx: zynqmp: Fix SPL_FS_LOAD_PAYLOAD_NAME usageMichal Simek2022-12-051-21/+24
| | | | | | | | | | | SPL_FS_LOAD_PAYLOAD_NAME depends on SPL to be enabled. If SPL is not enabled code still expects SPL_FS_LOAD_PAYLOAD_NAME to be present. That's why setup proper dependency in the code. And by doing so also change the logic around dfu_alt_info string composition to be simpler. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/3989c390a4acae13a1b05c040e14fb3d68bced02.1669986373.git.michal.simek@amd.com
* arm64: zynqmp: Do not include psu_init to U-Boot by defaultMichal Simek2022-12-051-5/+1
| | | | | | | | | | | | | | | | | | | The commit ed35de617013 ("Convert CONFIG_ZYNQMP_PSU_INIT_ENABLED to Kconfig") converted CONFIG_ZYNQMP_PSU_INIT_ENABLED symbol and enabled it by default which is not correct configuration. Intention of this config was to have it enabled by default for SPL and provide an option to users to also do low level initialization directly from U-Boot. That's why it is necessary to define second symbol with SPL marking in it and properly use symbols depends on usage in Makefile. Also disable ZYNQMP_PSU_INIT_ENABLED from boards which enables it by default. CONFIG_SPL_ZYNQMP_PSU_INIT_ENABLED is enabled by default when SPL is enabled. Reported-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/d5fcbd66b05bf0d7ef594e66464ee23b48c5e4cc.1669969083.git.michal.simek@amd.com
* board/xilinx/zynqmp/MAINTAINERS: change e-mail address for Luca CeresoliLuca Ceresoli2022-12-051-1/+1
| | | | | | | | | My Bootlin address is the preferred one now. Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Link: https://lore.kernel.org/r/20221203214939.56608-1-luca@lucaceresoli.net Signed-off-by: Michal Simek <michal.simek@amd.com>
* xilinx: Remove unused ZYNQ_MAC_IN_EEPROM/ZYNQ_GEM_I2C_MAC_OFFSET entriesMichal Simek2022-12-051-17/+0
| | | | | | | | | | The commit ba74bcf3e07b ("xilinx: common: Remove zynq_board_read_rom_ethaddr()") removed zynq_board_read_rom_ethaddr() because xlnx,eeprom link via DT chosen node is no longer used. But forget to remove Kconfig entries which are used by this code only. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/f97451ed33409838efea4071553b6da795cfc578.1669192026.git.michal.simek@amd.com
* xilinx: Add option to select SC id instead of DUT id for SC supportMichal Simek2022-12-053-1/+15
| | | | | | | | Reading MAC address from on board EEPROM requires different type for System Controller (SC). Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/90bb7cc5463568a690b979f18c8d42556986b46d.1669204122.git.michal.simek@amd.com
* MAINTAINERS: add RaspberryPi co-maintainerMatthias Brugger2022-12-021-0/+1
| | | | | | | | Peter accpeted to step up as a co-maintainer for the RPis. Reflect that in the corresponding MAINTAINERS files. Signed-off-by: Matthias Brugger <mbrugger@suse.com> Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
* sandbox: Move the capsule GUID declarations to board fileSughosh Ganu2022-11-221-0/+13
| | | | | | | | | The sandbox config file is to be removed. Move the GUID declarations needed for capsule update functionality to the board file where they are used. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm64: zynqmp: Create vck190 spl link for revBMichal Simek2022-11-221-0/+1
| | | | | | | vck190 system controller low level setup is the same for revB that's why also create symlink to revA. Signed-off-by: Michal Simek <michal.simek@amd.com>
* xilinx: common: Remove zynq_board_read_rom_ethaddr()Venkatesh Yadav Abbarapu2022-11-221-28/+0
| | | | | | | | | | Removing the zynq_board_read_rom_ethaddr() function as xlnx,eeprom is not used anymore. As all board dts to use nvmem alias instead of xlnx,eeprom. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20221017094818.17996-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
* Fix usage of CONFIG_PREBOOTPali Rohár2022-11-211-2/+2
| | | | | | | | | | | | | | | Due to usage of PREBOOT in Kconfig, macro CONFIG_PREBOOT is always defined when CONFIG_USE_PREBOOT is enabled. In case CONFIG_PREBOOT is not explicitly enabled it is set to empty C string and therefore '#ifdef CONFIG_PREBOOT' guard does not work. Fix this issue by introducing a new Kconfig symbol PREBOOT_DEFINED which cause to define new C macro CONFIG_PREBOOT_DEFINED only when CONFIG_PREBOOT is really defined. Change usage of '#ifdef CONFIG_PREBOOT' by '#ifdef CONFIG_USE_PREBOOT' for code which checks if preboot code would be called and by '#ifdef CONFIG_PREBOOT_DEFINED' for defining preboot code. Signed-off-by: Pali Rohár <pali@kernel.org>
* Merge tag 'u-boot-imx-20221114' of ↵Tom Rini2022-11-1416-29/+2290
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx For 2022.01 ----------- CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14083 - Fix UART - moved to binman (MX8 boards) - Toradex: sync DTS with Linux - Gateworks: fixes - New boards : MSC SM2S iMX8MP
| * imx: imx8qxp: giedi switch to binmanOliver Graute2022-11-091-1/+1
| | | | | | | | | | | | Switch to use binman to pack images Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
| * imx: imx8qm: imx8qm_mek switch to binmanOliver Graute2022-11-091-1/+1
| | | | | | | | | | | | Switch to use binman to pack images Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
| * imx: imx8qxp: imx8qxp_mek switch to binmanOliver Graute2022-11-091-2/+1
| | | | | | | | | | | | | | Switch to use binman pack images Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
| * imx: imx8qm: cgtqmx8: switch to binmanOliver Graute2022-11-091-2/+2
| | | | | | | | | | | | | | | | | | Switch to use binman to pack images Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com> Reviewed-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Peng Fan <peng.fan@nxp.com>
| * imx: imx8qm-rom7720: switch to binmanOliver Graute2022-11-091-2/+2
| | | | | | | | | | | | Switch to use binman to pack images Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
| * imx: imx8m{m,n,p}_venice: migrate to CONFIG_EXTRA_ENV_TEXTTim Harvey2022-11-081-0/+34
| | | | | | | | | | | | | | Move the majority of the environment from the board headers to a separate text file. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * board: gateworks: venice: remove redundance adjustment of thermal trip pointsTim Harvey2022-11-081-16/+0
| | | | | | | | | | | | | | | | commit 0543a1ed2787 ("imx8m: fixup thermal trips") moved updating the thermal trip points to all IMX8M so we can remove it from our board specific dt config. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * mx6cuboxi: migrate to DM_SERIALBaruch Siach2022-11-081-0/+3
| | | | | | | | | | | | | | | | | | Add the needed DT overrides to enable UART in SPL. Cc: Fabio Estevam <festevam@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Tested-by: Tom Rini <trini@konsulko.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
| * arm: imx8mp: Initial MSC SM2S iMX8MP supportMartyn Welch2022-11-086-0/+2209
| | | | | | | | | | | | | | | | Add support for the MSC SM2S-IMX8PLUS SMARC Module. Tested in conjunction with the MSC SM2-MB-EP1 Mini-ITX Carrier Board. Signed-off-by: Martyn Welch <martyn.welch@collabora.com> Signed-off-by: Fabio Estevam <festevam@denx.de>
| * imx: imx8mm-beacon: Enable USB booting via SDPAdam Ford2022-11-071-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | In order to boot over USB, the device tree needs to enable a few extra nodes in SPL. Since the USB driver has the ability to detect host/device, the dr_mode can be removed from the device tree since it needs to act as a device when booting and OTG is the default mode. Add USB boot support to spl_board_boot_device and enable the corresponding config options. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
| * imx: imx8mm_beacon: Eliminate a few extras to free up SPL spaceAdam Ford2022-11-071-5/+0
| | | | | | | | | | | | | | | | | | There are a few functions which are not essential for use in SPL, but they take up enough space to make other preferred features not fit. Remove the extras. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
| * imx: imx8mn-beacon: Fix out of spec voltageAdam Ford2022-11-071-0/+35
| | | | | | | | | | | | | | | | | | | | The DDR is configured for LPDDR4 running at 1.6GHz which requires the voltage on the PMIC to rise a bit before initializing LPDDR4 or it will be running out of spec. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* | global: Migrate CONFIG_HPS* symbols to the CFG namespaceTom Rini2022-11-1042-1997/+1997
| | | | | | | | | | | | | | Migrate all of CONFIG_HPS* to the CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespaceTom Rini2022-11-1060-121/+121
| | | | | | | | | | | | | | Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | global: Migrate CONFIG_SYS_MPC8* symbols to the CFG_SYS namespaceTom Rini2022-11-1028-56/+56
| | | | | | | | | | | | Migrate all of COFIG_SYS_MPC* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com>
* | Convert CONFIG_SYS_I2C_INIT_BOARD to KconfigTom Rini2022-11-103-14/+3
|/ | | | | | | | This converts the following to Kconfig: CONFIG_SYS_I2C_INIT_BOARD Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: mvebu: Add RD-AC5X boardChris Packham2022-11-073-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RD-AC5X-32G16HVG6HLG-A0 development board main components and features include: * Main 12V/54V power supply * 270 Gbps throughput packet processor on the main board * DDR4: * SR1: 2GB DDR4 2400MT/S(1GB x 2 pcs ) with ECC(1GB x 1 pcs) * SR2: 4GB DDR4 2400MT/S(2GB x 2 pcs ) with ECC(2GB x 1 pcs) * PCB co-layout with 4GB device to support 8GB (Dual CS) requirement * 16GB eMMC (Samsung KLMAG1JETD-B041006) * 16MB SPI NOR(GD25Q127C) * 32 x 1000 Base-T interfaces * 16 x 2500 Base-T interfaces * SR1: 88E2540*4 * SR2: 88E2580*1+88E2540*2 * Six (6) x 25G Base-R SFP28 interfaces * One (1) x RJ-45 console connector, interfacing to the on board UART * One (1) x USB Type-A connector, interfacing to the USB 2.0 port (0) * One (1) x USB Type-mini B connector, interfacing to the USB 2.0 port (1) * One (1) x RJ-45 1G Base-T Management port, interfacing to the host port (shared with PCIe) Connected to 88E1512 Gigabit Ethernet Phy * One (1) x Oculink port, interfacing to the PCIe port for external CPU connection * POE 802.3AT support on Port 1 ~ Port 32, 802.3BT support on Port 33 ~ Port 48 (Microsemi PD69208T4, PD69208M or TI TPS2388,TPS23881 solution) * POE total power budget 780W * LED interfaces per network port/POE * LED interfaces (common) showing system status * PTP TC mode Supported (Reserved M.2 connector to support BC mode) Signed-off-by: Chris Packham <judge.packham@gmail.com>
* Makefile: Rename u-boot-spl.kwb to u-boot-with-spl.kwbPali Rohár2022-11-073-10/+10
| | | | | | | | | | | | | | File name with pattern u-boot-spl* is used on all places except in kwb image for binary with SPL-only code. Combined binary with both SPL and proper U-Boot in other places has file name pattern u-boot-with-spl*. Make it consistent also for kwb image and rename u-boot-spl.kwb to u-boot-with-spl.kwb as this image contains both SPL and proper U-Boot code. Also update documentation about file name changes. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
* Merge tag 'mips-pull-2022-11-03' of ↵Tom Rini2022-11-031-4/+0
|\ | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-mips - MIPS: convert CONFIG_SYS_MIPS_TIMER_FREQ to Kconfig - MIPS: mtmips: fix incorrectly converted default value for CONFIG_SPL_PAD_TO
| * MIPS: remove CONFIG_SYS_MHZDaniel Schwierzeck2022-11-021-4/+0
| | | | | | | | | | | | | | | | | | Resolve all uses of CONFIG_SYS_MHZ with the currently defined value. Remove code which depends on CONFIG_SYS_MHZ but where no board configs actually use that code. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
* | Merge branch '2022-11-02-assorted-updates'Tom Rini2022-11-033-2/+47
|\ \ | | | | | | | | | | | | | | | | | | - Improve arm semihosting, NPCM8xx pinctrl driver, SP804 uclass timer driver (and enable on relevant platforms), pvblock cleanup, eeprom cmd bugfix, add RTI watchdog nodes to k3-am64-main, evb-ast2500 config updates.
| * | treewide: Remove the unnecessary space before semicolonBin Meng2022-11-021-1/+1
| | | | | | | | | | | | | | | | | | %s/return ;/return; Signed-off-by: Bin Meng <bmeng@tinylab.org>
| * | highbank: scan into hb_sregs DT subnodesAndre Przywara2022-11-022-1/+46
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DT used for Calxeda Highbank and Midway systems exposes a "system registers" block, modeled as a DT subnode. This includes several clocks, including the two fixed clocks for the main oscillator and timer. So far U-Boot was ignorant of this special construct (a "clocks" node within the "hb-sregs" node), as it didn't need the PLL clocks in there. But that also meant we lost the fixed clocks, which form the base for the UART baudrate generator and also the SP804 timer. To allow the generic PL011 and SP804 driver to read the clock rate, add a simple bus driver, which triggers the DT node discovery inside this special node. As we only care about the fixed clocks (we don't have drivers for the PLLs anyway), just ignore the address translation (for now). The binding is described in bindings/arm/calxeda/hb-sregs.yaml, the DT snippet in question looks like: ======================= sregs@fff3c000 { compatible = "calxeda,hb-sregs"; reg = <0xfff3c000 0x1000>; clocks { #address-cells = <1>; #size-cells = <0>; osc: oscillator { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <33333000>; }; .... }; }; ======================= Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | riscv: Update Microchip MPFS Icicle Kit supportPadmarao Begari2022-11-031-0/+7
|/ | | | | | | | | | | This patch updates Microchip MPFS Icicle Kit support. For now, add Microchip QSPI driver and a small 4MB reservation is made at the end of 32-bit DDR to provide some memory for the HSS to use. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rick Chen <rick@andestech.com>
* test: dm: Add test cases for FWU Metadata uclassSughosh Ganu2022-10-311-0/+8
| | | | | | | | | | | | | | Add test cases for accessing the FWU Metadata on the sandbox platform. The sandbox platform also uses the metadata access driver for GPT partitioned block devices. The FWU feature will be tested on the sandbox64 variant with a raw capsule. Remove the FIT capsule testing from sandbox64 defconfig -- the FIT capsule test will be run on the sandbox_flattree variant. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
* FWU: STM32MP1: Add support to read boot index from backup registerSughosh Ganu2022-10-311-0/+21
| | | | | | | | | | | | | | | The FWU Multi Bank Update feature allows the platform to boot the firmware images from one of the partitions(banks). The first stage bootloader(fsbl) passes the value of the boot index, i.e. the bank from which the firmware images were booted from to U-Boot. On the STM32MP157C-DK2 board, this value is passed through one of the SoC's backup register. Add a function to read the boot index value from the backup register. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
* stm32mp1: Add image information for capsule updatesSughosh Ganu2022-10-311-0/+18
| | | | | | | | | | | Enabling capsule update functionality on the platform requires populating information on the images that are to be updated using the functionality. Do so for the DK2 board. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
* Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASESimon Glass2022-10-3161-70/+70
| | | | | | | | | The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE and this makes it imposible to use CONFIG_VAL(). Rename it to resolve this problem. Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: bcmbca: remove bcm6753 support under CONFIG_ARCH_BCM6753William Zhang2022-10-314-65/+0
| | | | | | | | | | | | | | | | | | BCM6753 is essentially same as the main chip BCM6855 but with different SKU number. Now that BCM6855 is supported under CONFIG_ARCH_BCMBCA and CONFIG_BCM6855, remove the original ARCH_BCM6753 support and migrate its configuration and dts settings. This includes: - Remove the bcm96753ref board folder. It is replaced by the generic bcmbca board folder. - Merge the 6753.dtsi setting to the new 6855.dtsi file. Update 96753ref board dts with the new compatible string. - Delete broadcom_bcm96763ref.h and merge its setting to the new bcm96855.h file. - Delete bcm96753ref_ram_defconfig and use a basic config version of bcm96855_defconfig Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
* arm: bcmbca: add bcm6855 SoC support under CONFIG_ARCH_BCMBCAWilliam Zhang2022-10-311-0/+7
| | | | | | | | | | | | | | | | | BCM6855 is a Broadcom ARM A7 based PON Gateway SoC. It is part of the BCA (Broadband Carrier Access origin) chipset family. Like other broadband SoC, this patch adds it under CONFIG_BCM6855 chip config and CONFIG_ARCH_BCMBCA platform config. This initial support includes a bare-bone implementation and dts with CPU subsystem, memory and ARM PL101 uart. This SoC is supported in the linux-next git repository so the dts and dtsi files are copied from linux. The u-boot image can be loaded from flash or network to the entry point address in the memory and boot from there to the console. Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
* arm: bcmbca: remove bcm6858 support under CONFIG_ARCH_BCM6858William Zhang2022-10-314-88/+0
| | | | | | | | | | | | | | | | Now that BCM6858 is supported under CONFIG_ARCH_BCMBCA and CONFIG_BCM6858, remove the original ARCH_BCM6858 support and migrate its configuration and dts settings. This includes: - Remove the bcm968580xref board folder. It is replaced by the generic bcmbca board folder. - Update bcm968580xref board dts with the new compatible string. - Delete broadcom_bcm968580xref.h and merge its setting to the new bcm96858.h file. - Remove bcm968580xref_ram_defconfig as a basic config version of bcm96858_defconfig is now added. Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
* arm: bcmbca: add bcm6858 SoC support under CONFIG_ARCH_BCMBCAWilliam Zhang2022-10-311-0/+7
| | | | | | | | | | | | | | | | BCM6858 is a Broadcom B53 based PON Gateway SoC. It is part of the BCA (Broadband Carrier Access origin) chipset family. Like other broadband SoC, this patch adds it under CONFIG_BCM6858 chip config and CONFIG_ARCH_BCMBCA platform config. This initial support includes a bare-bone implementation and the original dts is updated with the one from linux next git repository. The u-boot image can be loaded from flash or network to the entry point address in the memory and boot from there to the console. Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
* arm: bcmbca: remove bcm68360 support under CONFIG_ARCH_BCM68360William Zhang2022-10-314-88/+0
| | | | | | | | | | | | | | | | | BCM68360 is a variant within the BCM6856 chip family. Now that BCM6856 is supported under CONFIG_ARCH_BCMBCA and CONFIG_BCM6856, remove the original ARCH_BCM68360 support and migrate its configuration and dts settings. This includes: - Remove the bcm968360bg board folder. It is replaced by the generic bcmbca board folder. - Merge the 68360.dtsi setting to the new 6856.dtsi file. Update board dts with the new compatible string. - Merge broadcom_bcm968360bg.h setting to the new bcm96856.h file. - Remove bcm968360bg_ram_defconfig as a basic config version of bcm96856_defconfig is now added. Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
* arm: bcmbca: add bcm6856 SoC support under CONFIG_ARCH_BCMBCAWilliam Zhang2022-10-311-0/+7
| | | | | | | | | | | | | | | | | | BCM6856 is a Broadcom B53 based PON Gateway SoC. It is part of the BCA (Broadband Carrier Access origin) chipset family. Like other Broadband SoC, this patch adds it under CONFIG_BCM6856 chip config and CONFIG_ARCH_BCMBCA platform config. This initial support includes a bare-bone implementation and dts with CPU subsystem, memory and Broadcom uart. This SoC is supported in the linux-next git repository so the dts and dtsi files are copied from linux. The u-boot image can be loaded from flash or network to the entry point address in the memory and boot from there to the console. Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
* arm: bcmbca: make reset_cpu function weakWilliam Zhang2022-10-311-1/+1
| | | | | | | | | BCM63158 carries the CONFIG_SYSRESET from the original configuration. It provide reset_cpu function already so need to define weak version of the dummy reset_cpu for other BCMBCA SoCs to avoid linking error. Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
* arm: bcmbca: remove bcm63158 support under CONFIG_ARCH_BCM63158William Zhang2022-10-314-88/+0
| | | | | | | | | Now that BCM63158 is supported under CONFIG_ARCH_BCMBCA and CONFIG_BCM63158, remove the original ARCH_BCM63158 support and migrate configuration settings. Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
* arm: bcmbca: add bcm63158 SoC support under CONFIG_ARCH_BCMBCAWilliam Zhang2022-10-311-0/+7
| | | | | | | | | | | | | | | | | | BCM63158 is a Broadcom B53 based DSL Gateway SoC. It is part of the BCA (Broadband Carrier Access origin) chipset family. Like other Broadband SoC, this patch adds it under CONFIG_BCM63158 chip config and CONFIG_ARCH_BCMBCA platform config. This initial support includes a bare-bone implementation and dts with CPU subsystem, memory and ARM PL011 uart. This SoC is supported in the linux-next git repository so the dts and dtsi files are copied from linux. The u-boot image can be loaded from flash or network to the entry point address in the memory and boot from there to the console. Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
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