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* Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into nextWIP/05Jan2021-nextTom Rini2021-01-0516-20/+20
|\ | | | | | | | | | | | | | | | | Driver model: make some udevice fields private Driver model: Rename U_BOOT_DEVICE et al. dtoc: Tidy up and add more tests ns16550 code clean-up x86 and sandbox minor fixes for of-platdata dtoc prepration for adding build-time instantiation
| * dm: Rename DM_GET_DRIVER() to DM_DRIVER_GET()Simon Glass2021-01-0515-17/+17
| | | | | | | | | | | | | | | | In the spirit of using the same base name for all of these related macros, rename this to have the operation at the end. This is not widely used so the impact is fairly small. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: core: Access device ofnode through functionsSimon Glass2021-01-052-2/+2
| | | | | | | | | | | | | | | | At present ofnode is present in the device even if it is never used. With of-platdata this field is not used, so can be removed. In preparation for this, change the access to go through inline functions. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: core: Access device flags through functionsSimon Glass2021-01-051-1/+1
| | | | | | | | | | | | | | At present flags are stored as part of the device. In preparation for storing them separately, change the access to go through inline functions. Signed-off-by: Simon Glass <sjg@chromium.org>
| * spi: Tidy up get/set of device nodeSimon Glass2021-01-051-1/+1
| | | | | | | | | | | | | | | | This code is a bit odd in that it only reads and updates the livetree version of the device ofnode. This means it won't work with flattree. Update the code to work as it was presumably intended. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Merge tag 'v2021.01-rc5' into nextTom Rini2021-01-052-17/+17
|\ \ | |/ |/| | | | | | | Prepare v2021.01-rc5 Signed-off-by: Tom Rini <trini@konsulko.com>
| * mtd: spinand: enable erasing of bad mtd blocksMikhail Kshevetskiy2020-12-181-1/+9
| | | | | | | | | | | | | | | | U-Boot is able to erase bad mtd blocks on raw nand devices, but this is not true for spinand flashes. Lets enable this feature for spinand flashes as well. This is extemelly useful for flash testing. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@oktetlabs.ru>
| * mtd: spinand: Do not erase the block before writing a bad block markerFrieder Schrempf2020-12-181-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently when marking a block, we use spinand_erase_op() to erase the block before writing the marker to the OOB area. Doing so without waiting for the operation to finish can lead to the marking failing silently and no bad block marker being written to the flash. In fact we don't need to do an erase at all before writing the BBM. The ECC is disabled for raw accesses to the OOB data and we don't need to work around any issues with chips reporting ECC errors as it is known to be the case for raw NAND. Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs") Cc: stable@vger.kernel.org Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-4-frieder.schrempf@kontron.de
| * mtd: spinand: Explicitly use MTD_OPS_RAW to write the bad block marker to OOBFrieder Schrempf2020-12-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When writing the bad block marker to the OOB area the access mode should be set to MTD_OPS_RAW as it is done for reading the marker. Currently this only works because req.mode is initialized to MTD_OPS_PLACE_OOB (0) and spinand_write_to_cache_op() checks for req.mode != MTD_OPS_AUTO_OOB. Fix this by explicitly setting req.mode to MTD_OPS_RAW. Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs") Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-3-frieder.schrempf@kontron.de
| * mtd: spinand: Stop using spinand->oobbuf for buffering bad block markersFrieder Schrempf2020-12-181-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For reading and writing the bad block markers, spinand->oobbuf is currently used as a buffer for the marker bytes. During the underlying read and write operations to actually get/set the content of the OOB area, the content of spinand->oobbuf is reused and changed by accessing it through spinand->oobbuf and/or spinand->databuf. This is a flaw in the original design of the SPI NAND core and at the latest from 13c15e07eedf ("mtd: spinand: Handle the case where PROGRAM LOAD does not reset the cache") on, it results in not having the bad block marker written at all, as the spinand->oobbuf is cleared to 0xff after setting the marker bytes to zero. To fix it, we now just store the two bytes for the marker on the stack and let the read/write operations copy it from/to the page buffer later. Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs") Cc: stable@vger.kernel.org Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-2-frieder.schrempf@kontron.de
* | dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass2020-12-131-2/+2
| | | | | | | | | | | | | | This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass2020-12-1317-18/+18
|/ | | | | | | | | | | | This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
* mtd: nand: pxa3xx: enable NAND controller if the SoC needs itShmuel Hazan2020-10-292-10/+44
| | | | | | | | | | | | | | | | | Based on Linux kernel commit fc256f5789cb ("mtd: nand: pxa3xx: enable NAND controller if the SoC needs it"). This commit adds support for the Armada 8040 nand controller. The kernel commit says this: Marvell recent SoCs like A7k/A8k do not boot with NAND flash controller activated by default. Enabling the controller is a matter of writing in a system controller register that may also be used for other NAND related choices. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Shmuel Hazan <shmuel.h@siklu.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
* mtd: pxa3xx_nand: remove dead codeBaruch Siach2020-10-291-9/+3
| | | | | | | | The kfree() call is unreachable, and is not needed. Remove this call and the fail_disable_clk label. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
* mtd: pxa3xx_nand: port to use driver modelShmuel Hazan2020-10-292-63/+54
| | | | | | | | | | Use the generic DT code to find the device compatible property for us. This makes the driver look more like other current drivers. It also make it easier to add support for other variants like Armada 8K in a future commit. Signed-off-by: Shmuel Hazan <shmuel.h@siklu.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
* mtd: mxs_nand: Fix not calling dev_xxx with a deviceSean Anderson2020-10-151-13/+15
| | | | | | This includes device_compat.h, and fixes several calls to dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* mtd: nand: Add NAND controller driver for OcteonTXSuneel Garapati2020-10-146-0/+2998
| | | | | | | | | | Adds support for NAND controllers found on OcteonTX or OcteonTX2 SoC platforms. Also includes driver to support Hardware ECC using BCH HW engine found on these platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* nand: vybrid: Re-introduce vf610_nfc.devSean Anderson2020-09-301-17/+21
| | | | | | | | | | | | This member was presumably dropped when this driver was converted from Linux. However, it is still used in log statements during initialization. This patch adds the member back. In addition, allocation of struct vf610_nfc has been moved to the callers of vf610_nfc_nand_init. This allows it to be allocated by DM (if it is being used) and for dev to be initialized. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
* nand: brcmnand: Fix not calling dev_err() with a deviceSean Anderson2020-09-301-14/+6
| | | | | | | | | | There are too many levels of indirection when calling dev_err. This is an artifact of the conversion of brcmnand_host.pdev from a struct platform_device (which has a member `dev` pointing to a struct device) to struct udevice. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
* nand: atmel: Fix not calling dev_xxx with a deviceSean Anderson2020-09-301-30/+39
| | | | | | | | Use mtd_info to get a device to log with. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
* mtd: spi-nand: Fix not calling dev_err with a deviceSean Anderson2020-09-301-4/+4
| | | | | | | | | Get it from spinand->slave->dev. Another option would be to use spinand_to_mtd(spinand)->dev, but this is what the existing code uses. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
* mtd: nand: sunxi: Fix not calling dev_err with a deviceSean Anderson2020-09-301-22/+23
| | | | | | | | | | | | Usually the device is gotten from sunxi_nfc. This is a struct device and not a struct udevice, but the whole driver seems to be written wihout DM anyway... In a few instances, this patch modifies functions to take an nfc to log with. In once instance we use mtd_info's device since there is no nfc. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
* mtd: nand: pxa3xx: Fix not calling dev_xxx with a deviceSean Anderson2020-09-301-15/+15
| | | | | | | | Use the device from any mtd already available, or from the active mtd via pxa3xx_nand_info if one is not. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
* nand: Kconfig: Change dependency for NAND_ARASANMichal Simek2020-09-231-1/+1
| | | | | | | | | | | | | NAND_ARASAN selecting DM_MTD uunconditionally. Driver can be enabled with !DM that's why Kconfig it showing it as error: WARNING: unmet direct dependencies detected for DM_MTD Depends on [n]: DM [=n] Selected by [y]: - NAND_ARASAN [=y] && MTD_RAW_NAND [=y] Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* xilinx: drivers: Use '_' instead of '-' in driver nameMichal Simek2020-09-232-2/+2
| | | | | | | | | The most of drivers are using '_' instead of '-' in driver name. That's why sync up these names to be aligned. It looks quite bad to see both in use. It is visible via dm tree command. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* mtd: nand: Fix nand write error with bad block addresses above 32-bitT Karthik Reddy2020-09-111-3/+3
| | | | | | | | | | | | | | | | Nand writes should skip the bad blocks with "nand write" command. In case of bad blocks with above 32-bit address, nand_block_isbad() returns false due to truncated bad block address. In below code segment, if (nand_block_isbad(mtd, offset & ~(mtd->erasesize - 1))) offset is 64-bit and mtd->erasesize is 32-bit, hence the truncation is happening. Cast 'mtd->erasesize' with loff_t to fix this issue. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* mtd: rawnand: stm32_fmc2: get resources from parent nodeChristophe Kerello2020-08-131-28/+59
| | | | | | | | | | | FMC2 EBI support has been added. Common resources (registers base address and clock) can now be shared between the 2 drivers using "st,stm32mp1-fmc2-nfc" compatible string. It means that the common resources should now be found in the parent device when EBI node is available. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* mtd: rawnand: stm32_fmc2: use clrsetbits_le32Christophe Kerello2020-08-131-35/+21
| | | | | | | This patch uses clrsetbits_le32 function instead of multiple instructions. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* mtd: rawnand: stm32_fmc2: use FIELD_PREP/FIELD_GET macrosChristophe Kerello2020-08-131-64/+56
| | | | | | | This patch removes custom macros and uses FIELD_PREP and FIELD_GET macros. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* mtd: rawnand: stm32_fmc2: cosmetic change to use nfc instead of fmc2 where ↵Christophe Kerello2020-08-131-132/+131
| | | | | | | | | | | | relevant This patch renames functions and local variables. This cleanup is done to get all functions starting by stm32_fmc2_nfc in the FMC2 raw NAND driver when all functions will start by stm32_fmc2_ebi in the FMC2 EBI driver. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* mtd: rawnand: stm32_fmc2: use FMC2_TIMEOUT_5S for timeoutsChristophe Kerello2020-08-131-3/+5
| | | | | | | | | | FMC2_TIMEOUT_5S will be used each time that we need to wait. It was seen, during stress tests in an overloaded system, that we could be close to 1 second, even if we never met this value. To be safe, FMC2_TIMEOUT_MS is set to 5 seconds. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* mtd: rawnand: stm32_fmc2: remove useless inline commentsChristophe Kerello2020-08-131-25/+0
| | | | | | | | Remove inline comments that are useless since function label are self explanatory. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* mtd: rawnand: stm32_fmc2: fix a buffer overflowChristophe Kerello2020-08-131-1/+1
| | | | | | | The chip select defined in the device tree could only be 0 or 1. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* Fix corner case in bad block table handling.Doyle, Patrick2020-08-041-1/+1
| | | | | | | | | In the unlikely event that both blocks 10 and 11 are marked as bad (on a 32 bit machine), then the process of marking block 10 as bad stomps on cached entry for block 11. There are (of course) other examples. Signed-off-by: Patrick Doyle <pdoyle@irobot.com> Reviewed-by: Richard Weinberger <richard@nod.at>
* nand: Drop dm.h header fileSimon Glass2020-08-032-2/+3
| | | | | | | This header file should not be included in other header files. Remove it and use a forward declaration instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* mtd: spinand: micron: Add new Micron SPI NAND devices with multiple diesShivamurthy Shastri2020-07-201-0/+55
| | | | | | | | | | Add device table for new Micron SPI NAND devices, which have multiple dies. Also, enable support to select the dies. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
* mtd: spinand: micron: Add M70A series Micron SPI NAND devicesShivamurthy Shastri2020-07-201-0/+20
| | | | | | | Add device table for M70A series Micron SPI NAND devices. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
* mtd: spinand: micron: identify SPI NAND device with Continuous Read modeShivamurthy Shastri2020-07-201-0/+16
| | | | | | | | | | | | | | | | | | | | | | Add SPINAND_HAS_CR_FEAT_BIT flag to identify the SPI NAND device with the Continuous Read mode. Some of the Micron SPI NAND devices have the "Continuous Read" feature enabled by default, which does not fit the subsystem needs. In this mode, the READ CACHE command doesn't require the starting column address. The device always output the data starting from the first column of the cache register, and once the end of the cache register reached, the data output continues through the next page. With the continuous read mode, it is possible to read out the entire block using a single READ command, and once the end of the block reached, the output pins become High-Z state. However, during this mode the read command doesn't output the OOB area. Hence, we disable the feature at probe time. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
* mtd: spinand: micron: Add new Micron SPI NAND devicesShivamurthy Shastri2020-07-201-0/+30
| | | | | | | Add device table for M79A and M78A series Micron SPI NAND devices. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
* mtd: spinand: micron: Describe the SPI NAND device MT29F2G01ABAGDShivamurthy Shastri2020-07-201-0/+1
| | | | | | | | Add the SPI NAND device MT29F2G01ABAGD series number, size and voltage details as a comment. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
* mtd: spinand: micron: Generalize the OOB layout structure and function namesShivamurthy Shastri2020-07-201-14/+14
| | | | | | | | In order to add new Micron SPI NAND devices, we generalized the OOB layout structure and function names. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
* mtd: nand: raw: denali: Wait for reset completion statusLey Foon Tan2020-07-113-1/+17
| | | | | | | | | | | | | Fixed delay 200us is not working in certain platforms. Change to poll for reset completion status to have more reliable reset process. Controller will set the rst_comp bit in intr_status register after controller has completed its reset and initialization process. Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Radu Bacrau <radu.bacrau@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* mtd: nand: raw: denali: Assert reset before deassertLey Foon Tan2020-07-111-0/+2
| | | | | | | | | | | | | | Always put the controller in reset, then take it out of reset. This is to make sure controller always in reset state in both SPL and proper Uboot. This is preparation for the next patch to poll for reset completion (rst_comp) bit after reset. Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Radu Bacrau <radu.bacrau@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* spl: fit: nand: fix fit loading in case of bad blocksDario Binacchi2020-07-081-0/+28
| | | | | | | | | | | | The offset at which the image to be loaded from NAND is located is retrieved from the itb header. The presence of bad blocks in the area of the NAND where the itb image is located could invalidate the offset which must therefore be adjusted taking into account the state of the sectors concerned. cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
* mtd: spinand: toshiba: Support for new Kioxia Serial NANDYoshio Furuyama2020-05-281-16/+103
| | | | | | | | | | | | | | Add support for new Kioxia products. The new Kioxia products support program load x4 command, and have HOLD_D bit which is equivalent to QE bit. Signed-off-by: Yoshio Furuyama <ytc-mb-yfuruyama7@kioxia.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/aa69e455beedc5ce0d7141359b9364ed8aec9e65.1584949601.git.ytc-mb-yfuruyama7@kioxia.com Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* mtd: spinand: toshiba: Rename function name to change suffix and prefix (8Gbit)Yoshio Furuyama2020-05-281-27/+27
| | | | | | | | | | | | | | | | | | | | | | The suffix was changed from "G" to "J" to classify between 1st generation and 2nd generation serial NAND devices (which now belong to the Kioxia brand). As reference that's 1st generation device of 1Gbit product is "TC58CVG0S3HRAIG" 2nd generation device of 1Gbit product is "TC58CVG0S3HRAIJ". The 8Gbit type "TH58CxG3S0HRAIJ" is new to Kioxia's serial NAND lineup and the prefix was changed from "TC58" to "TH58". Thus the functions were renamed from tc58cxgxsx_*() to tx58cxgxsxraix_*(). Signed-off-by: Yoshio Furuyama <ytc-mb-yfuruyama7@kioxia.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/0dedd9869569a17625822dba87878254d253ba0e.1584949601.git.ytc-mb-yfuruyama7@kioxia.com Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* mtd: rawnand: denali: deassert write protect pinMasahiro Yamada2020-05-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [ Linux commit 9afbe7c0140f663586edb6e823b616bd7076c00a ] If the write protect signal from this IP is connected to the NAND device, this IP can handle the WP# pin via the WRITE_PROTECT register. The Denali NAND Flash Memory Controller User's Guide describes this register like follows: When the controller is in reset, the WP# pin is always asserted to the device. Once the reset is removed, the WP# is de-asserted. The software will then have to come and program this bit to assert/de-assert the same. 1 - Write protect de-assert 0 - Write protect assert The default value is 1, so the write protect is de-asserted after the reset is removed. The driver can write to the device unless someone has explicitly cleared register before booting the kernel. The boot ROM of some UniPhier SoCs (LD4, Pro4, sLD8, Pro5) is the case; the boot ROM clears the WRITE_PROTECT register when the system is booting from the NAND device, so the NAND device becomes read-only. Set it to 1 in the driver in order to allow the write access to the device. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
* mtd: rawnand: denali: configure SPARE_AREA_SKIP_BYTES only for denali_splMasahiro Yamada2020-05-221-9/+9
| | | | | | | | This CONFIG option is only used in denali_spl.c Move it close to SPL_NAND_DENALI, and make it depend on SPL_NAND_DENALI. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* common: Drop linux/bitops.h from common headerWIP/2020-05-18-reduce-size-of-common.hSimon Glass2020-05-1819-0/+19
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop linux/delay.h from common headerSimon Glass2020-05-1816-0/+16
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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