summaryrefslogtreecommitdiff
path: root/drivers/mtd/spi
Commit message (Collapse)AuthorAgeFilesLines
* dm: spi: Update sandbox SPI emulation driver to use ofnodeSimon Glass2018-07-091-4/+5
| | | | | | Update the parameters sandbox_sf_bind_emul to support livetree. Signed-off-by: Simon Glass <sjg@chromium.org>
* sf: Enable FSR polling on N25Q256(A)Marek Vasut2018-06-281-2/+2
| | | | | | | | | | | The N25Q256(A) datasheet clearly states that this device does have a Flag Status Register and does update FSR PEC bit 7 during Program and Erase cycles to indicate the cycle is in progress. Enable the FSR PEC bit polling on this device to prevent data corruption. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jagan@openedev.com> Cc: Tom Rini <trini@konsulko.com>
* mtd: spi: Correct parameters for s25fs512s flashAshish Kumar2018-06-251-1/+1
| | | | | | | Change sector size to 256KiB in table spi_flash_ids. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* spi: sandbox: Fix memory leak in sandbox_sf_bind_emul()Simon Glass2018-06-191-3/+4
| | | | | | | | | Move the strdup() call so that it is only done when we know we will bind the device. Reported-by: Coverity (CID: 131216) Signed-off-by: Simon Glass <sjg@chromium.org>
* sf: Add support for gd25q32b gigadevice flashCarlo Caione2018-06-041-0/+1
| | | | | | | | This flash IC is used in some chromebook models manufactured by Bitland. Signed-off-by: Carlo Caione <carlo@endlessm.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* sf: Set current flash bank to 0 in clean_bar()Marek Vasut2018-06-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clean_bar() function resets the SPI NOR BAR register to 0, but does not set the flash->curr_bar to 0 , therefore those two can get out of sync, which could ultimatelly result in corrupted flash content. The simplest test case is this: => mw 0x10000000 0x1234abcd 0x4000 => sf probe => sf erase 0x1000000 0x10000 => sf write 0x10000000 0x1000000 0x10000 => sf probe ; sf read 0x12000000 0 0x10000 ; md 0x12000000 That is, erase a sector above the 16 MiB boundary and write it with random pre-configured data. What will actually happen without this patch is the sector will be erased, but the data will be written to BAR 0 offset 0x0 in the flash. This is because the erase command will call write_bar()+clean_bar(), which will leave flash->bank_curr = 1 while the hardware BAR registers will be set to 0 through clean_bar(). The subsequent write will also trigger write_bar()+clean_bar(), but write_bar checks if the target bank == flash->bank_curr and if so, does NOT reconfigure the BAR in the SPI NOR. Since flash->bank_curr is still 1 and out of sync with the HW, the condition matches, BAR programming is skipped and write ends up at address 0x0, thus corrupting flash content. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* sf: Add Macronix MX25U25635F IDMarek Vasut2018-05-291-0/+1
| | | | | | | Add ID for the Macronix MX25U25635F flash. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
* sf: Add Winbond W25Q256 IDMarek Vasut2018-05-291-0/+2
| | | | | | | Add ID for the Winbond W25Q256 flash. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
* sf: Default page size Spansion flash "S25FS512S" is 256bAshish Kumar2018-05-161-5/+6
| | | | | | | | | | page size for JEDEC EXT starting 0x4d00 is 512b, except JEDEC ID 0x215, 0x216 and 0x220 Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> [jagan: added proper commit message] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* sf: Add support for ISSI is25wpKimmo Rautkoski2018-05-161-0/+3
| | | | | | | Added support for is25wp032, is25wp064 and is25wp128. Signed-off-by: Kimmo Rautkoski <ext-kimmo.rautkoski@vaisala.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini2018-05-0710-21/+10
| | | | | | | | | | | | | | | | | | | | When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
* Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTRTom Rini2018-04-272-4/+0
| | | | | | | | We have a large number of places where while we historically referenced gd in the code we no longer do, as well as cases where the code added that line "just in case" during development and never dropped it. Signed-off-by: Tom Rini <trini@konsulko.com>
* sf: Add Spansion s25fl208k entrySean Nyekjaer2018-04-191-0/+1
| | | | | | | Add entry for Spansion s25fl208k part. Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Reviewed-by: Jagan Teki <jagan@openedev.com>
* mtd: sf: add support for sst26wf016, sst26wf032, sst26wf064Eugeniy Paltsev2018-04-191-0/+3
| | | | | | | | This commit adds support for the SST sst26wf016, sst26wf032 and sst26wf064 flash IC. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* mtd: sf: Add support of sst26wf* flash ICs protection opsEugeniy Paltsev2018-04-192-0/+181
| | | | | | | | | | sst26wf flash series block protection implementation differs from other SST series, so add specific implementation flash_lock/flash_unlock/flash_is_locked functions for sst26wf flash ICs. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* spi: spi_flash: do not fail silently on bad user inputLiam Beguin2018-03-221-1/+1
| | | | | | | Make sure the user is notified instead of silently returning an error. Signed-off-by: Liam Beguin <liambeguin@gmail.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* arm: sunxi: Move spl spi sunxi code to mach-sunxiJagan Teki2018-03-133-326/+0
| | | | | | | | | | | | This SUNXI variant SPL SPI code doesn't use either SPI or SPL_FLASG subsystems due to size constraints and also placing this code in drivers/mtd/spi will unnecessary build SPI_FLASH code(if defined) which never required, hence moved to arch area. And also renamed the file according to kconfig which resembles proper name. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* libfdt: move headers to <linux/libfdt.h> and <linux/libfdt_env.h>Masahiro Yamada2018-03-051-1/+1
| | | | | | | | | | | | | | | | | Thomas reported U-Boot failed to build host tools if libfdt-devel package is installed because tools include libfdt headers from /usr/include/ instead of using internal ones. This commit moves the header code: include/libfdt.h -> include/linux/libfdt.h include/libfdt_env.h -> include/linux/libfdt_env.h and replaces include directives: #include <libfdt.h> -> #include <linux/libfdt.h> #include <libfdt_env.h> -> #include <linux/libfdt_env.h> Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* sf: Add ISSI IS25LP256 entryMarek Vasut2018-02-231-0/+1
| | | | | | | Add entry for ISSI IS25LP256 part. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jagan@openedev.com>
* sf_probe: Merge spi_flash_probe_tail into spi_flash_probeMario Six2018-01-241-12/+7
| | | | | | | | | spi_flash_probe_tail is now only called from spi_flash_probe, hence we can merge its body into spi_flash_probe. Reviewed-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
* spi: sf_probe: Fix style violationsMario Six2018-01-241-2/+2
| | | | | | | Fix two indention-related style violations. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Jagan Teki <jagan@openedev.com>
* spi: Remove spi_flash_probe_fdtMario Six2018-01-241-13/+0
| | | | | | | | | | | | Commit ba45756 ("dm: x86: spi: Convert ICH SPI driver to driver model") removed the last usage of the spi_flash_probe_fdt function, rendering it obsolete. This patch removes the function. Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
* drivers: spi: consider command bytes when sending transfersÁlvaro Fernández Rojas2018-01-241-1/+1
| | | | | | | | | | Command bytes are part of the written bytes and they should be taken into account when sending a spi transfer. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* drivers: spi: allow limiting readsÁlvaro Fernández Rojas2018-01-241-0/+3
| | | | | | | | | | | | For some SPI controllers it's not possible to keep the CS active between transfers and they are limited to a known number of bytes. This splits spi_flash reads into different iterations in order to respect the SPI controller limits. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* mtd/spi: fix block count for is25lq040bSean Nyekjaer2017-12-191-1/+1
| | | | | | | | This spi-nor is 4Mbit/512KB Fixes: b4fbcbc5a5 ("mtd/spi: add support for is25lq040b") Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Reviewed-by: Jagan Teki <jagan@openedev.com>
* mtd/spi: add support for is25lq040bSean Nyekjaer2017-11-211-0/+1
| | | | | Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Reviewed-by: Jagan Teki <jagan@openedev.com>
* SPL: SPI: select SPL_SPI_FLASH_SUPPORT on SPL_SPI_SUNXIAndre Przywara2017-10-251-0/+1
| | | | | | | | | | | | | | The Allwinner SPI flash SPL boot support is guarded by the SPL_SPI_SUNXI symbol. But despite its generic name, the actual only use case for this is to provide SPI flash support to the SPL, which requires CONFIG_SPL_SPI_FLASH_SUPPORT to be defined. Select this symbol from the SPL_SPI_SUNXI Kconfig definition. This avoids doing this explicitly in the defconfig, and fixes SPI booting on the Pine64 SoPine (and -LTS version) and the OrangePi Win board (both with SPI flash). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* sf: bar: Clean BA24 Bank Address Register bit after read/write/erase operationLukasz Majewski2017-09-271-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The content of Bank Address Register (BAR) is volatile. It is cleared after power cycle or reset command (RESET F0h). Some memories (like e.g. s25fl256s) use it to access memory larger than 0x1000000 (16 MiB). The problem shows up when one: 1. Reads/writes/erases memory > 16 MiB 2. Calls "reset" u-boot command (which is not causing BAR to be cleared) In the above scenario, the SoC ROM sends 0x000000 address to read SPL. Unfortunately, the BA24 bit is still set and hence it receives content from 0x1000000 (16 MiB) memory address. As a result the SoC aborts and we hang. Only power cycle can take the SoC out of this state. How to reproduce/test: sf probe; sf erase 0x1200000 0x800000; reset sf probe; sf erase 0x1200000 0x800000; sf write 0x11000000 0x1200000 0x800000; reset sf probe; sf read 0x11000000 0x1200000 0x800000; reset Signed-off-by: Lukasz Majewski <lukma@denx.de> [Fixed comment text on clean_bar function] Signed-off-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* SPL: SPI: sunxi: add SPL FIT image supportAndre Przywara2017-09-271-7/+32
| | | | | | | | | | | | | The sunxi-specific SPI load routine only knows how to load a legacy U-Boot image. Teach it how to handle FIT images as well, simply by providing the existing SPL FIT loader with the right loader routine to access the SPI NOR flash. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reported-by: Peter Kosa <kope@madnet.sk> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* Fix s25fl256s position in spi_flash_ids listVsevolod Gribov2017-09-251-1/+1
| | | | | | | | | | | | Spansion S25FS256S and S25FL256S flashes have equal JEDEC ID and ext ID. As far as S25FL256S occures in spi_flash_ids before S25FS256S, U-Boot incorrectly detects FS flash as FL. Thus its better to compare with S25FS256S first. Signed-off-by: Vsevolod Gribov <vgribov@larch-networks.com> [Added S-o-b] Signed-off-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* sf: Fix S25FL116K entryMarek Vasut2017-09-251-1/+1
| | | | | | | | The flash chip is 2 MiB , organized as 32 x 64 kiB sectors . Rectify the entry to match the datasheet, reality and Linux SNOR IDs. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
* mtd/spi: Add MT35XU512ABA1G12 NOR flash supportYogesh Gaur2017-09-251-0/+1
| | | | | | | | | | | Add MT35XU512ABA1G12 parameters to NOR flash parameters array. The MT35XU512ABA1G12 only supports 1 bit mode and 8 bits. It can't support dual and quad. Supports subsector erase with 4KB granularity, have support of FSR(flag status register) and flash size is 64MB. Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* nds32: mtd: add spi flash id MX25U16335E.rick2017-09-211-0/+1
| | | | | | To support MACRONIX MX25U1635E 16M-BIT flash. Signed-off-by: rick <rick@andestech.com>
* sf: Preserve QE bit when clearing BP# bits for Macronix flashBin Meng2017-08-161-4/+18
| | | | | | | | | | | | | On some flash (like Macronix), QE (quad enable) bit is in the same status register as BP# bits, and we need preserve its original value during a reboot cycle as this is required by some platforms (like Intel ICH SPI controller working under descriptor mode). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com> [Refined code for readability] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* mtd: spi: sf_dataflash: Add print message while erase errorWenyou.Yang@microchip.com2017-08-081-2/+8
| | | | | | | | Add the print message to tell us why the erase operation doesn't work. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
* sf: Add Macronix MX25U6435F device parametersBin Meng2017-08-081-0/+1
| | | | | | | This adds support for Macronix flash MX25U6435F (device ID 0xc22537). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* arm: zynq: Move CONFIG_SF_DUAL_FLASH to defconfigMike Looijmans2017-06-201-0/+7
| | | | | | | | Move the only use of CONFIG_SF_DUAL_FLASH to defconfig. This makes the associated topic_miamiplus.h header obsolete, so remove that as well. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* dm: sandbox: spi: Convert driver to support livetreeSimon Glass2017-06-011-4/+2
| | | | | | Update this driver to support a live device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: spi-flash: Convert uclass to livetreeSimon Glass2017-06-011-4/+3
| | | | | | Update the SPI flash uclass to support a live device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2017-04-062-9/+9
|\ | | | | | | | | | | trini: Disable CONFIG_SPL_USE_ARCH_MEMSET on orangepi_2 Signed-off-by: Tom Rini <trini@konsulko.com>
| * sunxi: prepare for sharing MACH_SUN8I_H3 config symbolAndre Przywara2017-04-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared Kconfig option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * SPI: SPL: sunxi: fix 64-bit buildAndre Przywara2017-04-051-8/+8
| | | | | | | | | | | | | | | | | | | | | | Addresses passed on to readl and writel are expected to be of the same size as a pointer. Change the parameter types of sunxi_spi0_read_data() to make the compiler happy and allow a warning-free aarch64 compile. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | dm: core: Add flags parameter to device_remove()Stefan Roese2017-04-042-2/+2
|/ | | | | | | | | | | | | This patch adds the flags parameter to device_remove() and changes all calls to this function to provide the default value of DM_REMOVE_NORMAL for "normal" device removal. This is in preparation for the driver specific pre-OS (e.g. DMA cancelling) remove support. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* dm: core: Replace of_offset with accessorSimon Glass2017-02-082-3/+3
| | | | | | | | | At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
* spl: sunxi: Fix build error with CONFIG_SPL_SPI_SUNXIPriit Laes2017-01-041-1/+1
| | | | | | | Fix typo introduced in ebc4ef61d76fc182773fe225151adc9b913c62eb Signed-off-by: Priit Laes <plaes@plaes.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
* Revert "sf: Fix quad bit set for micron devices"Cyrille Pitchen2016-12-152-63/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit c56ae7519f141523ba1248b22b5b5169b21772fe. Once the 'Quad Enable' bit is cleared in their Enhanced Volatile Configuration Register (EVCR), Micron memories expect ALL commands to use the SPI 4-4-4 protocol. Commands using SPI 1-y-z protocols are no longer accepted. Within the reverted commit, the write_evcr() function is implemented using the spi_flash_write_common(), which is a shortcut for the [ spi_flash_cmd_write_enable(), spi_flash_cmd_write(), spi_flash_cmd_wait_ready() ] sequence. Since the internal state of the Micron memory has been changed when the spi_flash_cmd_write() function completes, the later call of the spi_flash_cmd_wait_ready() function fails. Indeed the SPI controller driver is not aware of the SPI protocol switch. Further patches will fix the support of Micron QSPI memories. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> [Rebase on master, use JEDEC_MFR(info) in place of idcode0] Signed-off-by: Jagan Teki <jagan@openedev.com>
* sf: Do not force the DT memory map size to exactly match the devicePhil Edworthy2016-12-151-1/+1
| | | | | | | | | As long as the memory mapped size specifeid in the DT is the same or bigger than the device size, it will work. So do not force the sizes to be identical. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* mtd: spi: don't return -1 when scan succeedFabien Parent2016-12-151-2/+2
| | | | | | | | | | In spi_flash_scan, 'ret' is initialled to -1, but 'ret' is not always used to store a return value, in that case, even when the function succeed, an error (-1) will be returned. Lets just return 0 if we hit the end of the function. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* spl: Add a name to the SPL load-image methodsSimon Glass2016-12-091-1/+1
| | | | | | | | | | | It is useful to name each method so that we can print out this name when using the method. Currently this happens using a separate function. In preparation for unifying this, add a name to each method. The name is only available if we have libcommon support (i.e can use printf()). Signed-off-by: Simon Glass <sjg@chromium.org>
* spi: Add of-platdata support to SPI and SPI flashSimon Glass2016-11-251-1/+1
| | | | | | | Some boards may want to use these subsystems with of-platdata in SPL. Add support for this by avoiding any device tree access in this case. Signed-off-by: Simon Glass <sjg@chromium.org>
View Lorry Controller Status