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* net: ks8851: Add Kconfig entriesMarek Vasut2020-05-221-0/+14
| | | | | | | | Convert CONFIG_KS8851_MLL and CONFIG_KS8851_MLL_BASEADDR to Kconfig Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* net: ks8851: Add DM supportMarek Vasut2020-05-221-0/+103
| | | | | | | | Add support for U-Boot DM and DT probing. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* net: ks8851: Receive one packet per recv callMarek Vasut2020-05-221-29/+36
| | | | | | | | | | | Instead of reading out the entire FIFO and possibly overwriting U-Boot memory, read out one packet per recv call, pass it to U-Boot network stack, and repeat. It is however necessary to cache RXFC value, because reading that one out clears it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* net: ks8851: Split non-DM specific bits from common codeMarek Vasut2020-05-221-16/+44
| | | | | | | | | Split network handling functions into non-DM specific parts and common code in preparation for conversion to DM. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* net: ks8851: Pass around driver private dataMarek Vasut2020-05-221-124/+133
| | | | | | | | | | Introduce a private data structure for this driver with embedded struct eth_device and pass it around. This prepares the driver to work with both DM and non-DM systems. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* net: ks8851: Checkpatch cleanupMarek Vasut2020-05-221-9/+10
| | | | | | | | Fix various checkpatch complaints. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* net: ks8851: Clean up chip ID readoutMarek Vasut2020-05-221-19/+2
| | | | | | | | | | | There is only one chip ID in the table of chip IDs for this chip. Read out the chip ID instead and mask off the last "revision" bit to check the chip ID, this works for all chips in the family. Then drop the chip ID passing around. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* net: ks8851: Remove type_frame_headMarek Vasut2020-05-221-29/+7
| | | | | | | | | | The packet status and length information should be extracted from the FIFO per-packet. Adjust the code such that it reads the packet meta data and then the packet afterward, if applicable. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* net: ks8851: Trim down struct ks_netMarek Vasut2020-05-221-61/+9
| | | | | | | | | Most of the entries in the structure are useless, remove them. Inline the rest of uses where applicable. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* net: ks8851: Use 16bit RXQCR accessMarek Vasut2020-05-221-13/+4
| | | | | | | | | | Per KS8851-16MLL, the RXQCR is a 16bit register. Use 16bit accessors to it consistently and drop the ks_wrreg8() function altogether, as it is not used anymore. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* net: ks8851: Remove RXQCR cacheMarek Vasut2020-05-221-9/+6
| | | | | | | | | The cached RXQCR value is never updated, remove the cache and just use the bits in the cache directly in the code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* net: ks8851: Replace malloc()+memset() with calloc()Marek Vasut2020-05-221-6/+3
| | | | | | | | | | | Replace combination of malloc()+memset() with calloc() as the behavior is exactly the same and the amount of code is reduced. Moreover, remove printf() in the fail path, as it is useless, and return proper -ENOMEM return code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqWIP/20May2020Tom Rini2020-05-202-5/+31
|\ | | | | | | | | | | | | - Add DM_ETH support for lx2160aqds, ls2080aqds, ls1088aqds - QSI related fixes on ls1012a, ls2080a, ls1046a, ls1088a, ls1043a based platforms - Bug-fixes/updtaes related to ls1046afrwy, fsl-mc, msi-map property
| * net: fsl-mc: fixup DPC: add /board/ports node if missingRazvan Ionut Cirjan2020-05-191-3/+14
| | | | | | | | | | | | | | | | | | | | The DPC fixup for MAC address and enet_if is not made if /board/ports node is missing in DPC file. Add /board/ports or /ports nodes if them are missing. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> Reviewed-by: Ioana Ciornei <Ioana.ciornei@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * drivers: net: fsl-mc: fixup msi-map propertyLaurentiu Tudor2020-05-191-1/+16
| | | | | | | | | | | | | | | | | | | | Similarly to iommu-map, the msi-map property must also be fixed up in the device tree, in order for the icid -> streamid translation be possible in the MSI case as well. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Diana Craciun <diana.craciun@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * driver: net: fm: minor fix in DM ETH supportMadalin Bucur2020-05-191-1/+1
| | | | | | | | | | | | | | | | Bus callback functions for read/write/reset need to be set only for DM_ETH, moving endif a bit lower. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | common: Drop linux/bitops.h from common headerWIP/2020-05-18-reduce-size-of-common.hSimon Glass2020-05-1845-0/+45
| | | | | | | | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop linux/delay.h from common headerSimon Glass2020-05-1884-0/+84
| | | | | | | | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Fix some checkpatch warnings in calls to udelay()Simon Glass2020-05-184-30/+30
| | | | | | | | | | | | | | Fix up some incorrect code style in calls to functions in the linux/time.h header, mostly udelay(). Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop linux/bug.h from common headerSimon Glass2020-05-188-0/+8
| | | | | | | | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop log.h from common headerSimon Glass2020-05-1877-1/+81
| | | | | | | | | | | | Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* | command: Remove the cmd_tbl_t typedefSimon Glass2020-05-188-28/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop image.h from common headerSimon Glass2020-05-187-0/+7
| | | | | | | | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop part.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | | | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop net.h from common headerSimon Glass2020-05-1832-0/+40
|/ | | | | | | | | | | Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
* rename symbol: CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOODTrevor Woerner2020-05-152-2/+2
| | | | | | | | Have this symbol follow the pattern of all other such symbols. This patch also removes a TODO from the code. Reviewed-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Trevor Woerner <twoerner@gmail.com>
* rename symbol: CONFIG_ORION5X -> CONFIG_ARCH_ORION5XTrevor Woerner2020-05-152-2/+2
| | | | | | | Have this symbol follow the pattern of all other such symbols. This patch removes a TODO from the code. Signed-off-by: Trevor Woerner <twoerner@gmail.com>
* net: bcmgenet: Don't set ID_MODE_DIS when not using RGMIINicolas Saenz Julienne2020-05-121-1/+4
| | | | | | | | | | | As per Linux's driver, ID_MODE_DIS is only set when the PHY interface is RGMII. Don't enable it for the rest of setups. This has been seen to misconfigure RPi4's PHY when booting Linux. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
* Merge tag 'ti-v2020.07-rc2' of ↵Tom Rini2020-05-111-0/+4
|\ | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-ti - Fix boot issues on Nokia RX-51 - Configure AM6 CPSW for 10Mbps in rgmii mode. - Minor changes for J721e
| * net: ethernet: ti: am65-cpsw-nuss: enable 10Mbps link speed in rgmii modeMurali Karicheri2020-05-091-0/+4
| | | | | | | | | | | | | | | | | | | | | | In RGMII mode the 10Mbps link speed is supported only when CPSW2G MAC SL is configured for External Control ("in band") mode CPSW_PN_MAC_CONTROL_REG.CTL_EN(18) = 1 Hence update am65_cpsw_update_link() to follow documentation. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
* | eQos: Implement the read_rom_hwaddr callbackYe Li2020-05-101-0/+11
| | | | | | | | | | | | | | | | | | Implement the read_rom_hwaddr callback to load MAC address from fuse for imx8m platforms. Reviewed-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | fec: Move imx_get_mac_from_fuse declare to imx fileYe Li2020-05-101-2/+0
| | | | | | | | | | | | | | | | | | | | imx_get_mac_from_fuse is used to load MAC address from fuse. On imx8mp, we have two different ENET controllers and both need to call this function. So decouple its declare from fec driver. Reviewed-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | net: eqos: implement callbaks to get interface and set txclk rateFugang Duan2020-05-101-3/+52
| | | | | | | | | | | | | | | | | | Implement the callbacks to get phy mode interface and txclk rate configuration. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | net: dwc_eth_qos: add dwc eqos for imx supportFugang Duan2020-05-101-14/+171
| | | | | | | | | | | | | | | | Add dwc eqos for imx support. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | net: phy: realtek: add rx delay support for RTL8211FFugang Duan2020-05-101-0/+11
| | | | | | | | | | | | | | | | Add RX delay enable support for RTL8211F PHY. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | net: Update eQos driver and FEC driver to use eth phy interfacesYe Li2020-05-102-16/+45
| | | | | | | | | | | | | | Update eQoS and fec ethernet drivers to support shared MDIO framework Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | net: Add eth phy generic driver for shared MDIOYe Li2020-05-103-0/+129
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For dual ethernet controllers, the HW design may connect ETH phys to one MDIO ports. So two different ethernet drivers have to share MDIO bus. Since two ethernet drivers are independent, we can't ensure their probe order. To resolve this problem, introduce an eth phy generic driver and uclass. After eth-uclass binds, we search the mdio node and binds the phy node with the eth-phy-generic driver. When one eth driver get its phy device, the parent of phy device will probe prior than phy device. So this ensure the eth driver ownes the MDIO bus will be probed before using its MDIO. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | net: fec: add fuse checkPeng Fan2020-05-101-0/+14
|/ | | | | | | | Add fuse check for fec. If the fuse indicates the module will not work in the SoC, let's fail the initialization. Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* phy: atheros: consolidate {ar8031|ar8035}_config()WIP/2020-05-07-atheros-phy-improvementsMichael Walle2020-05-071-27/+3
| | | | | | | The two functions are now exactly the same, remove one of them. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* phy: atheros: ar8035: remove static clock configMichael Walle2020-05-071-13/+0
| | | | | | | | | | | | | | | We can configure the clock output in the device tree. Disable the hardcoded one in here. This is highly board-specific and should have never been enabled in the PHY driver. If bisecting shows that this commit breaks your board it probably depends on the clock output of your Atheros AR8035 PHY. Please have a look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set "clk-out-frequency = <125000000>" because that value was the hardcoded value until this commit. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* phy: atheros: add device tree bindings and configMichael Walle2020-05-071-2/+222
| | | | | | | | | | | | | | | | | Add support for configuring the CLK_25M pin as well as the RGMII I/O voltage by the device tree. By default the AT803x PHYs outputs the 25MHz clock of the XTAL input. But this output can also be changed by software to other frequencies. This commit introduces a generic way to configure this output. Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V. An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V option needs an external supply voltage. This commit adds support to switch the internal LDO to 1.8V. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* phy: atheros: move delay config to common functionMichael Walle2020-05-071-16/+22
| | | | | Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* phy: atheros: introduce debug read and write functionsMichael Walle2020-05-071-16/+41
| | | | | | | Provide functions to read and write the Atheros debug registers. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* phy: atheros: use defines for PHY IDsMichael Walle2020-05-071-3/+7
| | | | | Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* phy: atheros: fix AR8021 PHY ID maskMichael Walle2020-05-071-1/+1
| | | | | | | The upper bits are all the OUI. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* phy: atheros: Clarify the intention of ar8021_configVladimir Oltean2020-05-071-4/+4
| | | | | | | | | | | Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at the other bit positions, just like the other PHYs in the family do. Therefore, it is not necessary to hardcode the reserved values, but instead simply follow the read-modify-write procedure from the common function. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* phy: atheros: Explicitly disable RGMII delaysVladimir Oltean2020-05-071-0/+8
| | | | | | | | | | | | To eliminate any doubts about the out-of-reset value of the PHY, that the driver previously relied on. If bisecting shows that this commit breaks your board you probably have a wrong PHY interface mode. You probably want the PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* phy: atheros: Clarify the configuration of the CLK_25M output pinVladimir Oltean2020-05-071-5/+14
| | | | | | | | Also take the opportunity to use the phy_read_mmd and phy_write_mmd convenience functions. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* phy: atheros: Use common functions for RGMII internal delaysVladimir Oltean2020-05-071-28/+41
| | | | | Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* phy: atheros: Make RGMII Tx delays actually configurable for AR8035Vladimir Oltean2020-05-071-4/+0
| | | | | | | | | | | | | | | | | | | | | Delete the extraneous write to debug reg 5 that enables Tx delay When the driver was originally introduced in commit "6027384a phylib: Add Atheros AR8035 GETH PHY support", the Tx delay was being unconditionally enabled. Then during "2ec4d10b phy: atheros: add support for RGMII_ID, RGMII_TXID and RGMII_RXID", the author did not notice that code for enabling Tx delay code was already. Therefore, the if condition for Tx delay has always been useless for this PHY since this commit introduced it. Prior to this patch, every AR8035 PHY in U-boot had Tx delay enabled. After this patch, only those who define the interface as RGMII_TXID or RGMII_ID will. This is to be expected, but will nonetheless break the setups of those who didn't know they rely on Tx delay implicitly. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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