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* doc: arch: sandbox: Replace all the instances of README.sandboxKeerthy2019-07-291-1/+1
| | | | | | | | | commit 49116e6d236d ("doc: arch: Convert README.sandbox to reST") Moves README.sandbox to doc/arch. Replace all the existing instances to point to the right documentation file. Signed-off-by: Keerthy <j-keerthy@ti.com>
* Merge tag 'u-boot-imx-20190719' of ↵Tom Rini2019-07-272-1/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20190719 - CCF for i.MX6 - nandbcb command to write SPL into NAND - Switch to DM (i.MX28) - Boards: Toradex, engicam, DH - Fixes for i.MX8 - Fixes for i.MX7ULP Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/561147504
| * net: fec: Enable support for i.MX28 DM_ETH in the fec_mxc.c driverLukasz Majewski2019-07-192-1/+2
| | | | | | | | | | | | | | | | | | The fec_mxc.c driver can be reused by i.MX28 when DM_ETH is enabled. One only needs to add proper compatible and dependency on FEC_MXC in the Kconfig. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Marek Vasut <marex@denx.de>
* | net: sun8i_emac: Test the correct phyEmmanuel Vadot2019-07-251-8/+21
| | | | | | | | | | | | | | | | | | | | | | | | H3/H5 can either use the internal phy or an external one. Before getting clock and resets for the internal phy, test that we are using it because otherwise it break emac when using an external phy. Tested-on: OrangePi PC2 (H5) Fixes: 2348453c41 (net: sun8i_emac: Add EPHY CLK and RESET support) Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: davinci_emac: convert to using the driver modelBartosz Golaszewski2019-07-251-35/+42
| | | | | | | | | | | | | | | | | | | | Now that we removed all legacy boards selecting TI_EMAC we can completely convert the driver code to using the driver model. This patch also updates all remaining users of davinci_emac. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Adam Ford <aford173@gmail.com> #am3517-evm & da850-evm Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* | net: macb: Fix check for little-endian system in gmac_configure_dma()Anup Patel2019-07-251-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | Instead of depending on CONFIG_SYS_LITTLE_ENDIAN, we check at runtime whether underlying system is little-endian or big-endian. This way we are not dependent on any U-Boot specific OR compiler specific macro to check system endianness. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: macb: Extend MACB driver for SiFive Unleashed boardAnup Patel2019-07-251-17/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The SiFive MACB ethernet has a custom TX_CLK_SEL register to select different TX clock for 1000mbps vs 10/100mbps. This patch adds SiFive MACB compatible string and extends the MACB ethernet driver to change TX clock using TX_CLK_SEL register for SiFive MACB. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: tsec: Change compatible strings to match LinuxVladimir Oltean2019-07-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the case of the tsec network driver, so far there has been no mainline user of DM_ETH where the DT bindings get used. In the case of the mdio bus, it looks like the "fsl,tsec-mdio" string was made up for the documentation, but there is no mainline code that parses the "compatible" property anyway. In both cases, there are no DT blobs that contain the old strings. So change the documentation to "fsl,etsec2" for the Ethernet ports and "fsl,etsec2-mdio" for the MDIO buses, which are strings that Linux also uses, at least for LS1021A. More compatible strings can be added once other (PowerPC) SoCs are migrated to DM_ETH. The current ls1021a.dtsi doesn't match what was documented for the MDIO buses anyway (the "compatible" is "gianfar" currently). This will be fixed in the next patch. Fixes: 69a00875e3db ("doc: dt-bindings: Describe Freescale TSEC ethernet controller") Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: tsec: Common handling of MAC station address for DM_ETHVladimir Oltean2019-07-251-9/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | In tsec_init, the MAC address is retrieved from 2 different structures depending on whether DM_ETH is enabled or not. But since the field name is the same inside both structures, we can conditionally define the structure of the correct type and simplify the assignments. Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | net: tsec: Make errors visibleVladimir Oltean2019-07-251-4/+4
| | | | | | | | | | | | | | | | | | This replaces debug() calls with printf() so that it is immediately obvious from the console that something is wrong. Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | net: tsec: Reverse Christmas tree notationVladimir Oltean2019-07-251-5/+5
| | | | | | | | | | | | | | | | | | This is a cosmetic patch that reorders variable definitions in the inverse order of their line length, where possible. Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | net: tsec: Fix offset of MDIO registers for DM_ETHVladimir Oltean2019-07-251-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By convention, the eTSEC MDIO controller nodes are defined in DT at 0x2d24000 and 0x2d50000, but actually U-Boot does not touch the interrupt portion of the register map (MDIO_IEVENTM, MDIO_IMASKM, MDIO_EMAPM). That leaves only the MDIO bus registers (MDIO_MIIMCFG, MDIO_MIIMCOM, MDIO_MIIMADD, MDIO_MIIMADD, MDIO_MIIMCON, MDIO_MIIMSTAT) which start at the 0x520 offset. So shift the DT-defined register map by the offset of MDIO_MIIMCFG when mapping the MDIO bus registers. Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | net: tsec: Refactor the readout of the tbi-handle propertyVladimir Oltean2019-07-251-8/+7
| | | | | | | | | | | | | | | | | | | | | | The point of this patch is to eliminate the use of the locally-defined "reg" variable (which interferes with next patch) and simplify the fallback to the default CONFIG_SYS_TBIPA_VALUE in case "tbi-handle" is missing. Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | net/macb: increase RX buffer size for GEMRamon Fried2019-07-251-8/+23
| | | | | | | | | | | | | | | | | | | | | | | | Macb Ethernet controller requires a RX buffer of 128 bytes. It is highly sub-optimal for Gigabit-capable GEM that is able to use a bigger DMA buffer. Change this constant and associated macros with data stored in the private structure. RX DMA buffer size has to be multiple of 64 bytes as indicated in DMA Configuration Register specification. Signed-off-by: Ramon Fried <rfried.dev@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: macb: apply sane DMA configurationRamon Fried2019-07-251-0/+28
| | | | | | | | | | | | | | | | | | | | | | DMA configuration was heavily dependent on the HW defaults, add function to properly set the required fields, including the new dma_burst_length. Signed-off-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Anup Patel <anup.patel@wdc.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: macb: add dma_burst_length configRamon Fried2019-07-251-1/+21
| | | | | | | | | | | | | | | | | | | | | | GEM support higher DMA burst writes/reads than the default (4). add configuration structure with dma burst length so it could be applied later to DMA configuration. Signed-off-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Anup Patel <anup.patel@wdc.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: macb: add support for SGMII phy interfaceRamon Fried2019-07-251-0/+7
| | | | | | | | | | | | | | | | | | | | | | This patch adds support for the sgmii phy interface, available only to DM users, dictated by current driver design. Signed-off-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Anup Patel <anup.patel@wdc.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: macb: use bit access macro from header fileRamon Fried2019-07-251-33/+15
| | | | | | | | | | | | | | | | | | | | | | macb.h provides macros for reading/setting bitfields, in macb registers and descriptors. use that instead of redefining them in the source file. Signed-off-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Anup Patel <anup.patel@wdc.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: macb: add support for faster clk ratesRamon Fried2019-07-252-1/+7
| | | | | | | | | | | | | | | | | | add support for clock rates higher than 2.4Mhz Signed-off-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Anup Patel <anup.patel@wdc.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: macb: sync header definitions as taken from LinuxRamon Fried2019-07-252-214/+662
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Few registers and bits were added by Cadence and they were not updated in the headers. Take the latest definitions as defined in Linux header (5.1) that also includes some comments about existing registers. One register was improperly named (UR), fix that. Signed-off-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Anup Patel <anup.patel@wdc.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | drivers: net: driver for MDIO muxes controlled over I2CAlex Marginean2019-07-252-0/+9
| | | | | | | | | | | | | | | | | | | | This driver is used for MDIO muxes driven over I2C. This is currently used on Freescale LS1028A QDS board, on which the physical MDIO MUX is controlled by an on-board FPGA which in turn is configured through I2C. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | net: designware: use 'phy_connect' instead of open codedSimon Goldschmidt2019-07-251-5/+3
| | | | | | | | | | | | | | | | Using 'phy_connect' instead of 'phy_find_by_mask' and 'phy_connect_dev' both deduplicates code and adds support for 'fixed-link'. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | drivers: net: fsl_enetc: add support for SGMII 2500Alex Marginean2019-07-252-7/+23
| | | | | | | | | | | | | | | | SGMII 2500 as supported on NXP SoCs requires AN to be disabled, handle this case in the enetc sgmii init code. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | drivers: net: apply serdes configuration for ENETC Ethernet interfacesAlex Marginean2019-07-253-5/+189
| | | | | | | | | | | | | | | | | | | | | | | | | | Ethernet interfaces using serial protocols go through the serdes block integrated in the SoC. This is accessed over dedicated internal MDIOs which are part of the Ethernet PCI functions. Set up serdes at _start, along with other protocol specific port/MAC configuration. MDIO code is shared with enetc_mdio, read/write functions are exported from fsl_enetc_mdio for this reason. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | drivers: net: add NXP ENETC MDIO driverAlex Marginean2019-07-255-2/+229
| | | | | | | | | | | | | | | | | | | | | | | | Adds a driver for the MDIO interface currently integrated in LS1028A SoC. This MDIO interface is shared by multiple ethernet interfaces and is presented as a stand-alone PCI function on the SoC ECAM. Ethernet has a functional dependency on MDIO, for simplicity there is a single config option for both. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | drivers: net: add NXP ENETC ethernet driverAlex Marginean2019-07-254-0/+556
| | | | | | | | | | | | | | | | | | | | | | Adds a driver for NXP ENETC ethernet controller currently integrated in LS1028A. ENETC is a fairly straight-forward BD ring device and interfaces are presented as PCI EPs on the SoC ECAM. Signed-off-by: Catalin Horghidan <catalin.horghidan@nxp.com> Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: designware: remove mdio bus on probe failureSimon Goldschmidt2019-07-181-5/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The designware eth driver registers an mdio bus during probe, but if no PHY is found, this bus is never removed although probe failes and the driver is shown as not probed in the dm tree. This later leads to errors when e.g. the mii or mdio commands try to use available mdio buses because the mdio bus is still registered but all corresponding data structures are invalid because probe failed. Fix this by unregistering the mdio bus on probe failure (just as it is unregistered in the .remove callback, too). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | test: dm: add a test for MDIO MUX DM uclassAlex Marginean2019-07-183-0/+108
| | | | | | | | | | | | | | | | | | Adds a test using a makeshift MDIO MUX. The test is based on the existing MDIO test. It uses the last emulated PHY register to verify MUX selection. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | test: dm_mdio: add a 2nd register to the emulated PHYAlex Marginean2019-07-181-7/+9
| | | | | | | | | | | | | | | | This 2nd register is used by the follow-up MDIO MUX test. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: add MDIO_MUX DM classAlex Marginean2019-07-181-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | Adds a class for MDIO MUXes, which control access to a series of downstream child MDIOs. MDIO MUX drivers are required to implement a select function used to switch between child buses. MUX children are registered as MDIO buses and they can be used just like regular MDIOs. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | drivers: net: phy: Ignore PHY ID 0 during PHY probingAlex Marginean2019-07-181-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | Current code fails to probe some C45 PHYs that also respond to C22 reads. This is the case for PHYs like Aquantia AQR112, Marvell 88X2242 (as previously posted on the u-boot list). If the PHY ID reads all 0s just ignore it and try the next devad. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-By: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | drivers: net: phy: Use Aquantia driver for AQR112, AQR412Alexandru Marginean2019-07-181-0/+28
|/ | | | | | | | | adds AQR112 and AQR412 to the list of supported PHYs using existing AQR code. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-By: Ramon Fried <rfried.dev@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: macb: Add support for 1000-baseXRadu Pirea2019-07-151-2/+4
| | | | | | | | | Macb can be used with Xilinx PCS/PMA PHY in fpga which is a 1000-baseX phy(lpa 0x41e0). This patch adds checks for LPA_1000XFULL and LPA_1000XHALF bits. Signed-off-by: Radu Pirea <radu_nicolae.pirea@upb.ro> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: macb: Fixed reading MII_LPA registerRadu Pirea2019-07-151-1/+1
| | | | | | | | | If macb is gem and is gigabit capable, lpa value is not read from the right register(MII_LPA) and is read from MII_STAT1000. This patch fixes reading of the lpa value. Signed-off-by: Radu Pirea <radu_nicolae.pirea@upb.ro> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: ethernet: ti: Introduce am654 gigabit eth switch subsystem driverKeerthy2019-07-153-0/+801
| | | | | | | | | | | | | | | | | | | | | Add new driver for the TI AM65x SoC Gigabit Ethernet Switch subsystem (CPSW NUSS). It has two ports and provides Ethernet packet communication for the device and can be configured as an Ethernet switch. CPSW NUSS features: the Reduced Gigabit Media Independent Interface (RGMII), Reduced Media Independent Interface (RMII), and the Management Data Input/Output (MDIO) interface for physical layer device (PHY) management. The TI AM65x SoC has integrated two-port Gigabit Ethernet Switch subsystem into device MCU domain named MCU_CPSW0. One Ethernet port (port 1) with selectable RGMII and RMII interfaces and an internal Communications Port Programming Interface (CPPI) port (Host port 0). Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels and on RX channels operating by TI am654 NAVSS Unified DMA Peripheral Root Complex (UDMA-P) controller. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* driver: net: ti: cpsw-mdio: use phys_addr_t for mdio_base addrKeerthy2019-07-152-3/+3
| | | | | | | | | | | Use phys_addr_t for mdio_base address to avoid build warnings on arm64 and dra7. Cast it to uintprt_t before assigning to regs. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: phy: cortina: Use block layer to read from mmcYinbo Zhu2019-07-151-0/+5
| | | | | | | This patch is to use block layer to read from mmc in cortina Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: mscc: refactor mscc_miimHoratiu Vultur2019-07-158-516/+63
| | | | | | | | | | Because all MSCC SoC use the same MDIO bus, put the implementation in one common file(mscc_miim) and make all the other MSCC network drivers to use these functions. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* test: dm: add MDIO testAlex Marginean2019-07-153-0/+103
| | | | | | | | | | A very simple test for DM_MDIO, mimicks a register write/read through the sandbox bus to a dummy PHY. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: introduce MDIO DM class for MDIO devicesAlex Marginean2019-07-151-0/+13
| | | | | | | | | | | Adds UCLASS_MDIO DM class supporting MDIO buses that are probed as stand-alone devices. Useful in particular for systems that support DM_ETH and have a stand-alone MDIO hardware block shared by multiple Ethernet interfaces. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: mscc: serval: Remove delay when serdes is configuredHoratiu Vultur2019-07-151-2/+0
| | | | | | | | | | | | | | When serdes configuration was written in hardware there was a delay of 100ms to be sure that configuration was written. But the delay is not needed because already the function serdes_write it is checking that the operation finished. Therefore remove the mdelay. This improves the speed of configuring the network driver. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: phy: ti: Fix clock output DT propertyTrent Piepho2019-07-151-8/+2
| | | | | | | | | | | | | | | | | | The code block reading the DT property for the clock output control was before the phy's DT node pointer was set, so it could never work. Move it after the node pointer is set. Also store the unsigned 32-bit property into an unsigned value, not a signed value, as the former will cause a problem if value overflows. For instance, if one were to add 0xffffffff as a code to mean the clock output should be turned off. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Janine Hagemann <j.hagemann@phytec.de> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Trent Piepho <tpiepho@impinj.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: phy: ti: Use default values for tx/rx delay and fifo sizeTrent Piepho2019-07-151-3/+3
| | | | | | | | | | | | | | | | | | | | When not using DM_ETH, these PHY settings are programmed with default values hardcoded into the driver. When using DM_ETH, they should come from the device tree. However, if the device tree does not have the properties, the driver will silent use -1. Which is entirely out of range, programs nonsense into the PHY's registers, and does not work. Change this to use the same defaults as non-DM_ETH if the device tree is lacking the properties. As an alternative, the kernel driver for the phy will display an error message and fail if the device tree is lacking. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Janine Hagemann <j.hagemann@phytec.de> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Trent Piepho <tpiepho@impinj.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* Merge tag 'u-boot-stm32-20190606' of https://github.com/pchotard/u-bootTom Rini2019-06-111-52/+383
|\ | | | | | | | | | | | | | | | | - Add Ethernet support for STM32MP1 - Add saveenv support for STM32MP1 - Add STM32MP1 Avenger96 board support - Add SPI driver suport for STM32MP1 - Add watchdog support for STM32MP1 - Update power supply check via USB TYPE-C for STM32MP1 discovery board
| * net: dwc_eth_qos: add Ethernet stm32mp1 supportChristophe Roullier2019-06-061-52/+383
| | | | | | | | | | | | | | | | | | | | | | Synopsys GMAC 4.20 is used. And Phy mode for eval and disco is RMII with PHY Realtek RTL8211 (RGMII) We also support some other PHY config on stm32mp157c PHY_MODE (MII,GMII, RMII, RGMII) and in normal, PHY wo crystal (25Mhz and 50Mhz), No 125Mhz from PHY config Signed-off-by: Christophe Roullier <christophe.roullier@st.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: fec_mxc: not access reserved register on i.MX8Peng Fan2019-06-111-1/+1
|/ | | | | | | We should not access reserved register on i.MX8, otherwise met SERROR Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* dm: net: macb: Implement link speed change callbackBin Meng2019-06-011-0/+35
| | | | | | | | | | | | | | | | At present the link speed change callback is a nop. According to macb device tree bindings, an optional "tx_clk" is used to clock the ethernet controller's TX_CLK under different link speed. In 10/100 MII mode, transmit logic must be clocked from a free running clock generated by the external PHY. In gigabit GMII mode, the controller, not the external PHY, must generate the 125 MHz transmit clock towards the PHY. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Tested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* dm: net: macb: Update macb_linkspd_cb() signatureBin Meng2019-06-011-1/+21
| | | | | | | | | This updates DM version macb_linkspd_cb() signature for future expansion, eg: adding an implementation for link speed changes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* configs: Migrate CONFIG_FMAN_ENET and some related options to KconfigTom Rini2019-05-262-1/+7
| | | | | | | | | Move the main symbol for Freescale Fman Ethernet controller option to Kconfig. Also migrate the CONFIG_SYS_QE_FMAN_FW_IN_xxx macros and rename the SPIFLASH one to follow the same format as all of the others. To do this fully we need to migrate CONFIG_QC, do so. Signed-off-by: Tom Rini <trini@konsulko.com>
* CONFIG_SPL_SYS_[DI]CACHE_OFF: addTrevor Woerner2019-05-183-3/+4
| | | | | | | | | | | | | While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com>
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