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* ram: rk3399: Compute stride for 2 channelsJagan Teki2019-07-191-1/+70
| | | | | | | | | | | | | | | | | | | | | | | | stride value from sdram timings can be computed dynamically based on the determined capacity for the given channel. Right now these stride values are taken as part of sdram timings via dtsi, but it possible to use same timings dtsi for given frequency even though the configured board sdram do support single channel with different size by dynamically detect the stride value. Example, NanoPi NEO4 do have DDR3-1866, but with single channel and 1GB size with dynamic stride detection it is possible to use existing rk3399-sdram-ddr3-1866.dtsi whose stride, number of channels and capacity it support is d efferent. So, add initial support to calculate the stride value for 2 channels sdram, which is available by default on existing boards. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* ram: rk3399: debug: Add sdram_print_strideJagan Teki2019-07-191-0/+29
| | | | | | | | | | | | Add code to print the channel stride, this would help to print the stride of associated channel. Here is sample print on LPDDR4, 50MHz. 256B stride Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* ram: rockchip: debug: Get the cs capacityJagan Teki2019-07-191-1/+45
| | | | | | | | | | | | Add code to get the channel capacity, this would help to print the capacity of specific channel. Here is sample print on LPDDR4, 50MHz channel 0 BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* ram: rockchip: debug: Add sdram_print_ddr_infoJagan Teki2019-07-191-0/+40
| | | | | | | | | | | | Add sdram ddr info print support, this would help to observe the sdram base parameters. Here is sample print on LPDDR4, 50MHz channel 0 BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* ram: rockchip: Add debug sdram driverJagan Teki2019-07-193-0/+44
| | | | | | | | | | | | | Add sdram driver to handle debug across rockchip SoCs. This would help to improve code debugging feature for sdram drivers in rockchip family, whoever wants to debug the driver should call these core debug code on their respective platform sdram drivers. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* ram: rockchip: Add initial KconfigJagan Teki2019-07-193-1/+19
| | | | | | | | | | | Right now sdram drivers in rockchip SoC are built based on the SoC configs which may not be an adequate solutions while adding common or debug driver. So, add meaningful Kconfig options start with rk3399. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* ram: rk3399: Add pctl start supportJagan Teki2019-07-191-20/+55
| | | | | | | | | | | | Add support for pctl start for both channel 0, 1 control and phy registers. This would also handle pwrup_srefresh_exit init based on the channel number. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* ram: rk3399: Move pwrup_srefresh_exit to dram_infoJagan Teki2019-07-191-6/+7
| | | | | | | | | | | Add pwrup_srefresh_exit to be part of dram_info so-that the it can help to support pwrup_srefresh_exit in individual channels while starting pctl in future. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* ram: rk3399: Add phy pctrl reset supportJagan Teki2019-07-191-0/+29
| | | | | | | | Add support for phy pctrl reset support for both channel 0, 1. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* ram: rk3399: Use rank mask in wdql data trainingJagan Teki2019-07-191-1/+7
| | | | | | | | | | Add rank_mask based on the rank number, this would keep the wdql data training loop based on the desired rank mask value instead of looping for all values. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* ram: rk3399: Use rank mask in ca data trainingJagan Teki2019-07-191-1/+7
| | | | | | | | | | Add rank_mask based on the rank number, this would keep the ca data training loop based on the desired rank mask value instead of looping for all values. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* ram: rk3399: Clear PI_175 interrupts in data trainingJagan Teki2019-07-191-0/+15
| | | | | | | | | | | Clear the PI_175 interrupts before processing actual data training in all relevant calls. This would help to clear interrupt from previous training. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* ram: rk3399: Handle data training return typesJagan Teki2019-07-191-12/+38
| | | | | | | | | | | | | | | | | data trainings calls like ca, wl, rg, rl, wdql have proper return types with -EIO and the return type missed to handle in data_training function. This patch, add proper return type checks along with useful debug statement on each data training calls. Incidentally this would help to prevent the sdram initialization hang for single channel dram and when the code is trying to initialize second channel with proper return type of relevant data training call might failed. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* ram: rockchip: rk3399: Add cap_info structureJagan Teki2019-07-191-33/+40
| | | | | | | | | | | | | | | | | | | Group common ddr attributes like - rank - col - bk - bw - dbw - row_3_4 - cs0_row - cs1_row - ddrconfig into a common cap_info structure for more code readability and extend if possible based on the new features. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* ram: rk3399: Order tsel variablesJagan Teki2019-07-191-15/+22
| | | | | | | | | | | Order tsel* variable declarations and assignment in proper and meaningful way. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* ram: rk3399: s/ca_tsel_wr_select_p/tsel_wr_select_ca_pJagan Teki2019-07-191-5/+5
| | | | | | | | | | | Rename ca_tsel_wr_select_p to tsel_wr_select_ca_p based on the bsp code. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* ram: rk3399: s/ca_tsel_wr_select_n/tsel_wr_select_ca_nJagan Teki2019-07-191-5/+5
| | | | | | | | | | | Rename ca_tsel_wr_select_n to tsel_wr_select_ca_n based on the bsp code. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* ram: rk3399: s/tsel_wr_select_p/tsel_wr_select_dq_pJagan Teki2019-07-191-6/+6
| | | | | | | | | | | Rename tsel_wr_select_p to tsel_wr_select_dq_p based on the bsp code. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* ram: rk3399: s/tsel_wr_select_n/tsel_wr_select_dq_nJagan Teki2019-07-191-6/+6
| | | | | | | | | | | Rename tsel_wr_select_n to tsel_wr_select_dq_n based on the bsp code. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* ram: rk3399: Handle pctl_cfg return typeJagan Teki2019-07-191-3/+5
| | | | | | | | Add proper return type handling of pctl_cfg with meaningful print statement. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* ram: rk3399: s/sdram_params/paramsJagan Teki2019-07-191-82/+78
| | | | | | | | | | Rename variable name of struct rk3399_sdram_params from sdram_params with params for more code readability. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* ram: rk3399: Some trivial code fixesJagan Teki2019-07-191-17/+43
| | | | | | | | | - Add proper spaces in data training, rk3399_dmc_init, pctl_cfg - Order include files - Move macro after include files Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* ram: rk3399: Fix code warningsJagan Teki2019-07-191-24/+24
| | | | | | | | | | | | | Fix checkpatch warninigs on sdram_rk3399.c like - Avoid CamelCase - Unnecessary parentheses - Alignment should match open parenthesis - multiple blank lines - misspelled - spaces preferred around that '>>' Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* ram: stm32mp1_ram: Fix warnings when compiling with W=1Patrick Delaunay2019-07-121-2/+3
| | | | | | | | | | | | | | | | This patch solves the following warnings: drivers/ram/stm32mp1/stm32mp1_ram.c: In function 'stm32mp1_ddr_clk_enable': warning: comparison between signed and unsigned integer expressions [-Wsign-compare] for (idx = 0; idx < ARRAY_SIZE(clkname); idx++) { ^ drivers/ram/stm32mp1/stm32mp1_ram.c: In function 'stm32mp1_ddr_setup': warning: comparison between signed and unsigned integer expressions [-Wsign-compare] for (idx = 0; idx < ARRAY_SIZE(param); idx++) { ^ Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* stm32mp1: ram: add tuning in DDR interactive modePatrick Delaunay2019-05-236-1/+1414
| | | | | | | | | | | Add command tuning for DDR interactive mode, used during board bring-up or with CubeMX DDR tools to execute software tuning for the DDR configuration: - software read DQS Gating (replace the built-in one) - Bit de-skew - Eye Training or DQS training Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* stm32mp1: ram: add tests in DDR interactive modePatrick Delaunay2019-05-235-0/+1541
| | | | | | | | Add command tests for DDR interactive mode, used during board bring-up or with CubeMX DDR tools to verify the DDR configuration. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* stm32mp1: ram: add interactive mode for DDR configurationPatrick Delaunay2019-05-234-0/+713
| | | | | | | | | This debug mode is used by CubeMX DDR tuning tools or manualy for tests during board bring-up. It is simple console used to change DDR parameters and check initialization. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* stm32mp1: ram: add support for LPDDR2/LPDDR3Patrick Delaunay2019-05-232-3/+10
| | | | | | | | | Manage power supply configuration for board using stpmic1 with LPDDR2 or with LPDDR3: + VDD_DDR1 = 1.8V with BUCK3 (bypass if possible) + VDD_DDR2 = 1.2V with BUCK2 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* stm32mp1: ram: update parameter array initializationPatrick Delaunay2019-05-232-16/+33
| | | | | | | | Force alignment of the size of parameters array with the expected value in the binding, that allows compilation error when the array size change. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* stm32mp1: ram: change ddr speed to kHzPatrick Delaunay2019-05-233-11/+11
| | | | | | Allow fractional support in DDR tools. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* stm32mp1: ram: increase the delay after reset to 128 cyclesPatrick Delaunay2019-05-231-5/+3
| | | | | | | | Component Notification DDR controller errata (3.00a):9001313030 Synchronization Time Waited After De-assertion of presetn is 128 pclk Cycles. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* stm32mp1: ram: update mask for operating modePatrick Delaunay2019-05-231-1/+1
| | | | | | | Regression introduced by rebase, when loop was replaced by readl_poll_timeout() function. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* mpc83xx: Introduce ARCH_MPC837XMario Six2019-05-201-4/+4
| | | | | | Replace CONFIG_MPC837x with a proper CONFIG_ARCH_MPC837X Kconfig option. Signed-off-by: Mario Six <mario.six@gdsys.cc>
* mpc83xx: Introduce ARCH_MPC836*Mario Six2019-05-201-4/+4
| | | | | | Replace CONFIG_MPC836* with proper CONFIG_ARCH_MPC836* Kconfig options. Signed-off-by: Mario Six <mario.six@gdsys.cc>
* mpc83xx: Introduce ARCH_MPC831*Mario Six2019-05-201-2/+2
| | | | | | Replace CONFIG_MPC833* with proper CONFIG_ARCH_MPC833* Kconfig options. Signed-off-by: Mario Six <mario.six@gdsys.cc>
* mpc83xx: Introduce ARCH_MPC830*Mario Six2019-05-201-2/+2
| | | | | | Replace CONFIG_MPC830* with proper CONFIG_ARCH_MPC830* Kconfig options. Signed-off-by: Mario Six <mario.six@gdsys.cc>
* rockchip: ram: rk3399: update for TPLKever Yang2019-05-081-5/+10
| | | | | | | Init the ddr sdram in TPL instead of SPL, update the code. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
* rockchip: dmc: rk3368: update rank number for evb-px5Kever Yang2019-05-081-0/+4
| | | | | | | evb-px5 has only 1 CS, update for it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
* Revert "rockchip: rk322x: ram: enable DRAM init in SPL instead of TPL"Kever Yang2019-05-081-6/+6
| | | | | | This reverts commit f338cca1d2bce906b049722d2fdbf527a4963b61. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: use 'arch-rockchip' as header file pathKever Yang2019-05-017-40/+40
| | | | | | | | Rockchip use 'arch-rockchip' instead of arch-$(SOC) as common header file path, so that we can get the correct path directly. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* stm32mp1: add trusted boot with TF-APatrick Delaunay2019-04-121-1/+2
| | | | | | | | | | | | | | | Add support of trusted boot, using TF-A as first stage bootloader, The boot sequence is BootRom >=> TF-A.stm32 (clock & DDR) >=> U-Boot.stm32 The TF-A monitor provides secure monitor with support of SMC - proprietary to manage secure devices (BSEC for example) - PSCI for power The same device tree is used for STMicroelectronics boards with basic boot and with trusted boot. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* rockchip: ram: update license for sdram driverKever Yang2019-01-026-6/+6
| | | | | | | | | Rockchip may use this sdram copy of source code for both open source and internal project, update the license to use both GPL2.0+ and BSD-3 Clause. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: rk322x: ram: enable DRAM init in SPL instead of TPLKever Yang2018-12-101-6/+6
| | | | | | | | | Patch for rk322x TPL is not merged, and only SPL is available now, enable the sdram driver in SPL first. We should update back to TPL after TPL is enabled for rk322x. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* ram: MediaTek: add DDR3 driver for MT7629 SoCRyder Lee2018-11-283-0/+774
| | | | | | | | This patch adds a DDR3 driver for MT7629 SoC. Signed-off-by: Wu Zou <wu.zou@mediatek.com> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ram: Introduce K3 AM654 DDR Sub System driverLokesh Vutla2018-11-164-0/+2027
| | | | | | | | | | | | | | | | | K3 based AM654 devices has DDR memory subsystem that comprises Synopys DDR controller, Synopsis DDR phy and wrapper logic to intergrate these blocks into the device. This DDR subsystem provides an interface to external SDRAM devices. Adding support for the initialization of the external SDRAM devices by configuring the DDRSS registers and using the buitin PHY routines. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Schuyler Patton <spatton@ti.com> Signed-off-by: James Doublesin <doublesin@ti.com>
* ram: bmips: Remove DM_FLAG_PRE_RELOC flagBin Meng2018-11-141-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be bound before relocation. However due to a bug in the DM core, the flag only takes effect when devices are statically declared via U_BOOT_DEVICE(). This bug has been fixed recently by commit "dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in lists_bind_fdt()", but with the fix, it has a side effect that all existing drivers that declared DM_FLAG_PRE_RELOC flag will be bound before relocation now. This may expose potential boot failure on some boards due to insufficient memory during the pre-relocation stage. To mitigate this potential impact, the following changes are implemented: - Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver only supports configuration from device tree (OF_CONTROL) - Keep DM_FLAG_PRE_RELOC flag in the driver only if the device is statically declared via U_BOOT_DEVICE() - Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for drivers that support both statically declared devices and configuration from device tree Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* drivers: cosmetic: Convert SPDX license tags to Linux Kernel stylePatrick Delaunay2018-10-282-4/+2
| | | | | | | | | Complete in the drivers directory the work started with commit 83d290c56fab ("SPDX: Convert all of our single license tags to Linux Kernel style"). Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* ram: Add driver for MPC83xxMario Six2018-09-183-0/+1106
| | | | | | | Add a RAM driver for the MPC83xx architecture. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
* bmips: ram: add an option to force the size of the ramPhilippe Reynes2018-08-081-1/+7
| | | | | | | | This adds an option to force the size of the ram, and avoid the detection of ram size. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* ram: bmips: convert to use live dtÁlvaro Fernández Rojas2018-06-011-5/+2
| | | | | | Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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