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path: root/drivers/spi/fsl_qspi.c
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* Merge branch '2021-02-02-drop-asm_global_data-when-unused'Tom Rini2021-02-151-0/+1
|\ | | | | | | - Merge the patch to take <asm/global_data.h> out of <common.h>
| * common: Drop asm/global_data.h from common headerWIP/2021-02-02-drop-asm_global_data-when-unusedSimon Glass2021-02-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* | spi: fsl_qspi: apply the same settings for LS1088 as LS208xMathew McBride2021-02-081-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | The LS1088 requires the same QUADSPI_QURIK_BASE_INTERNAL workaround as the LS208x and also has a 64 byte TX buffer. With the previous settings SPI-NAND reads over AHB were corrupted. Fixes: 91afd36f3802 ("spi: Transform the FSL QuadSPI driver to use the SPI MEM API") Signed-off-by: Mathew McBride <matt@traverse.com.au> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | spi: fsl_qspi: Ensure width is respected in spi-mem operationsMathew McBride2021-02-081-1/+1
|/ | | | | | | | | | | | | | | | | | | Adapted from kernel commit b0177aca7aea From: Michael Walle <michael@walle.cc> Make use of a core helper to ensure the desired width is respected when calling spi-mem operators. Otherwise only the SPI controller will be matched with the flash chip, which might lead to wrong widths. Also consider the width specified by the user in the device tree. Fixes: 91afd36f38 ("spi: Add a driver for the Freescale/NXP QuadSPI controller") Signed-off-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20200114154613.8195-1-michael@walle.cc Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Mathew McBride <matt@traverse.com.au> [adapt for U-Boot] Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* dm: Use access methods for dev/uclass private dataSimon Glass2021-01-051-1/+1
| | | | | | | | | | | Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
* dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass2020-12-131-1/+1
| | | | | | | Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass2020-12-131-1/+1
| | | | | | | | | | We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass2020-12-131-1/+1
| | | | | | | | | | | | This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
* spi: fsl_qspi: Include device_compat.hSean Anderson2020-10-161-4/+5
| | | | | | Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* spi: fsl_qspi: Support to use full AHB space on i.MXYe Li2020-07-161-24/+90
| | | | | | | | | | | | | | | | | | | | i.MX platforms provide large AHB mapped space for QSPI, each controller has 256MB. However, current driver only maps small size (AHB buffer size) of AHB space, this implementation causes i.MX failed to boot M4 with QSPI XIP image. Add config CONFIG_FSL_QSPI_AHB_FULL_MAP (default enabled for i.MX) to address above problem. When the config is set: 1. Full AHB space is divided to each CS. 2. A dedicated LUT entry is used for AHB read only. 3. The MODE instruction in LUT is replaced to standard ADDR instruction 4. The address in spi_mem_op is used to SFAR and AHB read Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: Kuldeep Singh <kuldeep.singh@nxp.com>
* spi: fsl_qspi: Add support for i.MX7ULPYe Li2020-07-161-6/+16
| | | | | | | | | | | | | Add compatible string and driver data for i.MX7ULP. Meanwhile, the address set to SFA1AD/SFA2AD/SFB1AD/SFB2AD should align with 1KB, because the lowest 10 bits are reserved by the registers definition. For i.MX7ULP which has only 128Bytes AHB buffer, must align it when setting the registers and selecting cs. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: Kuldeep Singh <kuldeep.singh@nxp.com>
* common: Drop linux/bitops.h from common headerWIP/2020-05-18-reduce-size-of-common.hSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop linux/delay.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop log.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop image.h from common headerSimon Glass2020-05-181-0/+3
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* spi: Transform the FSL QuadSPI driver to use the SPI MEM APIKuldeep Singh2020-04-291-969/+608
| | | | | | | | | | | | | | | | | | | | | | | | | To support the SPI MEM API, instead of modifying the existing U-Boot driver, this patch adds a port of the existing Linux driver. This also has the advantage that porting changes and fixes from Linux will be easier. Porting of driver left most of the functions unchanged while few of the changes are: -Remove lock(mutexes) and irq handler as u-boot is a single core execution. -Remove invalid masterid as it was required specially for multicore execution in LS2088ARDB which is not the case in u-boot. -Remove clock support as changing spi speed is not supported in uboot and nor in linux. Currently tested on LS1088ARDB, LS1012ARDB, LS1046ARDB, LS1046AFRWY, LS1043AQDS, LS1021ATWR, LS2088ARDB, I.MX6ULL EVK. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
* spi: fsl_qspi: Add support for QSPI on iMX7ULPYe Li2019-10-081-0/+10
| | | | | | Add the compatible string and driver data for iMX7ULP platform Signed-off-by: Ye Li <ye.li@nxp.com>
* spi: fsl_qspi: Update to use driver dataYe Li2019-10-081-34/+79
| | | | | | | Add the driver data for each compatible string. So we can remove the SOC config and use driver data instead. Signed-off-by: Ye Li <ye.li@nxp.com>
* spi: fsl_qspi: Update write data size for page program LUTYe Li2019-10-081-11/+1
| | | | | | | | | The write data size can be overwritten by writing to the IDATSZ field of IPCR register. Since the driver always updates the IDATSZ in page program operation. Set the LUT data size to 0 to align the codes with iMX. Signed-off-by: Ye Li <ye.li@nxp.com>
* spi: fsl_qspi: Fix DDR mode setting for latest iMX platformsYe Li2019-10-081-15/+16
| | | | | | | | | | | | | | On latest iMX platforms like iMX7D/iMX6UL/iMX8MQ, the QSPI controller is updated to have TDH field in FLSHCR register. According to reference manual, this TDH must be set to 1 when DDR_EN is set. Otherwise, the TX DDR delay logic won't be enabled. Another issue in DDR mode is the MCR register will be overwritten in every read/write/erase operation. This causes DDR_EN been cleared while TDH=1, then no clk2x output for TX data shift and all operations will fail. Signed-off-by: Ye Li <ye.li@nxp.com>
* drivers/spi: fsl_qspi: improve timeout calculationThomas Schaefer2019-07-181-11/+6
| | | | | | | | Use readl_poll_timeout instead of explicit calculation Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* drivers/spi: fsl_qspi: fix read timeoutThomas Schaefer2019-07-181-5/+4
| | | | | | | | | | During QSPI reads, current is_controller_busy function sporadically fails with -ETIMEDOUT due to fixed number of 5 test loops. Using timer functions to wait 1000 us instead will fix this. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* driver/spi: fsl_qspi: Remove non-DM stuffAshish Kumar2018-10-021-138/+0
| | | | | | | | | Convert fsl_qspi.c to complete DM mode. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Tested-by: Rajat Srivastava <rajat.srivastava@nxp.com> Tested-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* spi: fsl_qspi: remove superfluous assignmentHeinrich Schuchardt2018-05-161-1/+1
| | | | | | | | | | | | In void *rx_addr = NULL; rx_add = A; the first assignment has no effect. Remove it. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
* spi: fsl_qspi: Introduce is_controller_busy functionRajat Srivastava2018-05-091-10/+21
| | | | | | | | | | Some SoCs have different endianness of QSPI IP if compared to endianness of core. The function is_controller_busy() checks if the QSPI controller is busy or not, considering the endianness of the QSPI IP. Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini2018-05-071-2/+1
| | | | | | | | | | | | | | | | | | | | When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-spiTom Rini2018-01-261-10/+10
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| * wait_bit: use wait_for_bit_le32 and remove wait_for_bitÁlvaro Fernández Rojas2018-01-241-10/+10
| | | | | | | | | | | | | | | | wait_for_bit callers use the 32 bit LE version Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | spi: fsl_qspi: support i.MX6UL/6ULLL/7DPeng Fan2018-01-121-2/+16
|/ | | | | | | | | | | | | The QSPI module on i.MX7D is modified from i.MX6SX. The module used on i.MX6UL/6ULL is reused from i.MX7D. They share same tx buffer size. The endianness is not set at qspi driver initialization. So if we don't boot from QSPI, we will get wrong endianness when accessing from AHB address directly. Add the compatible entry for 6ul/7d. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* spi: fsl_qspi: Copy 16 byte aligned data in TX FIFOSuresh Gupta2017-09-251-10/+8
| | | | | | | | | | | | | | | In some of the QSPI controller version, there must be atleast 128bit data available in TX FIFO for any pop operation otherwise error bit will be set. The code will not make any behavior change for previous controller as the transfer data size in ipcr register is still the same. Patch is tested on LS1046A which do not require 16 bytes aligned and LS1088A which require 16 bytes aligned data in TX FIFO Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Anupam Kumar <anupam.kumar_1@nxp.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* spi: fsl_qspi: Add controller busy check before new spi operationSuresh Gupta2017-09-251-1/+27
| | | | | | | | | | | It is recommended to check either controller is free to take new spi action. The IP_ACC and AHB_ACC bits indicates that the controller is busy in IP or AHB mode respectively. And the BUSY bit indicates that controller is currently busy handling a transaction to an external flash device Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* spi: fsl_qspi: Pet watchdog even moreAlexander Stein2017-08-011-0/+8
| | | | | | | | | | Pet the watchdog once upon each command call (qspi_xfer) and during each loop iteration in several commands. This fixes a watchdog reset especially during erase command. Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com> Reviewed-by: York Sun <york.sun@nxp.com>
* spi: fsl_qspi: Add support for single chip selectSuresh Gupta2017-03-281-1/+4
| | | | | | | | SOC’s like LS1012A has only one chip select signal for QSPI flash. Avoid scanning other flash. Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* dm: core: Replace of_offset with accessorSimon Glass2017-02-081-1/+1
| | | | | | | | | At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
* libfdt: Sync fdt_for_each_subnode() with upstreamSimon Glass2016-10-131-1/+1
| | | | | | | | | | | The signature for this macro has changed. Bring in the upstream version and adjust U-Boot's usages to suit. Signed-off-by: Simon Glass <sjg@chromium.org> Update to drivers/power/pmic/palmas.c: Signed-off-by: Keerthy <j-keerthy@ti.com> Change-Id: I6cc9021339bfe686f9df21d61a1095ca2b3776e8
* spi: fsl_qspi: Preserve endianness of QSPI MCRYork Sun2016-10-061-2/+8
| | | | | | | | | | | The endianness can be changed by RCW + PBI sequence. It may have other than power on reset value. Signed-off-by: York Sun <york.sun@nxp.com> CC: Yuan Yao <yao.yuan@nxp.com> CC: Peng Fan <peng.fan@nxp.com> CC: Alison Wang <alison.wang@nxp.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* driver: spi: fsl-qspi: remove compile WarningsYunhui Cui2016-08-021-1/+3
| | | | | | | | | | Warnins log: drivers/spi/fsl_qspi.c: In function ‘qspi_ahb_read’: drivers/spi/fsl_qspi.c:400:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len); Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* spi: fsl_qspi: Enable Spansion S25FS-S family flashesYuan Yao2016-05-181-6/+52
| | | | | | | | | | The flash type of LS2085AQDS QSPI is S25FS256S. It has special write any device register command and read any device register command. This patch enable support for those commands. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* spi: fsl_qspi: Assign AMBA mem according CS num in dtsYuan Yao2016-05-181-12/+43
| | | | | | | | | | | QSPI controller automatic enable the chipselect signal according the dest AMBA memory address. Now we distribute the AMBA memory zone averagely to every chipselect slave device according chipselect numbers got from dts node. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* spi: fsl_qspi: Fix issues on arm64Yuan Yao2016-05-181-19/+27
| | | | | | | | | | | The address value and size value get from dts "reg" property have type of u64 on arm64. If we assign those values to "u32" variables, driver can't work correctly. Converting the type of those variables to fdt_xxx_t. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* spi: fsl_qspi: Fix qspi_op_rdsr memcpy issueGong Qianyu2016-01-271-3/+3
| | | | | | | | | | In current driver, we always copy 4 bytes to the dest memory. Actually the dest memory may be shorter than 4 bytes. Add an argument to indicate the dest memory length. Avoid writing memory outside of the bounds. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* spi: fsl_qspi: Fix qspi_op_rdid memcpy issueGong Qianyu2016-01-271-6/+6
| | | | | | | | | | | In current driver everytime we memcpy 4 bytes to the dest memory regardless of the remaining length. This patch adds checking the remaining length before memcpy. If the length is shorter than 4 bytes, memcpy the actual length of data to the dest memory. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* spi: fsl_qspi: fix compile warning for 64-bit platformGong Qianyu2016-01-271-1/+1
| | | | | | | | | | | | | | This patch fixes the following compile warning: drivers/spi/fsl_qspi.c: In function 'fsl_qspi_probe': drivers/spi/fsl_qspi.c:937:15: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] priv->regs = (struct fsl_qspi_regs *)plat->reg_base; ^ Just make the cast explicit. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* spi: fsl_qspi: fix an error of using GENMASKGong Qianyu2016-01-071-1/+1
| | | | | | | | | This commit fixes the change of below commit "spi: fsl_qspi: Use GENMASK" (sha1 :bad490a24212c068c5b718b9189f47ea4075d078) Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* fsl_qspi: Pet the watchdog while reading/writingAlexander Stein2015-12-151-0/+5
| | | | | | | | | When reading a large blob. e.g. a linux kernel (several MiBs) a watchdog timeout might occur meanwhile. So pet the watchdog while operating on the flash. Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-10-281-3/+3
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| * spi: fsl_qspi: Use GENMASKJagan Teki2015-10-271-1/+1
| | | | | | | | | | | | | | | | | | Replace numeric mask hexcodes with GENMASK macro in fsl_qspi Cc: York Sun <yorksun@freescale.com> Cc: Haikun Wang <Haikun.Wang@freescale.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: fsl: Use BIT macroJagan Teki2015-10-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Replace numerical bit shift with BIT macro in fsl_*spi.c :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: York Sun <yorksun@freescale.com> Cc: Haikun Wang <Haikun.Wang@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* | dm: Rename dev_get_parentdata() to dev_get_parent_priv()Simon Glass2015-10-231-1/+1
|/ | | | | | | | The current name is inconsistent with other driver model data access functions. Rename it and fix up all users. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* dm: spi: Convert Freescale QSPI driver to driver modelHaikun.Wang@freescale.com2015-04-181-329/+656
| | | | | | | | | Move the Freescale QSPI driver over to driver model. Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Tested-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Simon Glass <sjg@chromium.org>
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