summaryrefslogtreecommitdiff
path: root/drivers/timer
Commit message (Collapse)AuthorAgeFilesLines
* treewide: convert devfdt_get_addr() to dev_read_addr()Masahiro Yamada2020-07-254-4/+4
| | | | | | | | | | | | | | | | | | | | When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"Tom Rini2020-07-244-4/+4
| | | | | | | | | | This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com>
* treewide: convert devfdt_get_addr() to dev_read_addr()Masahiro Yamada2020-07-204-4/+4
| | | | | | | | | | | | | | | | | | | | When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* common: Drop linux/bitops.h from common headerWIP/2020-05-18-reduce-size-of-common.hSimon Glass2020-05-189-0/+9
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop linux/delay.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop asm/ptrace.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop log.h from common headerSimon Glass2020-05-183-0/+3
| | | | | | Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop init.h from common headerSimon Glass2020-05-183-0/+3
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop bootstage.h from common headerSimon Glass2020-05-183-0/+3
| | | | | | Move this fairly uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* timer MediaTek use upstream compatibleMatthias Brugger2020-05-011-0/+1
| | | | | | | The timers compatible string in upstream is called mt6577-timer. Add this compatible to the driver. Signed-off-by: Matthias Brugger <mbrugger@suse.com>
* timer: sti: use clk API to get timer clock rateNicolas Heemeryck2020-03-241-2/+15
| | | | | | | | | Retrieve clock rate through device tree. This mimics the behavior of arm_global_timer in Linux. Signed-off-by: Nicolas Heemeryck <nicolas.heemeryck@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
* timer: sti: convert to livetreeNicolas Heemeryck2020-03-241-6/+3
| | | | | | | | Update STI timer to support a live tree Signed-off-by: Nicolas Heemeryck <nicolas.heemeryck@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
* dm: core: Create a new header file for 'compat' featuresSimon Glass2020-02-053-0/+4
| | | | | | | | | | | | At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: core: Require users of devres to include the headerSimon Glass2020-02-053-0/+3
| | | | | | | | | | At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
* timer: Add driver for Nomadik Multi Timer Unit (MTU)Stephan Gerhold2020-01-223-0/+124
| | | | | | | | | | The Nomadik Multi Timer Unit (MTU) provides 4 decrementing free-running timers. It is used in ST-Ericsson Ux500 SoCs. The driver uses the first timer to implement UCLASS_TIMER. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* x86: timer: Reduce timer code size in TPL on Intel CPUsSimon Glass2019-12-152-2/+14
| | | | | | | | | | | | | | | Most of the timer-calibration methods are not needed on recent Intel CPUs and just increase code size. Add an option to use the known-good way to get the clock frequency in TPL. Size reduction is about 700 bytes. Note that version 1 of this commit caused bootstage to crash since the CPU was not identified. This is corrected by changes previously applied to make sure that the CPU is identified before spl_init() is called, such as 39146a2e0b x86: Move CPU init to before spl_init() Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: timer: use a timer base of 0Simon Glass2019-12-152-1/+16
| | | | | | | | | | | | | | | | On x86 platforms the timer is reset to 0 when the SoC is reset. Having this as the timer base is useful since it provides an indication of how long it takes before U-Boot is running. When U-Boot sets the timer base to something else, time is lost and we no-longer have an accurate account of the time since reset. This particularly affects bootstage. Change the default to not read the timer base, leaving it at 0. Add an option for when U-Boot is the secondary bootloader. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* common: Move interrupt functions into a new headerSimon Glass2019-12-021-0/+1
| | | | | | | | | | | | These functions do not use driver model but are fairly widely used in U-Boot. But it is not clear that they will use driver model anytime soon, so we don't want to label them as 'legacy'. Move them to a new irq_func.h header file. Avoid the name 'irq.h' since it is widely used in U-Boot already. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* common: Move get_ticks() function out of common.hSimon Glass2019-12-021-0/+1
| | | | | | | This function belongs in time.h so move it over and add a comment. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* common: Move wait_ticks functions out of common.hSimon Glass2019-12-021-0/+1
| | | | | | | This function belongs in time.h so move it over and add a comment. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* common: Drop global inclusion of status_led.hSimon Glass2019-12-021-0/+1
| | | | | | | | This is only used by a few files so it should not be in the common header. Move it out. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* Drop CONFIG_SHOW_ACTIVITYSimon Glass2019-12-021-4/+0
| | | | | | This feature is not enabled by any board. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
* timer: dw-apb: add reset handlingSimon Goldschmidt2019-11-201-1/+17
| | | | | | | To use this DM timer on socfpga as system tick, it needs to take itself out of reset. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* x86: timer: Use a separate flag for whether timer is initedSimon Glass2019-11-031-1/+2
| | | | | | | | | | | | | | At present the value of the timer base is used to determine whether the timer has been set up or not. It is true that the timer is essentially never exactly 0 when it is read. However 'time 0' may indicate the time that the machine was reset so it is useful to be able to denote that. Update the code to use a separate flag instead. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: timer: Set up the timer in timer_early_get_count()Simon Glass2019-11-031-0/+2
| | | | | | | | | | This function can be called before the timer is set up. Make sure that the init function is called so that it works correctly. This is needed so that bootstage can work correctly in TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: timer: Skip device that does not have a valid ofnode in pre_probe()Bin Meng2019-07-241-0/+4
| | | | | | | | It is possible that a timer device has a null ofnode, hence there is no need to further parse DT for the clock rate. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* timer: dw-apb: remove unused DECLARE_GLOBAL_DATA_PTRSimon Goldschmidt2019-05-101-2/+0
| | | | | | The dw-apb timer does not use 'gd', so remove its declaration. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* timer: renesas: Add RZ/A1 R7S72100 OSTM timer driverMarek Vasut2019-05-073-0/+100
| | | | | | | | | | Add OSTM timer driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* rockchip: use 'arch-rockchip' as header file pathKever Yang2019-05-011-1/+1
| | | | | | | | Rockchip use 'arch-rockchip' instead of arch-$(SOC) as common header file path, so that we can get the correct path directly. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* Merge tag 'u-boot-amlogic-20190423' of git://git.denx.de/u-boot-amlogicTom Rini2019-04-241-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | - Add support for Amlogic p200 & p201 Reference Designs - Add Amlogic SoC information display - Add support for the Libretech-AC AML-S805X-AC board - Add Amlogic AXG reset compatible - Add I2C support for Amlogic AXG - Fix AXG PIN and BANK pinctrl definitions - Fix regmap_read_poll_timeout warning about sandbox_timer_add_offset - Add initial support for Amlogic G12A SoC and U200 board - Enable PHY_REALTEK for selected boards - Fix Khadas VIM2 README
| * regmap: fix regmap_read_poll_timeout warning about sandbox_timer_add_offsetNeil Armstrong2019-04-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When fixing sandbox test for regmap_read_poll_timeout(), the sandbox_timer_add_offset was introduced but only defined in sandbox code thus generating warnings when used out of sandbox : include/regmap.h:289:2: note: in expansion of macro 'regmap_read_poll_timeout_test' regmap_read_poll_timeout_test(map, addr, val, cond, sleep_us, \ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/spi/meson_spifc.c:169:8: note: in expansion of macro 'regmap_read_poll_timeout' ret = regmap_read_poll_timeout(spifc->regmap, REG_SLAVE, data, ^~~~~~~~~~~~~~~~~~~~~~~~ drivers/spi/meson_spifc.c: In function 'meson_spifc_txrx': include/regmap.h:277:4: warning: implicit declaration of function 'sandbox_timer_add_offset' [-Wimplicit-function-declaration] This fix adds a timer_test_add_offset() only defined in sandbox, and renames the previous sandbox_timer_add_offset() to it. Cc: Simon Glass <sjg@chromium.org> Reported-by: Tom Rini <trini@konsulko.com> Fixes: df9cf1cc08 ("test: dm: regmap: Fix the long test delay") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | timer: dw-apb: Add missing 64bit up-conversionMarek Vasut2019-04-171-1/+1
|/ | | | | | | | | | | | | | | | | | The generic timer count is an incrementing 64bit value and a timer driver must return an incrementing 64bit value. The DW APB timer only provides a 32bit timer counting down, thus the result must be inverted and converted to a 64bit value. The current implementation is however missing the 64bit up-conversion and this results in random timer roll-overs, which in turn triggers random timeouts throughout the codebase. This patch adds the missing 64bit up-conversion to fix the issue. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
* x86: tsc: Add support for native calibration of TSC freqBernhard Messerklinger2019-02-121-0/+55
| | | | | | | | | | | Add native tsc calibration function. Calibrate the tsc timer the same way as linux does in arch/x86/kernel/tsc.c. Fixes booting for Apollo Lake processors. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* timer: Add generic driver for RISC-V privileged architecture defined timerBin Meng2018-12-183-0/+64
| | | | | | | | | | | | | | | | | | | | | | RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
* timer: MediaTek: add timer driver for MediaTek SoCsRyder Lee2018-11-283-0/+93
| | | | | | | | | This patch adds clock source and clock event for the timer found on the Mediatek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* timer: Remove DM_FLAG_PRE_RELOC flag in various driversBin Meng2018-11-1414-14/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be bound before relocation. However due to a bug in the DM core, the flag only takes effect when devices are statically declared via U_BOOT_DEVICE(). This bug has been fixed recently by commit "dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in lists_bind_fdt()", but with the fix, it has a side effect that all existing drivers that declared DM_FLAG_PRE_RELOC flag will be bound before relocation now. This may expose potential boot failure on some boards due to insufficient memory during the pre-relocation stage. To mitigate this potential impact, the following changes are implemented: - Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver only supports configuration from device tree (OF_CONTROL) - Keep DM_FLAG_PRE_RELOC flag in the driver only if the device is statically declared via U_BOOT_DEVICE() - Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for drivers that support both statically declared devices and configuration from device tree Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* timer: Sort Kconfig driver entriesBin Meng2018-11-141-55/+55
| | | | | | | This is currently out of order. Sort it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in lists_bind_fdt()Bin Meng2018-11-141-1/+1
| | | | | | | | | | | | | | | | | | | | Currently the comments of several APIs (eg: dm_init_and_scan()) say: @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC flag. If false bind all drivers. The 'Pre-Relocation Support' chapter in doc/driver-model/README.txt documents the same that both device tree properties and driver flag are supported. However the implementation only checks these special device tree properties without checking the driver flag at all. This updates lists_bind_fdt() to consider both scenarios. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Squashed in http://patchwork.ozlabs.org/patch/996473/ : Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: tsc: Introduce config option for early timer frequencyBin Meng2018-10-222-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | So far the TSC timer driver supports trying hardware calibration first and using device tree as last resort for its running frequency as the normal timer. However when it is used as the early timer, it only supports hardware calibration and if it fails, the driver just panics. This introduces a new config option to specify the early timer frequency in MHz and it should be equal to the value described in the device tree. Without this patch, the travis-ci testing on QEMU x86_64 target fails each time after it finishes the 'bootefi selftest' as the test.py see an error was emitted on the console like this: TSC frequency is ZERO resetting ... ### ERROR ### Please RESET the board ### It's strange that this error is consistently seen on the travis-ci machine, but only occasionally seen on my local machine (maybe 1 out of 10). Since QEMU x86_64 target enables BOOTSTAGE support which uses early timer, with this fix it should work without any failure. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Enable CONFIG_TIMER_EARLY with bootstageSimon Glass2018-10-221-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In initr_bootstage() we call bootstage_mark_name() which ends up calling timer_get_us(). This call happens before initr_dm(), which inits driver model. On x86 we set gd->timer to NULL in the transition from board_init_f() to board_init_r(). See board_init_f_r() for this assignment. So U-Boot knows there is no timer available in the period immediately after relocation. On x86 the timer_get_us() call is implemented as calls to get_ticks() and get_tbclk(). Both of these call dm_timer_init() to set up the timer, if gd->timer is NULL and the early timer is not available. However dm_timer_init() cannot succeed before initr_dm() is called. So it seems that on x86 if we want to use CONFIG_BOOTSTAGE we must enable CONFIG_TIMER_EARLY. Update the Kconfig to handle this. Note: On most architectures we can rely on the pre-relocation memory still being available, so that gd->timer pointers to a valid timer device and everything works correctly. Admittedly this is not strictly correct since the timer device is set up by pre-relocation U-Boot, but normally this is fine. On x86 the 'CAR' (cache-as-RAM) memory used by pre-relocation U-Boot disappears in board_init_f_r() and any attempt to access it will hang. This is the reason why we must mark the timer as invalid when we get to board_init_f_r(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* timer: Add MPC83xx timer driverMario Six2018-09-183-0/+257
| | | | | | Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc>
* timer: Sort Makefile entriesMario Six2018-09-181-8/+8
| | | | | | Makefile entries should be sorted. Signed-off-by: Mario Six <mario.six@gdsys.cc>
* dm: omap-timer: Update clock rate only if not populatedLokesh Vutla2018-09-101-1/+2
| | | | | | | | | timer_pre_probe() tries to populate the clock rate from DT. omap timer driver tries to overwrite this value irrespective of the value populated fro DT. So update this value only when DT doesn't populate the clock rate. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* dm: omap-timer: Use 64bit for counter valuesLokesh Vutla2018-09-101-1/+2
| | | | | | | In order to handle counter overflows use 64 bit values for counter. Also load the initial value during probe. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* timer: dw-apb: Add Designware APB timer driverMarek Vasut2018-08-243-0/+98
| | | | | | | | | | Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
* x86: tsc: Try hardware calibration firstBin Meng2018-08-201-11/+16
| | | | | | | | | | | | | At present if TSC frequency is provided in the device tree, it takes precedence over hardware calibration result. This swaps the order to try hardware calibration first and uses device tree as last resort. This can be helpful when a generic dts (eg: coreboot/efi payload) is supposed to work on as many hardware as possible, including emulators like QEMU where TSC hardware calibration sometimes fails. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
* x86: timer: tsc: Allow specifying clock rate from device tree againBin Meng2018-07-021-2/+11
| | | | | | | | | | | | | | With the introduction of early timer support in the TSC driver, the capability of getting clock rate from device tree was lost unfortunately. Now we bring such functionality back, but with a limitation that when TSC is used as early timer, specifying clock rate from device tree does not work. This fixes random boot failures seen on QEMU targets: printing "TSC frequency is ZERO" and reset forever. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* timer: cadence: Implement timer_get_boot_usMichal Simek2018-06-151-0/+22
| | | | | | | This function is required for adding bootstage support. Also enable it directly for ZynqMP R5 configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* x86: tsc: add support for reading CPU freq from cpuidChristian Gmeiner2018-06-131-5/+24
| | | | | | | | | | | | Starting with cpuid level 0x16 (Skylake-based processors) it is possible to get CPU base freq via cpuid. This fixes booting on a skylake based system. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed wrong indention of labels] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* timer: cadence: Use live-tree functionsMichal Simek2018-05-311-1/+3
| | | | | | | | Use live-tree functions. Reported-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
View Lorry Controller Status