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* nand: Remove unused ppc4xx NAND driver and referencesStefan Roese2018-03-193-217/+0
| | | | | | | | | ppc4xx support was removed some time ago. Lets remove the now unused NAND driver and all its references for this platform as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Cc: Scott Wood <oss@buserror.net>
* clk: stm32mp1: add clock tree initializationPatrick Delaunay2018-03-191-0/+576
| | | | | | add binding and code for clock tree initialization from device tree Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* clk: add driver for stm32mp1Patrick Delaunay2018-03-193-0/+1166
| | | | | | | | | add RCC clock driver for STMP32MP157 - base on driver model = UCLASS_CLK - support ops to enable, disable and get rate of all SOC clock needed by U-Boot Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* reset: stm32: adapt driver for stm32mp1Patrick Delaunay2018-03-192-7/+31
| | | | | | | - move to livetree and allow to get address to parent - add stm32mp1 compatible for probe Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* pinctrl: stm32: update pincontrol for stmp32mp157Patrick Delaunay2018-03-191-2/+7
| | | | | | | | | - add the 2 new compatible used by STM32MP157 "st,stm32mp157-pinctrl" "st,stm32mp157-z-pinctrl" - update the mask for the port Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* pmic: add stpmu1 supportPatrick Delaunay2018-03-193-0/+71
| | | | | | | | | | This driver implements register read/write operations for STPMU1. The STPMU1 PMIC provides 4 BUCKs, 6 LDOs, 1 VREF and 2 power switches. It is accessed via an I2C interface. This device is used with STM32MP1 SoCs. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* ram: stm32mp1: add driverPatrick Delaunay2018-03-198-0/+1291
| | | | | | Add driver and binding for stm32mp1 ddr controller and phy Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* arm: stm32: add new architecture for STM32MP familyPatrick Delaunay2018-03-193-5/+5
| | | | | | | | | | | - add new arch stm32mp for STM32 MPU/Soc based on Cortex A - support for stm32mp157 SOC - SPL is used as first boot stage loader - using driver model for all the drivers, even in SPL - all security feature are deactivated (ETZC and TZC) - reused STM32 MCU drivers when it is possible Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* stm32mp: stm32f7_i2c: use calloc instead of kmallocPatrick Delaunay2018-03-191-2/+2
| | | | | | | | | Kmalloc is using memalign allocation function. It is not necessary to align this structure so to save bytes, we move to calloc. And kmalloc function can't be used in SPL early stage (in board_init_f()) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* gpio: stm32f7_gpio: handle node ngpiosPatrick Delaunay2018-03-191-1/+2
| | | | Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* dm: gpio: Convert stm32f7 driver to livetreePatrick Delaunay2018-03-191-9/+3
| | | | | | | Update the GPIO driver to support a live device tree. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* spl: add SPL_RESET_SUPPORTPatrick Delaunay2018-03-191-0/+1
| | | | | | | | Add option to include RESET driver and uclass in SPL. That can be useful to handle IP reset with same driver in U-Boot and in SPL. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* video: stm32: stm32_ltdc: set the blending factoryannick fertre2018-03-191-6/+35
| | | | | | Set the blending factor regarding the pixel format Signed-off-by: yannick fertre <yannick.fertre@st.com>
* video: stm32: stm32_ltdc: missing set of line interrupt positionyannick fertre2018-03-191-0/+2
| | | | | | Set LIPCR (line interrupt position conf) register with line length. Signed-off-by: yannick fertre <yannick.fertre@st.com>
* video: stm32: stm32_ltdc: set rate of the pixel clockyannick fertre2018-03-191-23/+29
| | | | | | pxclk is useless to set pixel clock. Signed-off-by: yannick fertre <yannick.fertre@st.com>
* video: stm32: stm32_ltdc: update file header & footeryannick fertre2018-03-191-9/+8
| | | | | | Modified copyright & driver name. Signed-off-by: yannick fertre <yannick.fertre@st.com>
* video: stm32: stm32_ltdc: add resetyannick fertre2018-03-191-0/+11
| | | | | | Add reset of LTDC display controller. Signed-off-by: yannick fertre <yannick.fertre@st.com>
* video: exynos: remove redundant assignmentsHeinrich Schuchardt2018-03-191-6/+6
| | | | | | No need to initialize variables if the next usage is an assignment. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* video, da8xx-fb: fix time out in wait_for_event()Heinrich Schuchardt2018-03-191-2/+3
| | | | | | If an event does not occur the current coding stays in an endless loop. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* video: stb_truetype: simplify expressionHeinrich Schuchardt2018-03-191-1/+1
| | | | | | Eliminate (x2 - x2) which is always zero. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* video: cfb_console: simplify logical constraintHeinrich Schuchardt2018-03-191-1/+1
| | | | | | (A || !A && B) == (A || B) Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* Convert all of CONFIG_CONS_INDEX to KconfigTom Rini2018-03-161-8/+40
| | | | | | | | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_CONS_INDEX We have existing entries for this option in a number of places, with different guards on them. They're also sometimes used for things not directly inside of the serial driver. First, introduce a new symbol to guard the use of CONFIG_CONS_INDEX, so that in the case where we don't need this for the serial driver, but for some other use, we can still do it. Next, consolidate all of these into the single entry in drivers/serial/Kconfig. Finally, introduce CONS_INDEX_[023456] so that we can imply a correct value here to make the defconfig side of this smaller. Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Rework a lot of the logic here, such that I took authorship from Adam, but kept his S-o-B line] Signed-off-by: Tom Rini <trini@konsulko.com>
* watchdog: omap_wdt: improve watchdog reset pathRuslan Bilovol2018-03-161-6/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove busy looping during watchdog reset. Each polling of W_PEND_WTGR bit ("finish posted write") after watchdog reset takes 120-140us on BeagleBone Black board. Current U-Boot code has watchdog resets in random places and often there is situation when watchdog is reset few times in a row in nested functions. This adds extra delays and slows the whole system. Instead of polling W_PEND_WTGR bit, we skip watchdog reset if the bit is set. Anyway, watchdog is in the middle of reset *right now*, so we can just return. This noticeably increases performance of the system. Below are some measurements on BBB: - DFU upload over USB 15% faster - fastboot image upload 3x times faster - USB ep0 transfers with 4k packets 20% faster Signed-off-by: Ruslan Bilovol <ruslan.bilovol@gmail.com> Tested-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> Tested-by: Alex Kiernan <alex.kiernan@gmail.com>
* clk: at91: clk-system: add set/get_rate operationsWenyou Yang2018-03-161-0/+26
| | | | | | To support set/get the clock rate, add set/get_rate operations. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
* clk: at91: add PLLADIV driverWenyou Yang2018-03-162-1/+89
| | | | | | | | As said in the SAMA5D2 datasheet, the PLLA clock must be divided by 2 by writing the PLLADIV2 bit in PMC_MCKR, if the ratio between PCK and MCK is 3 (MDIV = 3). This is the purpose of the driver. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
* clk: at91: add USB Host clock driverWenyou Yang2018-03-163-0/+155
| | | | | | | | Add USB clock driver to configure the input clock and the divider in the PMC_USB register to generate a 48MHz and a 12MHz signal to the USB Host OHCI. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
* Merge git://git.denx.de/u-boot-spiTom Rini2018-03-156-427/+25
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| * spi: omap3: Fix redeclared errorJagan Teki2018-03-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | omap3_spi_set_speed|mode redeclared bus symbol, fix the same. error: drivers/spi/omap3_spi.c: In function ‘omap3_spi_set_speed’: drivers/spi/omap3_spi.c:650:18: error: ‘bus’ redeclared as different kind of symbol struct udevice *bus = dev->parent; Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * arm: sunxi: Move spl spi sunxi code to mach-sunxiJagan Teki2018-03-133-326/+0
| | | | | | | | | | | | | | | | | | | | | | | | This SUNXI variant SPL SPI code doesn't use either SPI or SPL_FLASG subsystems due to size constraints and also placing this code in drivers/mtd/spi will unnecessary build SPI_FLASH code(if defined) which never required, hence moved to arch area. And also renamed the file according to kconfig which resembles proper name. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: omap3: Skip set_mode, set_speed from claimJagan Teki2018-03-131-5/+16
| | | | | | | | | | | | | | | | set_mode, set_seed functions has separate function pointers in dm_spi_ops, so use them in relevent one instead of calling from claim_bus. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: atcspi200: Drop non-dm codeJagan Teki2018-03-132-94/+7
| | | | | | | | | | | | | | | | Boards adp-ae3xx_defconfig, nx25-ae250_defconfig already enabled DM_SPI, so non-dm code make no use of it hence droped. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* | Merge git://git.denx.de/u-boot-sunxiTom Rini2018-03-143-3/+16
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| * | Move CONFIG_PHY_ADDR to KconfigStefan Mavrodiev2018-03-131-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_PHY_ADDR is used for old-style configuration. This makes impossible changing the PHY address, if multiple boards share a same config header file (for example include/configs/sunxi-common.h). Moving this to Kconfig helps overcoming this issue. It's defined as entry inside PHYLIB section. After the implemention, moveconfig was run. The issues are: - edb9315a - CONFIG_PHYLIB is not enabled. Entry is deleted. - ds414 - CONFIG_PHYLIB is in incompatible format: { 0x1, 0x0 }. This entry is also deleted. - devkit3250 - The PHY_ADDR is in hex format (0x1F). Manually CONFIG_PHY_ADDR=31 is added in the defconfig. After the changes the suspicious defconfigs passes building. Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> [jagan: rebased on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | net: sun8i_emac: Fix PHY initializationSamuel Holland2018-03-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous code tried to update the PHY parameters without waiting for autonegotiation to complete. This caused wrong values to be written to the EMAC in sun8i_adjust_link(). As a result, any commands that called eth_start() before autonegotiation completed would find the network nonfunctional. Fix this by using the correct function to start up the PHY. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | mmc: sunxi: support cd-invertedHeinrich Schuchardt2018-03-131-2/+8
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With CONFIG_DM_MMC the BananaPi does not detect SD cards. The sunxi device trees use the cd-inverted property to indicate that the card detect is inverted. This property is documented in Linux kernel devicetree/bindings/mmc/mmc.txt The property is not marked as deprecated. A similar patch was posted by Tuomas but is in status "Changes Requested". https://patchwork.ozlabs.org/patch/850377/ This patch is a stripped down version of his patch. Suggested-by: Tuomas Tynkkynen <tuomas@tuxera.com> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | arch-stm32: Factorize stm32.h for STM32F4 and F7Patrice Chotard2018-03-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | For STM32F4 and F7 SoCx family, a specific stm32.h file exists. Some common defines are duplicated or even unused in each of these stm32.h. Factorize all common definition in arch/arm/include/asm/stm32f.h and keep specific definitions in each arch/arm/include/asm/arch-stm32fx/stm32.h. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | clk: clk_stm32f: Add DSI clock supportPatrice Chotard2018-03-131-1/+1
| | | | | | | | | | | | | | | | DSI clock is available on STM32F769-disco and STM32F469-disco board. Signed-off-by: Yannick Fertre <yannick.fertre@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | clk: clk_stm32f: Add set_rate for LTDC clockPatrice Chotard2018-03-131-0/+100
| | | | | | | | | | | | | | | | Implement set_rate() for LTDC clock only, set_rate for other clocks will be added if needed. This is needed by future LTDC driver improvements. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | clk: clk_stm32f: Configure SAI PLL to generate LTDC pixel clockPatrice Chotard2018-03-131-1/+36
| | | | | | | | | | | | | | | | | | Configure SAI PLL configuration to generate LTDC pixel clock on the PLLSAIR output. PLLSAI is enabled only if CONFIG_VIDEO_STM32 flag is set. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | clk: clk_stm32f: Rework SDMMC stm32_clk_get_rate() partPatrice Chotard2018-03-131-31/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | Rework the way SDMMC clock get rate is done in a more generic way : _ Add stm32_clk_get_pllsai_rate() which give the PLLSAI indicated output rate. _ Add stm32_clk_get_pllsai_vco_rate() which give the VCO internal rate. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | clk: clk_stm32f: No more need of 48Mhz from PLL_SAIPatrice Chotard2018-03-131-21/+8
| | | | | | | | | | | | | | | | | | | | | | Initially, 48Mhz for SDIO clock was generated from SAI pll for STM32F469 and STM32F746 SoCs, but this solution was not suitable for STM32F429 SoCs. A generic solution is to used the PLL_Q output as 48Mhz clock for all STM32F SOCs family. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | clk: clk_stm32f: Fix RCC_PLLSAICFGR mask definesPatrice Chotard2018-03-131-4/+4
| | | | | | | | | | | | Use the correct name for RCC_PLLSAICFGR_PLLSAIx_MASK masks. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | clk: clk_stm32f: Fix stm32_clk_get_rate()Patrice Chotard2018-03-131-5/+7
| | | | | | | | | | | | | | Wrong parameter was passed to stm32_clk_pll48clk_rate(). sysclk (PLL_p output value) was passed instead of VCO value. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | mmc: stm32: sdmmc2: add support for st, pin-ckinsdmmc_ckinPatrick Delaunay2018-03-131-1/+6
| | | | | | | | | | | | | | | | | | | | This patch adds "st,pin-ckin" support to activate sdmmc_ckin feature. When using an external driver (a voltage switch transceiver), it's advised to select SDMMC_CKIN feedback clock input to sample the received data. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | mmc: stm32: sdmmc2: add hardware flow control supportPatrick Delaunay2018-03-131-1/+2
| | | | | | | | | | | | | | | | | | | | The hardware flow control functionality is used to avoid FIFO underrun (TX mode) and overrun (RX mode) errors. The behavior is to stop SDMMC_CK during data transfer and freeze the SDMMC state machines. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | board: stm32: switch to DM STM32 timerPatrice Chotard2018-03-132-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | Use available DM stm32_timer driver instead of dedicated mach-stm32/stm32fx/timer.c. Remove all defines or files previously used for timer usage in arch/arm/include/asm/arch-stm32fx and in arch/arm/mach-stm32/stm32fx Enable DM STM32_TIMER for STM32F4/F7 and H7. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | clk: clk_stm32h7: Fix prescaler for Domain 3Patrice Chotard2018-03-131-3/+4
| | | | | | | | | | | | | | d1cfgr register was used to calculate the domain 3 prescaler value instead of d3cfgr. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | clk: clk_stm32h7: Fix stm32_clk_get_rate() for timerPatrice Chotard2018-03-131-12/+90
| | | | | | | | | | | | | | For timer clock, an additional prescaler is used which was not taken into account previously. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | clk: clk_stm32f: Fix stm32_clk_get_rate() for timerPatrice Chotard2018-03-131-17/+99
| | | | | | | | | | | | | | For timer clock, an additionnal prescaler is used which was not taken into account previously. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | timer: stm32: Add timer support for STM32 SoCs familyPatrice Chotard2018-03-133-0/+146
| | | | | | | | | | | | | | | | This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
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