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* dra7xx: Add dra72_evm_defconfig using CONFIG_DMTom Rini2015-08-121-0/+1
| | | | | | | | | | - Import various DT files for DRA7 / DR72x / dra72-evm from Linux Kernel v4.1 - Add config file for this board, enable DM and DM_GPIO Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* gpio: omap: Drop 'method' parameterTom Rini2015-08-121-48/+59
| | | | | | | | | | The "method" parameter was part of the original port of the driver from the kernel. At some point this may have been added to allow for future differentiation (as omap1 and omap2 have different GPIO IP blocks, so this wasn't an unreasonable thing to do). At this point however it's just extra overhead, so drop. Signed-off-by: Tom Rini <trini@konsulko.com>
* mmc: omap_hsmmc: enable 8bit interface for eMMC for AM43xxNikita Kiryanov2015-08-121-2/+2
| | | | | | | | | Enable 8bit interface on HSMMC2 for am43xx to support 8bit eMMC chips. Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* mmc: omap_hsmmc: enable proper CMD(DAT) lines reset procedure for am43xxNikita Kiryanov2015-08-121-1/+1
| | | | | | | | | | | The CMD(DAT) lines reset procedure described in the OMAP4(AM335x, OMAP5, DRA7xx) TRMs is also necessary for AM43XX. Enable it in the driver. Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* spi: omap3_spi: add am43xx support to omap3_spiNikita Kiryanov2015-08-121-1/+1
| | | | | | | | | Add support for AM43XX to the omap3_spi driver. Cc: Jagan Teki <jteki@openedev.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Reviewed-by: Jagan Teki <jteki@openedev.com>
* mmc: hi6220_dw_mmc: Add hi6220 glue code for dw_mmc controller.Peter Griffin2015-08-122-0/+57
| | | | | | | | | This patch adds the glue code for hi6220 SoC which has 2x synopsis dw_mmc controllers. This will be used by the hikey board support in subsequent patches. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* pmic: pmic_hi6553: Add a driver for the hi6553 pmic found on hikey board.Peter Griffin2015-08-122-0/+134
| | | | | | | | | This adds a simple pmic driver for the hi6553 pmic which is used in conjunction with the hi6220 SoC on the hikey board. Eventually this driver will be updated to be a proper UCLASS PMIC driver which can parse the voltages direct from device tree. Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
* dm: gpio: hi6220: Add a hi6220 GPIO driver model driver.Peter Griffin2015-08-122-0/+97
| | | | | | | This patch adds support for the GPIO perif found on hi6220 SoC. Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
* usb: ohci: enable cache supportWu, Josh2015-08-122-12/+2
| | | | | | | | Remove the CONFIG_DM_USB limitation to enable cache support functions. Tested on SAMA5D3x-EK board. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
* Correct License and Copyright information on few filesRuchika Gupta2015-08-121-3/+1
| | | | | | | | | gpio.h - Added missing copyright in few files. rsa-mod-exp.h - Corrected copyright in the file. fsl_sec.h - Added missing license in files drivers/crypto/fsl/Makefile - Removed the incomplete GPLv2 license and replaced it with GPLv2+ license Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
* drivers: hierarchize drivers Kconfig menuMasahiro Yamada2015-08-1211-0/+68
| | | | | | | | | | | The menuconfig for drivers are getting more and more cluttered and unreadable because too many entries are displayed in a single flat menu. Use hierarchic menu for each category. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Update to apply again in a few places, drop USB hunk] Signed-off-by: Tom Rini <trini@konsulko.com>
* dwc2: Add dcache supportAlexander Stein2015-08-121-7/+17
| | | | | | | | | | | This adds dcache support for dwc2. The DMA buffers must be DMA aligned and is flushed for outgoing transactions before starting transfer. For ingoing transactions it is invalidated after the transfer has finished. Signed-off-by: Alexander Stein <alexanders83@web.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> [trini: Update to apply again on top of DM patches] Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: bcm283x: Allocate all mailbox buffers cacheline alignedAlexander Stein2015-08-121-2/+2
| | | | | | | | | | The mailbox buffer is required to be at least 16 bytes aligned, but for cache invalidation and/or flush it needs to be cacheline aligned. Use ALLOC_CACHE_ALIGN_BUFFER for all mailbox buffer allocations. Signed-off-by: Alexander Stein <alexanders83@web.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
* input: twl4030: Keypad scan and inputPaul Kocialkowski2015-08-121-0/+39
| | | | | | | | | | | This allows scanning the twl4030 keypad, storing the result in a 64-byte long matrix with the twl4030_keypad_scan function. Detecting a key at a given column and row is made easier with the twl4030_keypad_key function. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* input: TWL4030 input support for power button, USB and chargerPaul Kocialkowski2015-08-122-0/+50
| | | | | | | This adds support for detecting a few inputs exported by the TWL4030. Currently-supported inputs are the power button, USB and charger presence. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* power: twl4030: Power off supportPaul Kocialkowski2015-08-121-0/+60
| | | | | | | | | | This adds support for powering off (the omap3 SoC) from the twl4030. This is especially useful when the kernel does not actually power off the device using this method but reboots and leaves it up to the bootloader to actually turn the power off. Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* nand: lpc32xx: add SLC NAND controller supportVladimir Zapolskiy2015-08-122-0/+177
| | | | | | | | | | | | | | | | | | | | | The change adds support of LPC32xx SLC NAND controller. LPC32xx SoC has two different mutually exclusive NAND controllers to communicate with single and multiple layer chips. This simple driver allows to specify NAND chip timings and defines custom read_buf()/write_buf() operations, because access to 8-bit data register must be 32-bit aligned. Support of hardware ECC calculation is not implemented (data correction is always done by software), since it requires a working DMA engine. The driver can be included to an SPL image. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Scott Wood <scottwood@freescale.com> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
* spl: nand: simple: replace readb() with chip specific read_buf()Vladimir Zapolskiy2015-08-121-2/+5
| | | | | | | | | | | | | | | Some NAND controllers define custom functions to read data out, respect this in order to correctly support bad block handling in simple SPL NAND framework. NAND controller specific read_buf() is used even to read 1 byte in case of connected 8-bit NAND device, it turns out that read_byte() may become outdated. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Cc: Tom Rini <trini@konsulko.com> Cc: Tom Warren <twarren@nvidia.com> Acked-by: Scott Wood <scottwood@freescale.com>
* nand, atmel: remove udelay in spl_nand_erase_one()Heiko Schocher2015-08-121-2/+0
| | | | | | | | remove unneeded udelay() in this function, as we use the dev_ready pin. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Scott Wood <scottwood@freescale.com>
* dm: pmic: max77686: Correct two typos in a commentSimon Glass2015-08-121-2/+2
| | | | | | These were pointed out in review but I missed them. Signed-off-by: Simon Glass <sjg@chromium.org>
* power: regulator: max77686 correct variable typePeng Fan2015-08-121-8/+8
| | | | | | | | | The return type of pmic_read and pmic_write is signed int, so correct variable 'ret' from type unsigned int to int. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Simon Glass <sjg@chromium.org> Cc: Przemyslaw Marczak <p.marczak@samsung.com>
* power: regulator: add pfuze100 supportPeng Fan2015-08-123-0/+577
| | | | | | | | | | | | | 1. Add new regulator driver pfuze100. * Introduce struct pfuze100_regulator_desc for maintaining info for one regulator. 2. Add new Kconfig entry DM_REGULATOR_PFUZE100 for pfuze100. 3. This driver intends to support PF100, PF200 and PF3000. 4. Add related macro definition in pfuze header file. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org>
* power: pmic: pfuze100 support driver modelPeng Fan2015-08-121-0/+1
| | | | | | | | | | | | | 1. Support driver model for pfuze100. 2. Introduce a new Kconfig entry DM_PMIC_PFUZE100 for pfuze100 3. This driver intends to support PF100, PF200 and PF3000, so add the device id into the udevice_id array. 4. Rename PMIC_NUM_OF_REGS macro to PFUZE100_NUM_OF_REGS. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* power: regulator use node name when no regulator-namePeng Fan2015-08-121-1/+3
| | | | | | | | | If there is no property named 'regulator-name' for regulators, choose node name instead, but not directly return failure value. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-dmTom Rini2015-08-102-3/+28
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| * dm: serial: Add a REQUIRE_SERIAL_CONSOLE option for boards with no serial portHans de Goede2015-08-102-3/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the serial code assumes that there is always at least one serial port (and panics / crashes due to null pointer dereferences when there is none). This makes it impossible to use u-boot on boards where there is no (debug) serial port, because e.g. all uart pins are muxed to another function. This commit adds a CONFIG_REQUIRE_SERIAL_CONSOLE Kconfig option, which defaults to y (preserving existing behavior), which can be set to n on such boards to make them work. This commit only implements this for CONFIG_DM_SERIAL=y configs, as allowing running without a serial port for CONFIG_DM_SERIAL=n configs is non trivial, and is not necessary at this moment. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-08-087-86/+672
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| * sunxi: display: Add composite video out supportHans de Goede2015-08-081-22/+178
| | | | | | | | | | | | | | | | | | | | Add composite video out support. This only gets enabled on the Mele M3 for now, since that is were it was tested. It will be enabled on more boards after testing. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: display: Add support for interlaced modesHans de Goede2015-08-081-13/+22
| | | | | | | | | | | | | | | | Add support for interlaced modes, this is a preparation patch for adding composite out support. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: display: Add a few extra register and constant definesHans de Goede2015-08-081-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Add a few extra sunxi display registers and constant defines. Also rename some existing defines (e.g. dropping _GCTRL) and make some more generic (e.g. dropping the 2x scaling from SUNXI_LCDC_TCON1_TIMING_V_TOTAL). This is a preparation patch for adding composite video out support. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: display: Correct clk_delay calculations for lcd displaysHans de Goede2015-08-081-4/+7
| | | | | | | | | | | | | | We should only subtract 2 from the vblank time when using tcon1. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: display: Replace #ifdef-ery with helper functionsHans de Goede2015-08-081-34/+56
| | | | | | | | | | | | | | | | | | | | | | | | All the #ifdef-ery in selecting the default and fallback monitor type is becoming unyielding and makes the code hard to read, replace it with a few helper functions. This will also be useful with the upcoming CHIP board which has display adapter daughterboards which should be runtime detectable. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: usb-phy: Never power off the usb portsHans de Goede2015-08-083-14/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB devices are not really designed to get the power bounced off and on at them. Esp. USB powered harddisks do not like this. Currently we power off the USB ports both on a "usb reset" and when booting the kernel, causing the usb-power to bounce off and then back on again. This patch removes the powering off calls, fixing the undesirable power bouncing. Note this requires some special handling for the OTG port: 1) We must skip the external vbus check if we've already enabled our own vbus to avoid false positives 2) If on an usb reset we no longer detect that the id-pin is grounded, turn off vbus as that means an external vbus may be present now Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: nand: Add board configuration optionsPiotr Zierhoffer2015-08-081-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When SPL_NAND_SUNXI option is selected in config, set some configuration options for sunxi NAND. This commit also introduces the configurable options in Kconfig. Signed-off-by: Peter Gielda <pgielda@antmicro.com> Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com> Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com> Signed-off-by: Karol Gugala <kgugala@antmicro.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: nand: Add basic sunxi NAND driver for SPL with DMA supportPiotr Zierhoffer2015-08-082-0/+354
| | | | | | | | | | | | | | | | | | | | | | | | | | This driver adds NAND support to SPL. It was tested on Allwinner A20. Signed-off-by: Peter Gielda <pgielda@antmicro.com> Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com> Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com> Signed-off-by: Karol Gugala <kgugala@antmicro.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | ddr: altera: sequencer: Clean checkpatch issuesMarek Vasut2015-08-081-71/+88
| | | | | | | | | | | | | | | | | | Fix most of the dangling checkpatch issues, no functional change. There are still 7 warnings, 1 checks , but those are left in place for the sake of readability of the code. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | ddr: altera: sequencer: Clean data typesMarek Vasut2015-08-081-48/+48
| | | | | | | | | | | | | | Replace uintNN_t with uNN. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | ddr: altera: sequencer: Pluck out misc macros from codeMarek Vasut2015-08-081-22/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | Actually convert the sequencer code to use socfpga_sdram_misc_config instead of the various macros. This is just an sed exercise here, no manual coding needed. This patch actually removes the need to include any board-specific files in sequencer.c , so sequencer.c namespace is now no longer poluted by QTS-generated macros. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | ddr: altera: sequencer: Zap SEQ_T(INIT|RESET)_CNTR._VALMarek Vasut2015-08-082-49/+4
| | | | | | | | | | | | | | | | | | This is another macro used to obfuscate the real code. The T(INIT|RESET)_CNTR._VAL is always defined, so this indirection is unnecessary. Get rid of this. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | ddr: altera: sequencer: Zap VFIFO_SIZEMarek Vasut2015-08-082-7/+4
| | | | | | | | | | | | | | Just use READ_VALID_FIFO_SIZE directly, no need for this macro obfuscation. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | ddr: altera: sequencer: Wrap misc remaining macrosMarek Vasut2015-08-081-0/+2
| | | | | | | | | | | | | | | | | | | | | | Introduce structure socfpga_sdram_misc_config to wrap the remaining misc configuration values in board file. Again, introduce a function, socfpga_get_sdram_misc_config(), which returns this the structure. This is almost the final step toward wrapping the nasty QTS generated macros in board files and reducing the pollution of the namespace. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | ddr: altera: sequencer: Pluck out IO_* macros from codeMarek Vasut2015-08-081-101/+100
| | | | | | | | | | | | | | | | | | Actually convert the sequencer code to use socfpga_sdram_io_config instead of the IO_* macros. This is just an sed excercise here, no manual coding needed. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | ddr: altera: sequencer: Wrap IO_* macrosMarek Vasut2015-08-081-0/+2
| | | | | | | | | | | | | | | | | | | | | | Introduce structure socfpga_sdram_io_config to wrap the IO configuration values in board file. Introduce socfpga_get_sdram_io_config() function, which returns this the structure. This is another step toward wrapping the nasty QTS generated macros in board files and reducing the pollution of the namespace. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | ddr: altera: sequencer: Pluck out RW_MGR_* macros from codeMarek Vasut2015-08-082-154/+154
| | | | | | | | | | | | | | | | | | Actually convert the sequencer code to use socfpga_sdram_rw_mgr_config instead of the RW_MGR_* macros. This is just an sed exercise here, no manual coding needed. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | ddr: altera: sequencer: Wrap RW_MGR_* macrosMarek Vasut2015-08-081-0/+4
| | | | | | | | | | | | | | | | | | | | | | Introduce structure socfpga_sdram_rw_mgr_config to wrap the RW manager configuration values in board file. Introduce a complementary function, socfpga_get_sdram_rwmgr_config(), which returns this the structure. This is another step toward wrapping the nasty QTS generated macros in board files and reducing the pollution of the namespace. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | ddr: altera: sequencer: Wrap ac_rom_init and inst_rom_initMarek Vasut2015-08-081-6/+8
| | | | | | | | | | | | | | | | | | | | Introduce two wrapper functions, socfpga_get_seq_ac_init() and socfpga_get_seq_inst_init() to avoid direct inclusion of the sequencer_auto_ac_init.h and sequencer_auto_inst_init.h QTS generated files. This reduces namespace pollution again. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | ddr: altera: sequencer: Zap bogus redefinition of RW_MGR_MEM_NUMBER_OF_RANKSMarek Vasut2015-08-081-1/+0
| | | | | | | | | | | | | | | | This is defined in the QTS-generated headers, so it must not be re-defined in sequencer.h . Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | ddr: altera: sequencer: Zap unused params and macrosMarek Vasut2015-08-082-75/+5
| | | | | | | | | | | | | | | | These parameters are not used in the code, zap them and the macros which are used by them as well. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | ddr: altera: sequencer: Move qts-generated files to board dirMarek Vasut2015-08-085-605/+9
| | | | | | | | | | | | | | | | Move the files generated by QTS into the board directory, they should not be part of the driver files at all. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | ddr: altera: sdram: Make sdram_start and sdram_end into u32Marek Vasut2015-08-081-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Originally, both sdram_start and sdram_end were 64b values. The sdram_start had no reason for being so, since our address space is only 32b, so switching sdram_start to u32 is simple. The sdram_end is a bit more complex, since it can actually be set to (1 << 32) if someone really wanted to use an SoCFPGA with 4 GiB of DRAM and fixed the code around a little. But, the code handling the protection rules internally decrements the sdram_end variable anyway. Thus, instead of calling the code and passing in the address of the SDRAM end, pass in the address already decremented by one. This lets the sdram_end be 32b as well. Signed-off-by: Marek Vasut <marex@denx.de>