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* Merge git://git.denx.de/u-boot-x86Tom Rini2017-09-021-3/+2
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| * x86: ich-spi: Clear atomic preop only when SPI settings are not lockedBin Meng2017-09-021-1/+2
| | | | | | | | | | | | | | | | The atomic preop register can only be written when SPI settings are not locked, otherwise it's read-only. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * x86: ich-spi: Remove useless assignment in ich_spi_xfer()Bin Meng2017-09-021-2/+0
| | | | | | | | | | | | | | | | | | In ich_spi_xfer() when the driver presets control fields, control variable gets assigned twice. Apparently only the last assignment takes effect. Remove the other one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
* | Kconfig: Add EEPROM options to Kconfig when I2C_EEPROM is setAdam Ford2017-09-021-0/+45
|/ | | | | | | | | | | | | | | | | | Add the following options to drivers/misc/Kconfig: SYS_I2C_EEPROM_ADDR SYS_I2C_EEPROM_BUS SYS_EEPROM_SIZE SYS_EEPROM_PAGE_WRITE_BITS SYS_EEPROM_PAGE_WRITE_DELAY_MS SYS_I2C_EEPROM_ADDR_LEN SYS_I2C_EEPROM_ADDR_OVERFLOW This does not migrate any boards, but provides a foundations for those who want/need these options Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Migrate uniphier] Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_SYS_I2C_BUS_MAX to KconfigAdam Ford2017-09-011-0/+10
| | | | | | | | | | This converts the following to Kconfig: CONFIG_SYS_I2C_BUS_MAX Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> [trini: Fix AM43XX drop AM44XX] Signed-off-by: Tom Rini <trini@konsulko.com>
* Configs: Migrate I2C_BUS_MAX to CONFIG_SYS_I2C_BUS_MAXAdam Ford2017-09-012-10/+10
| | | | | | | | For consistency with other platforms and in preparation of Kconfig migration, let's change Several TI platforms that use I2C_BUS_MAX to CONFIG_SYS_I2C_BUS_MAX Signed-off-by: Adam Ford <aford173@gmail.com>
* Revert "Merge git://git.denx.de/u-boot-video"Tom Rini2017-09-011-12/+1
| | | | | | | | | This reverts commit 1d20170467b079642be96996dcd71db64c3c365c, reversing changes made to 6aee2ab68c362ace5a59f89a63abed82e0bf19e5. The mxc_ipuv3_fb.c changes introduce build failures on some targets. Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-videoTom Rini2017-09-011-1/+12
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| * video: ipuv3_fb: skip IPU shutdown if IPU was not enabled beforeAnatolij Gustschin2017-08-291-1/+12
| | | | | | | | | | | | | | | | | | | | Boards can skip display interface init using board_video_skip(). If display interface was not initialized (e.g. no ipuv3 framebuffer registered or IPU clock disabled), booting Linux stops due to the crash in IPU shutdown function, when accessing IPU registers. Check IPU clock and skip shutdown if clock is not enabled. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | Merge git://git.denx.de/u-boot-imxTom Rini2017-09-015-4/+754
|\ \ | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: configs/imx6qdl_icore_mmc_defconfig configs/imx6qdl_icore_rqs_defconfig
| * | pinctrl: imx7ulp: Add new info instance for iomuxc1Peng Fan2017-08-231-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To i.MX7ULP, we need to create two info instances for iomux0 and iomux1 respectively, otherwise iomuxc0/1 will share one info instance and use one base, because imx_pinctrl_probe will use info to store base address and etc. But iomuxc0/1 actually have different base address. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de>
| * | pinctrl: imx: Fix mask when SHARE_MUX_CONF_REG is setPeng Fan2017-08-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | when using SHARE_MUX_CONF_REG, wrong mask is used for writing config value, which causes mux value is cleared. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de>
| * | spl: add serial download protocol (SDP) supportStefan Agner2017-08-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add USB serial download protocol support to SPL. If the SoC started in recovery mode the SPL will immediately switch to SDP and wait for further downloads/commands from the host side. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Łukasz Majewski <lukma@denx.de>
| * | usb: gadget: sdp: extend images compatible for jumpsStefan Agner2017-08-231-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support U-Boot images in SPL so that u-boot.img files can be directly downloaded and executed. Furthermore support U-Boot scripts download and execution in full U-Boot so that custom recovery actions can be downloaded from the host in a third step. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Łukasz Majewski <lukma@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * | usb: gadget: add SDP driverStefan Agner2017-08-233-0/+729
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SDP (Serial Downloader Protocol) implementation for U-Boot. The protocol is used in NXP SoC's boot ROM and allows to download program images. Beside that, it can also be used to read/write registers and download complete Device Configuration Data (DCD) sets. This basic implementation supports downloading images with the imx header format reading and writing registers. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Łukasz Majewski <lukma@denx.de>
* | | Merge git://git.denx.de/u-boot-uniphierTom Rini2017-09-0112-2/+194
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | - add {ofnode,dev}_read_resource_byname - provide DT probe hook to Denali NAND driver - update clk/reset driver - update DT - misc cleanups
| * | | reset: uniphier: add PXs3 supportMasahiro Yamada2017-08-301-0/+23
| | | | | | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | reset: uniphier: fix compatible for SD reset node for LD11/LD20Masahiro Yamada2017-08-301-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | LD20 has SD ctrl instead of MIO ctrl. LD11 has both of them. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | clk: uniphier: add System clock supportMasahiro Yamada2017-08-304-0/+67
| | | | | | | | | | | | | | | | | | | | | | | | Support system clocks for LD4, Pro4, sLD8, Pro5, PXs2/LD6b, LD11, LD20. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | mtd: nand: denali_dt: add a DT driverMasahiro Yamada2017-08-305-1/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A patch for NAND uclass support was proposed about half a year ago: https://patchwork.ozlabs.org/patch/722282/ It was not merged and I do not see on-going work for this. Without DM-based probing, we need to set up pinctrl etc. in an ad-hoc way and give lots of crappy CONFIG options for base addresses and properties, which are supposed to be specified by DT. This is painful. This commit just provides a probe hook to retrieve "reg" from DT and allocate private data in a DM manner. This DT driver is not essentially a NAND driver, in fact it is (ab)using UCLASS_MISC. Once UCLASS_NAND is supported, it would be possible to migrate to it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | ofnode: add {ofnode, dev}_read_resource_byname()Masahiro Yamada2017-08-292-0/+18
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux supports platform_get_resource_byname() to look up a resource by name. We want a similar helper. It is useful when a device node has named register regions. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2017-09-012-4/+29
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| * | | mmc: sunxi: Only update timing mode bit when enabling new timing modeChen-Yu Tsai2017-09-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When enabling the new mmc timing mode, we inadvertently clear all the remaining bits in the new timing mode register. The bits cleared include a default phase delay on the output clock. The BSP kernel states that the default values are supposed to be used. Clearing them results in decreased performance or transfer errors on some boards. Fixes: de9b1771c3b6 ("mmc: sunxi: Support new mode") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | | mmc: sunxi: fix legacy MMC initialisationMaxime Ripard2017-08-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver-model rework changed, among other things, the way the private data were moved around. It now uses the private field in the struct mmc. However, the mmc_create argument was changed in the process to always pass the array we used to have to store our private structures. The basically means that all the MMC driver instances will now have the private data of the first instance, which obviously doesn't work very well. Pass the proper pointer to mmc_create. Fixes: 034e226bc77e ("dm: mmc: sunxi: Pass private data around explicitly") Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | | mmc: sunxi: Support new modeMaxime Ripard2017-08-282-3/+28
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Almost all of the newer Allwinner SoCs have a new operating mode for the eMMC clocks that needs to be enabled in both the clock and the MMC controller. Details about that mode are sparse, and the name itself (new mode vs old mode) doesn't give much details, but it seems that the it changes the sampling of the MMC clock. One side effect is also that it divides the parent clock rate by 2. Add support for it through a Kconfig option. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2017-08-281-2/+2
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| * | | usb: dwc3: fix Kconfig dependency to accept host driver in drivers/usb/dwc3Masahiro Yamada2017-08-281-2/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We see the choice of USB_DWC3_HOST / _GADGET in drivers/usb/dwc3/Kconfig, but we can not choose USB_DWC3_HOST unless USB_GADGET is defined. This is strange. Loosen the "depends on" and also move "select USB_GADGET_DUALSPEED" to the correct place. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | nvme: Get rid of the global variable nvme_infoBin Meng2017-08-283-35/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the NVMe uclass driver uses a global variable nvme_info to store global information like namespace id, and NVMe controller driver's priv struct has a blk_dev_start that is used to calculate the namespace id based on the global information from nvme_info. This is not a good design in the DM world and can be replaced with the following changes: - Encode the namespace id in the NVMe block device name during the NVMe uclass post probe - Extract the namespace id from the device name during the NVMe block device probe - Let BLK uclass calculate the devnum for us by passing -1 to blk_create_devicef() as the devnum Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | | nvme: Use blk_create_devicef() APIBin Meng2017-08-281-9/+3
| | | | | | | | | | | | | | | | | | | | | The codes in nvme_uclass_post_probe() can be replaced to call the blk_create_devicef() API directly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | | nvme: Apply cache operations on the DMA buffersBin Meng2017-08-282-5/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far cache operations are only applied on the submission queue and completion queue, but they are missing in other places like identify and block read/write routines. In order to correctly operate on the caches, the DMA buffer passed to identify routine must be allocated properly on the stack with the existing macro ALLOC_CACHE_ALIGN_BUFFER(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | | nvme: Consolidate block read and write routinesBin Meng2017-08-281-53/+12
| | | | | | | | | | | | | | | | | | | | | The NVMe block read and write routines are almost the same except the command opcode. Let's consolidate them to avoid duplication. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | | nvme: Use macros to access NVMe queuesBin Meng2017-08-281-7/+15
| | | | | | | | | | | | | | | | | | | | | | | | NVMe driver only uses two queues. The first one is allocated to do admin stuff, while the second one is for IO stuff. So far the driver uses magic number (0/1) to access them. Change to use macros. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | | nvme: Respect timeout when en/disabling the controllerBin Meng2017-08-281-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | So far the driver unconditionally delays 10ms when en/disabling the controller and still return 0 if 10ms times out. In fact, spec defines a timeout value in the CAP register that is the worst case time that host software shall wait for the controller to become ready. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | | nvme: Cache controller's capabilitiesBin Meng2017-08-282-6/+6
| | | | | | | | | | | | | | | | | | | | | Capabilities register is RO and accessed at various places in the driver. Let's cache it in the controller driver's priv struct. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | | nvme: Fix endianness assignment to prp2 in nvme_identify()Bin Meng2017-08-281-1/+1
| | | | | | | | | | | | | | | | | | | | | So far this is not causing any issue due to NVMe and x86 are using the same endianness, but for correctness, it should be fixed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | | nvme: Fix ndev->queues allocationBin Meng2017-08-281-2/+2
| | | | | | | | | | | | | | | | | | | | | ndev->queues is a pointer to pointer, but the allocation wrongly requests sizeof(struct nvme_queue). Fix it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | | nvme: Fix getting PCI vendor id of the NVMe block deviceBin Meng2017-08-282-22/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The codes currently try to read PCI vendor id of the NVMe block device by dm_pci_read_config16() with its parameter set as its root complex controller (ndev->pdev) instead of itself. This is seriously wrong. We can read the vendor id by passing the correct udevice parameter to the dm_pci_read_config16() API, however there is a shortcut by reading the cached vendor id from the PCI device's struct pci_child_platdata. While we are here fixing this bug, apparently the quirk stuff handle codes in nvme_get_info_from_identify() never takes effect since its logic has never been true at all. Remove these codes completely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | | nvme: Remove useless definesBin Meng2017-08-281-60/+0
|/ / | | | | | | | | | | | | These are leftover when the driver was ported from Linux and are not used by the U-Boot driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2017-08-261-33/+96
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| * | clk: rmobile: Split R8A7795 and R8A7796 core clock tablesMarek Vasut2017-08-261-33/+96
| |/ | | | | | | | | | | | | | | | | | | The R8A7795 and R8A7796 tables use different constants to identify clock in DT, so split the tables and use the correct constants on R8A7795. This fixes UART clock misconfiguration on R8A7795. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | Merge git://git.denx.de/u-boot-x86Tom Rini2017-08-266-233/+102
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| * | serial: serial-uclass: Add generic serial RX buffer supportStefan Roese2017-08-242-2/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pasting longer lines into the U-Boot console prompt sometimes leads to characters missing. One problem here is the small 16-byte FIFO of the legacy NS16550 UART, e.g. on x86 platforms. This patch now introduces a Kconfig option to enable RX buffer support for all DM based serial drivers. With this option enabled, I was able paste really long lines into the U-Boot console, without any characters missing. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * | Revert "serial: ns16550: Add RX interrupt buffer support"Stefan Roese2017-08-242-128/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 6822cf3ec7c8768b8727573b8f4b2cb3d870b881. As Bin Meng has tested and pointed out, we don't need the RX interrupt for the RX buffer support at all. Just reading all available characters into a buffer is sufficient to solve the problem with the dropped characters upon long lines pasted into the U-Boot prompt. Since this RX buffer support can be implemented in a generic way, without any device specifica (e.g. for the ns16550), I'll post a new patch with a new serial RX buffer support for DM, which all DM based serial drivers can use. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | vbe: Drop vbe_get_video_info()Bin Meng2017-08-241-41/+0
| | | | | | | | | | | | | | | | | | With DM video, this is not used any more. Drop it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: ich-spi: Move opcode registers configuration to another routineBin Meng2017-08-241-6/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the ICH SPI opcode registers configuration is done in the ich_spi_remove() routine, a little bit weird but that's how current. Linux MTD driver works. This changes to move the opcode registers configuration to a separate routine ich_spi_config_opcode() which might be called by U-Boot itself as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | x86: ich-spi: Don't read cached lock statusBin Meng2017-08-242-8/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the ICH SPI controller driver reads the controller lock status from its register in the probe routine and saves the lock status to a member of priv. Later the driver uses the cached status from priv to judge whether the controller setting is locked and do different setup. But such logic is only valid when there is only the SPI controller driver that touches the SPI hardware. In fact the lock status change can be trigged outside the driver, eg: during the fsp_notify() call when Intel FSP is used. This changes the driver to read the lock status every time when an SPI transfer is initiated instead of reading the cached one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | x86: ich-spi: Remove unnecessary assignment in ich_init_controller()Bin Meng2017-08-241-1/+0
| | | | | | | | | | | | | | | | | | | | | There is no need to do another assignment to ich7_spi. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | x86: ich-spi: Remove spi_write_protect_region()Bin Meng2017-08-241-50/+0
| |/ | | | | | | | | | | | | This routine is not called anywhere. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
* | Merge git://git.denx.de/u-boot-i2cTom Rini2017-08-266-0/+1051
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| * | i2c: muxes: add i2c gpio multiplexer driverPeng Fan2017-08-233-0/+148
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add an i2c mux driver providing access to i2c bus segments using a hardware MUX sitting on a master bus and controlled through gpio pins. E.G. something like: ---------- ---------- Bus segment 1 - - - - - | | SCL/SDA | |-------------- | | | |------------| | | | | | Bus segment 2 | | | Linux | GPIO 1..N | MUX |--------------- Devices | |------------| | | | | | | | Bus segment M | | | |---------------| | ---------- ---------- - - - - - SCL/SDA of the master I2C bus is multiplexed to bus segment 1..M according to the settings of the GPIO pins 1..N. Note commit log from kernel commit 92ed1a76("i2c: Add generic I2C multiplexer using GPIO API") Signed-off-by: Peng Fan <peng.fan@nxp.com> Tested-by: Peng Fan <peng.fan@nxp.com> (i.MX6QP-Sabreauto) Cc: Heiko Schocher <hs@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Simon Glass <sjg@chromium.org>
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