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* virtio: Add virtio over pci transport driverBin Meng2018-11-144-0/+603
| | | | | | | | | | | This adds a transport driver that implements UCLASS_VIRTIO for virtio over pci, which is commonly used on x86. It only supports the legacy interface of the pci transport, which is the default device that QEMU emulates. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* virtio: Add block driver supportTuomas Tynkkynen2018-11-144-0/+274
| | | | | | | | This adds virtio block device driver support. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* blk: Introduce IF_TYPE_VIRTIOTuomas Tynkkynen2018-11-141-0/+2
| | | | | | | | This adds a new block interface type for VirtIO block devices. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* blk: Make blk_next_free_devnum() publicBin Meng2018-11-141-1/+1
| | | | | | | | blk_next_free_devnum() can be helpful in some cases. Make it a public API. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* blk: Drop blk_prepare_device()Bin Meng2018-11-141-9/+0
| | | | | | | With the post_probe() changes, this API is no longer needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* blk: Call part_init() in the post_probe() methodBin Meng2018-11-146-8/+13
| | | | | | | | | | | part_init() is currently called in every DM BLK driver, either in its bind() or probe() method. However we can use the BLK uclass driver's post_probe() method to do it automatically. Update all DM BLK drivers to adopt this change. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sandbox: blk: Switch to use platdata_auto_alloc_size for the driver dataBin Meng2018-11-141-7/+8
| | | | | | | | | | | | | Currently the sandbox block driver uses priv_auto_alloc_size for the driver data, however that's only available after the device probe phase. In order to make it accessible in an earlier phase, switch to use platdata_auto_alloc_size instead. This patch is the prerequisite for the follow up patch of DM BLK driver changes to work with Sandbox. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* virtio: Add net driver supportTuomas Tynkkynen2018-11-144-0/+494
| | | | | | | | This adds virtio net device driver support. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* virtio: Add virtio over mmio transport driverBin Meng2018-11-144-0/+550
| | | | | | | | | | | | | | | VirtIO can use various different buses and virtio devices are commonly implemented as PCI devices. But virtual environments without PCI support (a common situation in embedded devices models) might use simple memory mapped device (“virtio-mmio”) instead of the PCI device. This adds a transport driver that implements UCLASS_VIRTIO for virtio over mmio. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* virtio: Add codes for virtual queue/ring managementTuomas Tynkkynen2018-11-142-1/+359
| | | | | | | | | This adds support for managing virtual queue/ring, the channel for high performance I/O between host and guest. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: Add a new uclass driver for VirtIO transport devicesBin Meng2018-11-145-0/+403
| | | | | | | | | | | | | | | | This adds a new virtio uclass driver for “virtio” [1] family of devices that are are found in virtual environments like QEMU, yet by design they look like physical devices to the guest. The uclass driver provides child_pre_probe() and child_post_probe() methods to do some common operations for virtio device drivers like device and driver supported feature negotiation, etc. [1] http://docs.oasis-open.org/virtio/virtio/v1.0/virtio-v1.0.pdf Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: core: Allow uclass to set up a device's child after it is probedBin Meng2018-11-141-1/+12
| | | | | | | | | | | Some buses need to set up their child devices after they are probed. Support a common child_post_probe() method for the uclass. With this change, the two APIs uclass_pre_probe_device() and uclass_post_probe_device() become symmetric. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* regmap: Add endianness supportMario Six2018-11-141-10/+124
| | | | | | | | | | | | Add support for switching the endianness of regmap accesses via the "little-endian", "big-endian", and "native-endian" boolean properties in the device tree. The default endianness is native endianness. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* regmap: Support reading from specific rangeMario Six2018-11-141-5/+44
| | | | | | | | | | | | | | It is useful to be able to treat the different ranges of a regmap separately to be able to use distinct offset for them, but this is currently not implemented in the regmap API. To preserve backwards compatibility, add regmap_read_range and regmap_write_range functions that take an additional parameter 'range_num' that identifies the range to operate on. Reviewed-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
* regmap: Add raw read/write functionsMario Six2018-11-141-7/+57
| | | | | | | | | | | | | | | | | The regmap functions currently assume that all register map accesses have a data width of 32 bits, but there are maps that have different widths. To rectify this, implement the regmap_raw_read and regmap_raw_write functions from the Linux kernel API that specify the width of a desired read or write operation on a regmap. Implement the regmap_read and regmap_write functions using these raw functions in a backwards-compatible manner. Reviewed-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org>
* regmap: Add error outputMario Six2018-11-141-2/+8
| | | | | | | | | Add some debug output in cases where the initialization of a regmap fails. Reviewed-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
* regmap: Introduce init_rangeMario Six2018-11-141-12/+56
| | | | | | | | | | | | Both fdtdec_get_addr_size_fixed and of_address_to_resource can fail with an error, which is not currently checked during regmap initialization. Since the indentation depth is already quite deep, extract a new 'init_range' method to do the initialization. Reviewed-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
* core: ofnode: Fix mem leak in error pathMario Six2018-11-141-1/+3
| | | | | | | | | | A newly created property is currently not freed if a name could not be allocated. This patch fixes the resulting memory leak in the error patch. Reported-by: Coverity (CID: 184085) Fixes: e369e58df79c ("core: Add functions to set properties in live-tree") Signed-off-by: Mario Six <mario.six@gdsys.cc>
* misc: Add IHS FPGA driverMario Six2018-11-144-0/+926
| | | | | | | | Add a driver for gdsys IHS (Integrated Hardware Systems) FPGAs, which supports initialization of the FPGA, as well as information gathering. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
* misc: Add gdsys_soc driverMario Six2018-11-144-0/+106
| | | | | | | This patch adds a driver for the bus associated with a IHS FPGA. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
* misc: Sort Makefile entriesMario Six2018-11-141-30/+31
| | | | | | | | | Makefile entries should be sorted. Reviewed-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc> Signed-off-by: Anatolij Gustschin <agust@denx.de>
* regmap: Improve error handlingMario Six2018-11-141-0/+17
| | | | | | | | | | | | ofnode_read_simple_addr_cells may fail and return a negative error code. Check for this when initializing regmaps. Also check if both_len is zero, since this is perfectly possible, and would lead to a division-by-zero further down the line. Reviewed-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
* regmap: Add documentationMario Six2018-11-141-0/+6
| | | | | | | | Document the regmap_alloc() function. Reviewed-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
* timer: Sort Kconfig driver entriesBin Meng2018-11-141-55/+55
| | | | | | | This is currently out of order. Sort it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: core: Mirror the chosen node parse logic in the livetree scanningBin Meng2018-11-141-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | Commit f2006808f099: ("dm: core: parse chosen node") added a logic to parse the chosen node during dm_scan_fdt_node(), but unfortunately it missed adding the same logic in dm_scan_fdt_live(). This mirrors the logic in the livetree version. The weird thing is that commit f2006808f099 did update the test case to test such logic, but even if I reset to that commit, the test case still fails, and I have no idea how it could pass. With this fix, the following 2 test cases now pass: Test: dm_test_bus_children: bus.c test/dm/bus.c:112, dm_test_bus_children(): num_devices == list_count_items(&uc->dev_head): Expected 7, got 6 Test: dm_test_fdt: test-fdt.c test/dm/test-fdt.c:184, dm_test_fdt(): num_devices == list_count_items(&uc->dev_head): Expected 7, got 6 Fixes: f2006808f099 ("dm: core: parse chosen node") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in lists_bind_fdt()Bin Meng2018-11-146-14/+17
| | | | | | | | | | | | | | | | | | | | Currently the comments of several APIs (eg: dm_init_and_scan()) say: @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC flag. If false bind all drivers. The 'Pre-Relocation Support' chapter in doc/driver-model/README.txt documents the same that both device tree properties and driver flag are supported. However the implementation only checks these special device tree properties without checking the driver flag at all. This updates lists_bind_fdt() to consider both scenarios. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Squashed in http://patchwork.ozlabs.org/patch/996473/ : Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: util: Add a livetree equivalent API of dm_fdt_pre_reloc()Bin Meng2018-11-141-0/+25
| | | | | | | | This adds a new API dm_ofnode_pre_reloc(), a livetree equivalent API of dm_fdt_pre_reloc(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* cpu: mpc83xx: Remove unnecessary characters in the description stringBin Meng2018-11-141-1/+1
| | | | | | | | The description string should not contain unnecessary characters, like the ending '\n' or the leading 'CPU:'. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'next'Tom Rini2018-11-1416-969/+2444
|\ | | | | | | This brings in the u-boot-net PR from Joe.
| * driver: net: ti: keystone_net: switch to use common mdio libGrygorii Strashko2018-11-052-102/+18
| | | | | | | | | | | | | | | | Update TI Keystone 2 driver to re-use common mdio lib. Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
| * driver: net: ti: cpsw: switch to use common mdio libGrygorii Strashko2018-11-051-128/+6
| | | | | | | | | | | | | | | | Update TI CPSW driver to re-use common mdio lib Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
| * driver: net: ti: introduce common mdio support libraryGrygorii Strashko2018-11-053-1/+222
| | | | | | | | | | | | | | | | | | | | All existing TI SoCs network HW have similar MDIO implementation, so introduce common mdio support library which can be reused by TI networking drivers. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * driver: net: ti: cpsw: update to use SPDX identifierGrygorii Strashko2018-11-051-10/+2
| | | | | | | | | | | | | | | | Update to use SPDX license identifier. Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
| * drivers: net: keystone_net: drop non dm codeGrygorii Strashko2018-11-051-286/+1
| | | | | | | | | | | | | | | | | | | | Networking support for all TI K2 boards converted to use DM model and CONFIG_DM_ETH enabled in all corresponding defconfig files, hence drop unused non DM K2 networking code. Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
| * configs: net: convert DRIVER_TI_KEYSTONE_NET kconfigGrygorii Strashko2018-11-051-0/+5
| | | | | | | | | | | | | | | | Convert DRIVER_TI_KEYSTONE_NET to Kconfig. Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
| * driver: net: consolidate ti's code in separate folderGrygorii Strashko2018-11-059-14/+24
| | | | | | | | | | | | | | | | | | Add drivers/net/ti/ folder and move all TI's code in this folder for better maintenance. Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
| * net: phy: mscc: add support for VSC8574 PHYQuentin Schulz2018-11-051-0/+420
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The VSC8574 PHY is a 4-port PHY that is 10/100/1000BASE-T, 100BASE-FX, 1000BASE-X and triple-speed copper SFP capable, can communicate with the MAC via SGMII, QSGMII or 1000BASE-X, supports WOL, downshifting and can set the blinking pattern of each of its 4 LEDs, supports SyncE as well as HP Auto-MDIX detection. This adds support for 10/100/1000BASE-T and SGMII/QSGMII link with the MAC. The VSC8574 has also an internal Intel 8051 microcontroller whose firmware needs to be patched when the PHY is reset. If the 8051's firmware has the expected CRC, its patching can be skipped. The microcontroller can be accessed from any port of the PHY, though the CRC function can only be done through the PHY that is the base PHY of the package (internal address 0) due to a limitation of the firmware. The GPIO register bank is a set of registers that are common to all PHYs in the package. So any modification in any register of this bank affects all PHYs of the package. Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: phy: mscc: factorize part of config function for VSC8584Quentin Schulz2018-11-051-17/+39
| | | | | | | | | | | | | | | | | | | | Part of the config is common between the VSC8584 and the VSC8574, so to prepare for the upcoming support of VSC8574, use the phy_device.priv pointer that will keep the function that holds code that is PHY-specific and that should be called during config function. Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: phy: mscc: add support for VSC8584 PHYQuentin Schulz2018-11-051-0/+553
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The VSC8584 PHY is a 4-port PHY that is 10/100/1000BASE-T, 100BASE-FX, 1000BASE-X and triple-speed copper SFP capable, can communicate with the MAC via SGMII, QSGMII or 1000BASE-X, supports downshifting and can set the blinking pattern of each of its 4 LEDs, supports hardware offloading of MACsec and supports SyncE as well as HP Auto-MDIX detection. This adds support for 10/100/1000BASE-T and SGMII/QSGMII link with the MAC. The VSC8584 has also an internal Intel 8051 microcontroller whose firmware needs to be patched when the PHY is reset. If the 8051's firmware has the expected CRC, its patching can be skipped. The microcontroller can be accessed from any port of the PHY, though the CRC function can only be done through the PHY that is the base PHY of the package (internal address 0) due to a limitation of the firmware. The GPIO register bank is a set of registers that are common to all PHYs in the package. So any modification in any register of this bank affects all PHYs of the package. The revA of the VSC8584 PHY (which is not and will not be publicly released) should NOT patch the firmware of the microcontroller or it'll make things worse, the easiest way is just to not support it. Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * aspeed: ast2500: fix D2-PLL clock setting in RGMII modeCédric Le Goater2018-11-051-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The algorithm in the ast2500_calc_clock_config() routine suffers from integer rounding and the requested rate does not get the appropriate set of Numerator, Denumerator, Post Divider parameters. This is the case for the D2-PLL clock used by the MAC controllers in RGMII mode. The requested rated is 250MHz but a 251MHz is assigned. The easiest way to fix this problem is to introduce an array of clock settings defining the N, M, P parameters for well known frequencies used by the Aspeed SoC. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: ftgmac100: Add support for the Aspeed SoCCédric Le Goater2018-11-051-4/+27
| | | | | | | | | | | | | | | | | | | | The Faraday ftgmac100 MAC controllers as found on the Aspeed SoCs have some slight differences in the HW interface (End-Of-Rx/Tx-Ring bits). Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * aspeed: ast2500: fix missing break in D2PLL clock enablementCédric Le Goater2018-11-051-0/+1
| | | | | | | | | | | | | | Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: ftgmac100: add clock supportCédric Le Goater2018-11-051-1/+14
| | | | | | | | | | | | Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: ftgmac100: handle timeouts when transmittingCédric Le Goater2018-11-051-0/+24
| | | | | | | | | | Signed-off-by: Cédric Le Goater <clg@kaod.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: ftgmac100: convert the RX/TX descriptor arraysCédric Le Goater2018-11-051-77/+64
| | | | | | | | | | | | | | | | | | | | Use simple arrays under the device priv structure to hold the RX and TX descriptors and handle memory coherency by invalidating or flushing the d-cache when required. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: ftgmac100: add MDIO bus and phylib supportCédric Le Goater2018-11-051-220/+160
| | | | | | | | | | | | | | | | | | | | Implement the MDIO bus read/write functions using the readl_poll_timeout() routine, initialize the bus and scan for the PHY. RGMII and RMII mode are supported. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: ftgmac100: use setbits_le32() in the reset methodCédric Le Goater2018-11-051-1/+1
| | | | | | | | | | | | Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: ftgmac100: convert to driver modelCédric Le Goater2018-11-052-92/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver is based on the previous one and the code is only adapted to fit the driver model. The support for the Faraday ftgmac100 controller is the same with MAC and MDIO bus support for RGMII/RMII modes. Configuration is updated to enable compile again. At this stage, the driver compiles but is not yet functional. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: ftgmac100: use the aligned() macroCédric Le Goater2018-11-051-2/+2
| | | | | | | | | | | | Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: ftgmac100: use the BIT() macroCédric Le Goater2018-11-051-77/+77
| | | | | | | | | | | | Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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