summaryrefslogtreecommitdiff
path: root/drivers
Commit message (Collapse)AuthorAgeFilesLines
* CONFIG_SPL_SYS_[DI]CACHE_OFF: addTrevor Woerner2019-05-186-6/+7
| | | | | | | | | | | | | While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2019-05-156-25/+38
|\ | | | | | | | | - micrel, ti PHY fixes - rtl8169, mtk-eth fixes
| * eth: mtk-eth: fix incorrect read of phy-handleWeijie Gao2019-05-141-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In mt7629-rfb.dts, the phy-handle is a reference to the node phy0, not the node itself: phy-handle = <&phy0>; phy0: ethernet-phy@0 { reg = <0>; } However the driver used ofnode_find_subnode("phy-handle") to read the node. It will always fail. This patch replaces ofnode_find_subnode with dev_read_phandle_with_args to make sure the node can be read correctly. Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: rtl8169: Support RTL-8168h/8111hThierry Reding2019-05-141-0/+1
| | | | | | | | | | | | | | | | | | This version of the RTL-8168 is present on some development boards and is compatible with this driver. Add support for identifying this version of the chip so that U-Boot won't complain about it being unknown. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: rtl8169: Implement ->hwaddr_write() callbackThierry Reding2019-05-141-0/+18
| | | | | | | | | | | | | | | | | | Implement this callback that allows the MAC address to be set for the Ethernet card. This is necessary in order for the device to be able to receive packets for the MAC address that U-Boot advertises. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * phy: ti: Init node before readingMichal Simek2019-05-141-4/+4
| | | | | | | | | | | | | | | | There is a need to fill node before clk_output_sel is setup. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Reviewed-by: <hannes.schmelzer@br-automation.com>
| * net: phy: micrel: Allow KSZ8xxx and KSZ90x1 to be used togetherJames Byrne2019-05-143-18/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit d397f7c45b0b ("net: phy: micrel: Separate KSZ9000 drivers from KSZ8000 drivers") separated the KSZ8xxx and KSZ90x1 drivers and warns that you shouldn't select both of them due to a device ID clash between the KSZ9021 and the KS8721, asserting that "it is highly unlikely for a system to contain both a KSZ8000 and a KSZ9000 PHY". Unfortunately boards like the SAMA5D3xEK do contain both types of PHY, but fortunately the Linux Micrel PHY driver provides a solution by using different PHY ID and mask values to distinguish these chips. This commit contains the following changes: - The PHY ID and mask values for the KSZ9021 and the KS8721 now match those used by the Linux driver. - The warnings about not enabling both drivers have been removed. - The description for PHY_MICREL_KSZ8XXX has been corrected (these are 10/100 PHYs, not GbE PHYs). - PHY_MICREL_KSZ9021 and PHY_MICREL_KSZ9031 no longer select PHY_GIGE since this is selected by PHY_MICREL_KSZ90X1. - All of the relevant defconfig files have been updated now that PHY_MICREL_KSZ8XXX does not default to 'Y'. Signed-off-by: James Byrne <james.byrne@origamienergy.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | Merge tag 'u-boot-stm32-mcu-20190514' of https://github.com/pchotard/u-bootTom Rini2019-05-151-1/+1
|\ \ | |/ |/| | | | | | | | | | | STM32 MCUs update: _ Add MPU region for SPI NOR memory mapped region _ Add missing QSPI flash compatible for STM32 F7 boards _ Update spi-tx-bus-width and spi-rx-bus-width properties _ Add QSPI support for STM32F469 Discovery board
| * spi: Kconfig: Add STM32F4 support for STM32_QSPI driverPatrice Chotard2019-05-061-1/+1
| | | | | | | | | | | | Allow to select STM32_QSPI driver on STM32F4 SoCs. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2019-05-137-70/+527
|\ \ | | | | | | | | | - A10 FPGA programming support, Gen5 livetree conversion
| * | gpio: dwapb_gpio: convert to livetreeSimon Goldschmidt2019-05-101-14/+11
| | | | | | | | | | | | | | | | | | | | | Convert 'gpio_dwapb_bind' to iterate over subnodes using livetree functions (inspired from mt7621_gpio.c). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * | reset: socfpga: convert to livetreeSimon Goldschmidt2019-05-101-3/+1
| | | | | | | | | | | | | | | | | | | | | Convert 'socfpga_reset_probe' to use 'dev_read_u32_default' instead of 'fdtdec_get_int'. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * | serial: altera_uart: convert to livetreeSimon Goldschmidt2019-05-101-4/+1
| | | | | | | | | | | | | | | | | | | | | Convert 'altera_uart_ofdata_to_platdata' to use 'dev_read_u32_default' instead of 'fdtdec_get_int' and get rid of DECLARE_GLOBAL_DATA_PTR. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * | spi: designware: convert to livetreeSimon Goldschmidt2019-05-101-6/+2
| | | | | | | | | | | | | | | | | | | | | Convert 'dw_spi_ofdata_to_platdata' to use 'dev_read_u32_default' instead of 'fdtdec_get_int' and get rid of DECLARE_GLOBAL_DATA_PTR. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * | spi: cadence_qspi: convert to livetreeSimon Goldschmidt2019-05-101-20/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert 'cadence_spi_ofdata_to_platdata' to use dev_read_* functions to read driver parameters and 'dev_read_first_subnode'/'ofnode_read_*' to read flash (child node) parameters. Tested on socfpga_socrates (socfpga gen5). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * | timer: dw-apb: remove unused DECLARE_GLOBAL_DATA_PTRSimon Goldschmidt2019-05-101-2/+0
| | | | | | | | | | | | | | | | | | The dw-apb timer does not use 'gd', so remove its declaration. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * | spl: socfpga: Implement fpga bitstream loading with socfpga loadfsTien Fong Chee2019-05-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add support for loading FPGA bitstream to get DDR up running before U-Boot is loaded into DDR. Boot device initialization, generic firmware loader and SPL FAT support are required for this whole mechanism to work. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
| * | ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loadingTien Fong Chee2019-05-101-13/+484
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add FPGA driver to support program FPGA with FPGA bitstream loading from filesystem. The driver are designed based on generic firmware loader framework. The driver can handle FPGA program operation from loading FPGA bitstream in flash to memory and then to program FPGA. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
| * | ARM: socfpga: Moving the watchdog reset to the for-loop status pollingTien Fong Chee2019-05-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Current watchdog reset is misplaced after for-loop status polling, so this poses a risk that watchdog can't be reset timely if polling taking longer than watchdog timeout. This patch moving the watchdog reset into polling to ensure the watchdog can be reset timely. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
| * | ARM: socfpga: Cleaning up and ensuring consistent format messages in driverTien Fong Chee2019-05-101-6/+7
| | | | | | | | | | | | | | | | | | | | | Ensure all the debug messages are always prefix with "FPGA: " and comment beginning with uppercase letter. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
* | | sh: sh3: Remove CPU supportMarek Vasut2019-05-101-67/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CPU core is old, no boards using the CPU are left in mainline, it has no prospects of ever being converted to DM, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
* | | sh: sh2: Remove CPU supportMarek Vasut2019-05-101-8/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CPU core is old, no boards using the CPU are left in mainline, it has no prospects of ever being converted to DM, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
* | | serial: sh: Drop assorted SH3, SH4, SH5 macrosMarek Vasut2019-05-102-115/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Drop unused macros from the header to clean it up. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
* | | serial: sh: Drop RTS7751R2D supportMarek Vasut2019-05-101-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no RTS7751R2D support in U-Boot, drop all the RTS7751R2D macros. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
* | | serial: sh: Drop SH2007 supportMarek Vasut2019-05-101-8/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no SH2007 support in U-Boot, drop all the SH2007 macros. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
* | | serial: sh: Drop H8 supportMarek Vasut2019-05-101-84/+0
|/ / | | | | | | | | | | | | | | | | | | There is no H8 support in U-Boot, drop all the H8 macros. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
* | mtd: ubi: Remove select for non existent optionChris Packham2019-05-101-1/+0
| | | | | | | | | | | | | | | | | | There is no 'config CRC32' remove the select that was attempting to use it. Reported-by: Robert P. J. Day <rpjday@crashcourse.ca> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* | sysreset: select DM_GPIO instead of GPIOChris Packham2019-05-101-1/+1
| | | | | | | | | | | | | | | | | | CONFIG_GPIO does not exist. sysreset_gpio.c uses the DM gpio APIs so the correct option to select is DM_GPIO. Reported-by: Robert P. J. Day <rpjday@crashcourse.ca> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | remoteproc: k3_system_controller: Increase rx timeoutLokesh Vutla2019-05-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is one case where 400ms is not sufficient for loading the system firmware: - System firmware is not signed with rsa degenerate key. - ROM loading the sysfw directly from SPI flash which is in memory mapped mode. The above scenario is definitely not desired in production use cases as it effects boot time. But still keeping this support as this is a valid boot scenario. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | test/py: avb: fix test_avb_persistent_values failIgor Opaniuk2019-05-091-1/+1
| | | | | | | | | | | | | | | | Fix test_avb_persistent_values() pytest, which was failing because of wrong size value provided from tee sandbox driver. Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
* | ata: ahci: fix memory leakChristian Gmeiner2019-05-091-4/+1
| | | | | | | | | | | | | | | | malloc(..) and memalign(..) are both allocating memory and as a result we leak the memory allocated with malloc(..). Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | usb: ohci: ohci-da8xx: Cleanup Error handling and fix flagsAdam Ford2019-05-091-4/+5
| | | | | | | | | | | | | | | | | | Per feedback from Marek, he suggested better handling and to enable DM_FLAG_OS_PREPARE, this patch re-orders some of the error checking, and errors returns the error code right away and also sets DM_FLAG_OS_PREPARE. Signed-off-by: Adam Ford <aford173@gmail.com>
* | Merge tag 'rockchip-for-v2019.07-rc1' of git://git.denx.de/u-boot-rockchipTom Rini2019-05-0917-413/+938
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Improvements and new features: - split more rockchip pinctrl_core feature into per SoC - enable TPL for evb-rk3399 board - enable TPL/SPL for evb-px5 board - enable TPL and OP-TEE support for evb-rk3229 - update fix in arm common assembly start code for rockchip header file - update default SPL_FIT_GENERATOR for rockchip - rk3399 boards update to use '-u-boot.dtsi' - add new rk3399 boards: Nanopi M4, Nanopc T4 - enable sound for chromebook_minnie
| * | pinctrl: rockchip: Also move common set_schmitter func into per Soc fileDavid Wu2019-05-084-21/+37
| | | | | | | | | | | | | | | | | | | | | | | | Only some Soc need Schmitter feature, so move the implementation into their own files. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | pinctrl: rockchip: Clean the unused type and labelDavid Wu2019-05-0810-30/+0
| | | | | | | | | | | | | | | | | | | | | | | | As the mux/pull/drive feature implement at own file, the type and label are not necessary. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | pinctrl: rockchip: Special treatment for RK3288 gpio0 pins' pullDavid Wu2019-05-081-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | RK3288 pmu_gpio0 pull setting have no higher 16 writing corresponding bits, need to read before write the register. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | pinctrl: rockchip: Split the common set_pull() func into per SocDavid Wu2019-05-0811-112/+275
| | | | | | | | | | | | | | | | | | | | | | | | As the common set_mux func(), implement the feature at the own file for each Soc. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | pinctrl: rockchip: Special treatment for RK3288 gpio0 pins' drive strengthDavid Wu2019-05-081-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | RK3288 pmu_gpio0 drive strength setting have no higher 16 writing corresponding bits, need to read before write the register. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | pinctrl: rockchip: Split the common set_drive() func into per SocDavid Wu2019-05-088-100/+224
| | | | | | | | | | | | | | | | | | | | | | | | As the common set_mux func(), implement the feature at the own file for each Soc. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | pinctrl: rockchip: Special treatment for RK3288 gpio0 pins' iomuxDavid Wu2019-05-081-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | RK3288 pmu_gpio0 iomux setting have no higher 16 writing corresponding bits, need to read before write the register. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | pinctrl: rockchip: Split the common set_mux() into per SocDavid Wu2019-05-0811-32/+297
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Such as rk3288's pins of pmu_gpio0 are a special feature, which have no higher 16 writing corresponding bits, use common set_mux() func would introduce more code, so implement their set_mux() in each Soc's own file to reduce the size of code. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | pinctrl: rockchip: Remove redundant spacesDavid Wu2019-05-087-63/+63
| | | | | | | | | | | | | | | | | | | | | Some files have the redundant spaces, remove them. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | pinctrl: rockchip: Add pull-pin-default param and remove unused paramDavid Wu2019-05-081-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | Some Socs use the pull-pin-default config param, need to add it. And input-enable/disable config params are not necessary, remove it. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | Revert "pinctrl: rockchip: Add 32bit writing function for rk3288 gpio0 pinctrl"Kever Yang2019-05-083-76/+13
| | | | | | | | | | | | | | | | | | | | | This reverts commit 502980914b2d6f9ee85a823aa3ef9ead76c0b7f2. This is a superseded version, revert this to apply new patch set. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: ram: rk3399: update for TPLKever Yang2019-05-081-5/+10
| | | | | | | | | | | | | | | | | | | | | Init the ddr sdram in TPL instead of SPL, update the code. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
| * | rockchip: dmc: rk3368: update rank number for evb-px5Kever Yang2019-05-081-0/+4
| | | | | | | | | | | | | | | | | | | | | evb-px5 has only 1 CS, update for it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
| * | sysreset: enable driver support in SPL/TPLKever Yang2019-05-082-1/+19
| | | | | | | | | | | | | | | | | | SPL/TPL also need use sysreset for some feature like panic callback. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: clk: rk322x: fix assert clock valueKever Yang2019-05-081-2/+2
| | | | | | | | | | | | | | | | | | BUS_PCLK_HZ and BUS_HCLK_HZ are from BUS_ACLK_HZ, not from GPLL_HZ. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: rk322x: add CLK_EMMC_SAMPLE clock supportKever Yang2019-05-081-0/+2
| | | | | | | | | | | | Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | Revert "rockchip: rk322x: ram: enable DRAM init in SPL instead of TPL"Kever Yang2019-05-081-6/+6
| | | | | | | | | | | | | | | | | | This reverts commit f338cca1d2bce906b049722d2fdbf527a4963b61. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
View Lorry Controller Status