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* Merge git://git.denx.de/u-boot-marvellTom Rini2018-03-305-53/+791
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| * arm64: a37xx: pci: add support for aardvark pcie driverWilson Ding2018-03-303-0/+701
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduced the Aardvark PCIe driver based driver model. The PCIe driver is supposed to work in Root Complex mode. It only supports X1 lane width. Signed-off-by: Wilson Ding <dingwei@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38725 Reviewed-by: Victor Gu <xigu@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: Hua Jing <jinghua@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm64: a37xx: pinctrl: Correct mpp definitionsKen Ma2018-03-301-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch corrects below mpp definitions: - The sdio_sb group is composed of 6 pins and not 5; - The rgmii group contains pins mpp2[17:6] and not mpp2[19:6]; - Pin of group "pmic0" is mpp1[6] but not mpp1[16]; - Pin of group "pmic1" is mpp1[7] but not mpp1[17]; - A new group "smi" is added in A0 with 2 pins - mpp2[19:18], its bitmask is bit4; - Group "pcie1" has 3 pins in A0 - mpp2[5:3], its bit mask is bit5 | bit9 | bit10 but not bit4; - Group "ptp" has 3 pins in A0 as Z1, but its bitmask is changed to bit11 | bit12 | bit13. Reviewed-on: http://vgitil04.il.marvell.com:8080/43288 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm64: a37xx: pinctrl: Fix gpio pin offset in registerKen Ma2018-03-301-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For armada_37xx_update_reg(), the parameter offset should be pointer so that it can be updated, otherwise offset will keep old value, and then when offset is larger than or equal to 32 the mask calculated by "BIT(offset)" will be 0 in gpio chip hook functions, it's an error, this patch set offset parameter of armada_37xx_update_reg() as pointer. Reviewed-on: http://vgitil04.il.marvell.com:8080/43287 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm64: a37xx: pinctrl: Fix the pin 23 on south bridgeKen Ma2018-03-301-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin 23 on South bridge does not belong to the rgmii group. It belongs to a separate group which can have 3 functions. Due to this the fix also have to update the way the functions are managed. Until now each groups used NB_FUNCS(which was 2) functions. For the mpp23, 3 functions are available but it is the only group which needs it, so on the loop involving NB_FUNCS an extra test was added to handle only the functions added. The bug was visible when the gpio regulator used the gpio 23, the whole rgmii group was setup to gpio which broke the Ethernet support on the Armada 3720 DB board. Thanks to this patch, the UHS SD cards (which need the vqmmc) _and_ the Ethernet work again. Reviewed-on: http://vgitil04.il.marvell.com:8080/43284 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm64: a37xx: pinctrl: Fix number of pin in south bridgeKen Ma2018-03-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | On the south bridge we have pin from 0 to 29, so it gives 30 pins (and not 29). Reviewed-on: http://vgitil04.il.marvell.com:8080/43285 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * dm: pcie: designware: add correct ATU handlingIgal Liberman2018-03-301-33/+58
| | | | | | | | | | | | | | | | | | | | | | | | Currently, ATU (address translation unit) implementation doesn't support translate addresses > 32 bits. This patch allows to configure ATU correctly for different memory accesses (memory, configuration and IO). The same approach is used in Linux Kernel. Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge git://git.denx.de/u-boot-x86Tom Rini2018-03-302-5/+8
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| * | x86: mmc: Fix mapping of BAR memoryBernhard Messerklinger2018-03-301-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use dm_pci_map_bar function for BAR mapping. This has the advantage of clearing BAR flags and and only accepting mapped memory. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | dm: pci: Avoid setting a PCI region that has 0 sizeBin Meng2018-03-301-2/+3
| | | | | | | | | | | | | | | | | | | | | It makes no sense to set a PCI region that has 0 size. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | dm: pci: Check board information pointer in decode_regions()Bin Meng2018-03-301-0/+3
| |/ | | | | | | | | | | | | | | | | | | | | | | PCI enumeration may happen very early on an x86 board. The board information pointer should have been checked in decode_regions() as its space may not be allocated yet. With this commit, Intel Galileo board boots again. Fixes: 664758c ("pci: Fix decode regions for memory banks") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-riscvTom Rini2018-03-305-254/+131
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| * | mmc: ftsdc010: Merge nds32_mmc to ftsdc010Rick Chen2018-03-305-165/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nsd32_mmc was created to support ftsdc010 dm. It is not necessary to separate both, so merge it to ftsdc010. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Cc: Greentime Hu <green.hu@gmail.com>
| * | mmc: ftsdc010: Migrate CONFIG_FTSDC010_SDIO to KconfigRick Chen2018-03-301-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert CONFIG_FTSDC010_SDIO to Kconfig. So CONFIG_FTSDC010_SDIO can also be removed from config_whitelist.txt. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Cc: Greentime Hu <green.hu@gmail.com>
| * | mmc: ftsdc010: Drop non-dm codeRick Chen2018-03-302-103/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only three defconfig(adp-ag101p_defconfig, adp-ae3xx_defconfig, nx25-ae250_defconfig) set CONFIG_FTSDC010=y. And they all also enable CONFIG_DM_MMC. So the non-dm code of ftsdc010 can be dropped now. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Cc: Greentime Hu <green.hu@gmail.com>
| * | mmc: ftsdc010: Support High-Speed modeRick Chen2018-03-301-0/+5
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | ftsdc010 dm driver has been disable High-Speed mode as default to work around Andes AE3XX platform's problem, because of it does not support High-Speed mode in commit id 73cd56b2df213c629191139e5c6705e069b6214f. But other platforms or SoCs maybe support this function. So High-Speed mode can be enabled from dts with cap-mmc-highspeed or cap-sd-highspeed property. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com>
* | rockchip: sdhci: support 8bit bus-widthPhilipp Tomsich2018-03-281-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Rockchip-specific SDHCI wrapper does not process the 'bus-width' property in the SDHCI node. Consequently, the bus is always kept in 4bit mode, even if 8bit wide operation is available, supported and requested in the DTS. This change adds processing of the 'bus-width' property and sets the host capability flag for an 8bit wide bus, if set to 8. As the logic in sdhci.c does not support clearing the 4bit capability, we assume that 4bit operation is always supported. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | rockchip: clk: rk3188: update dpll settings to make EMAC workAlexander Kochetkov2018-03-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch set dpll settings for 300MHz to values used by binary blob[1]. With new values dpll still generate 300MHz clock, but EMAC work. Probably with new values dpll generate more stable clock. dpll on rk3188 provide clocks to DDR and EMAC. With current dpll settings EMAC doesn't work on radxa rock. EMAC sends packets to network, but it doesn't receive anything. ifconfig shows a lot of framing errors. [1] https://github.com/linux-rockchip/u-boot-rockchip/blob/u-boot-rk3288/ tools/rk_tools/3188_LPDDR2_300MHz_DDR3_300MHz_20130830.bin Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | video: rk3288_mipi: Combine NULL check into IS_ERR_OR_NULL()Punit Agrawal2018-03-281-1/+1
| | | | | | | | | | | | Signed-off-by: Punit Agrawal <punit.agrawal@arm.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | video: rk3288_mipi: check in rk_mipi_ofdata_to_platdataHeinrich Schuchardt2018-03-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | The error checking should also catch the case that no range has beeen defined. syscon_get_first_range() returns NULL if no range is defined. cf. rk3399_mipi.c Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | video: rk3399_mipi: Combine NULL check into IS_ERR_OR_NULL()Punit Agrawal2018-03-281-1/+1
| | | | | | | | | | | | Signed-off-by: Punit Agrawal <punit.agrawal@arm.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | video: rk3399_mipi: correct error checkingHeinrich Schuchardt2018-03-281-1/+1
| | | | | | | | | | | | | | | | | | Pointers are never negative. Use macro IS_ERR() for checking. cf. rk3288_mipi.c Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | usb: rockchip: remove duplicate assignement.Heinrich Schuchardt2018-03-281-1/+0
| | | | | | | | | | | | | | | | Assigning f_rkusb->reboot_flag twice doesn't make sense. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | driver: ram: rockchip: rk3399: missing counter incrementHeinrich Schuchardt2018-03-281-0/+1
| | | | | | | | | | | | | | | | If we want to check the duration we need to increment the counter. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | rockchip: pinctrl: rk3188: Move the iomux definitions into pinctrl-driverAlexander Kochetkov2018-03-281-0/+380
| | | | | | | | | | | | | | | | | | Clean the iomux definitions at grf_rk3188.h, and move them into pinctrl-driver for resolving the compiling error of redefinition. Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | rockchip: pinctrl: rk3036: Move the iomux definitions into pinctrl-driverAlexander Kochetkov2018-03-281-0/+410
| | | | | | | | | | | | | | | | | | Clean the iomux definitions at grf_rk3036.h, and move them into pinctrl-driver for resolving the compiling error of redefinition. Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | rockchip: pinctrl: rk3399: add support for I2C[123467]Philipp Tomsich2018-03-281-6/+55
|/ | | | | | | | | | This adds support for the (to date unsupported) I2C controllers 1~4 and 6~7 (i.e. now all controllers except I2C5, which is not accessible on the RK3399-Q7, are supported by pinctrl). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* Merge git://git.denx.de/u-boot-ubiTom Rini2018-03-251-0/+7
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| * Convert CONFIG_UBI_SILENCE_MSG to KconfigPetr Vorel2018-03-241-0/+7
| | | | | | | | Signed-off-by: Petr Vorel <petr.vorel@gmail.com>
* | Merge git://git.denx.de/u-boot-spiTom Rini2018-03-252-47/+89
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| * | omap3: spi: Correct ti, pindir-d0-out-d1-in parsingSjoerd Simons2018-03-231-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | The ti,pindir-d0-out-d1-in property is not expected to have a value according to the device-tree binding, so treat it as a boolean not a uint property. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | DW SPI: use 32 bit access instead of 16 and 32 bit mixEugeniy Paltsev2018-03-221-25/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current DW SPI driver uses 32 bit access for some registers and 16 bit access for others. So if DW SPI IP is connected via bus which doesn't support 16 bit access we will get bus error. Fix that by switching to 32 bit access only instead of 16 and 32 bit mix Additional Documentation to Support this Change: The DW_apb_ssi databook states: "All registers in the DW_apb_ssi are addressed at 32-bit boundaries to remain consistent with the AHB bus. Where the physical size of any register is less than 32-bits wide, the upper unused bits of the 32-bit boundary are reserved. Writing to these bits has no effect; reading from these bits returns 0." [1] [1] Section 6.1 of dw_apb_ssi.pdf (version 3.22a) Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | DW SPI: add option to use external gpio for chip selectEugeniy Paltsev2018-03-221-1/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DW SPI internal chip select management has limitation: it hold CS line in active state only when the FIFO is not empty. If the FIFO freed before we add new data the SPI transaction will be broken. So add option to use external gpio for chip select. Gpio can be added via device tree using standard gpio bindings. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | DW SPI: refactor poll_transfer functionsEugeniy Paltsev2018-03-221-22/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no sense in waiting for RX data in dw_reader function: there is no chance that RX data will appear in RX FIFO if RX FIFO is empty after previous TX write in dw_writer function. So get rid of this waiting. After that we can get rid of dw_reader return value and make it returning void. After that we can get rid of dw_reader return value check in poll_transfer function. With these changes we're getting closer to Linux DW SPI driver. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | DW SPI: fix transmit only modeEugeniy Paltsev2018-03-221-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In current implementation we get -ETIMEDOUT error when we try to use transmit only mode (SPI_TMOD_TO) This happens because in transmit only mode input FIFO never gets any data which breaks our logic in dw_reader(): we are waiting until RX data will be ready in dw_reader, but this newer happens, so we return with error. Fix that by using SPI_TMOD_TR instead of SPI_TMOD_TO which allows to use RX FIFO. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | DW SPI: fix tx data loss on FIFO flushEugeniy Paltsev2018-03-221-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In current implementation if some data still exists in Tx FIFO it can be silently flushed, i.e. dropped on disabling of the controller, which happens when writing 0 to DW_SPI_SSIENR (it happens in the beginning of new transfer) So add wait for current transmit operation to complete to be sure that current transmit operation is finished before new one. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | | Merge git://git.denx.de/u-boot-i2cTom Rini2018-03-251-5/+5
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| * | | i2c: lpi2c: remove superfluous assignmentsHeinrich Schuchardt2018-03-231-5/+5
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | In lpi2c_status_t result = A; result = B; the first assignment has no effect. Let's remove it. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | | arm64: zynqmp: Print the value of pl clocks and wdt clock using clk dumpVipul Kumar2018-03-231-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | This patch print pl clocks (pl0...pl3) and watchdog clock using clk dump. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | arm64: zynqmp: nand: Fixed NAND erase issue for size 1GiB or moreVipul Kumar2018-03-231-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NAND erase was not happening for size 1GiB or more. Erase command was executing successfully but in actual, it was not erasing. This patch fixed erase issue for 1 GiB or more size nand. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | watchdog: Add Cadence watchdog driverShreenidhi Shedi2018-03-233-0/+293
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This IP can be found on Zynq and ZynqMP devices. The driver was tested with reset-on-timeout; feature. Also adding WATCHDOG symbol to Kconfig because it is required. Signed-off-by: Shreenidhi Shedi <imshedi@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | clk: zynq: Show watchdog clock rate properlyMichal Simek2018-03-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | watchdog clock is also connected to cpu 1X clocksource. Zynq> clk dump ... Before: swdt 4294967290 After: swdt 111111110 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | net: zynq_gem: Dont run any phy detection logic for GMII caseSiva Durga Prasad Paladugu2018-03-231-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch bypasses phy detection logic for GMII interface and just depend on phy address received from DT. This patch is required as phy detection logic is different for some phys like xilinx phy which can be connected over SGMII and GMII interface. This fixes the issue of ethernet failures when xilinx phy is connected over GMII interface. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | | fpga: Simplify error path in fpga_addMichal Simek2018-03-231-10/+11
|/ / | | | | | | | | | | | | | | Check !desc earlier to simplify code. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Reviewed-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
* | Merge git://git.denx.de/u-boot-netTom Rini2018-03-2220-1229/+3066
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| * | net: Drop CONFIG_ENC28J60Tuomas Tynkkynen2018-03-223-1198/+0
| | | | | | | | | | | | | | | | | | | | | | | | Last user of this driver went away in October 2014 in commit d58a9451e7339ed4 ("ppc/arm: zap EMK boards"). Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: macb: remove superfluous logical constraintHeinrich Schuchardt2018-03-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In if (a > =0) {...} else (a < 0) {...} the second logical constraint is superfluous. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | drivers: net: cpsw: remove superfluous assignment.Heinrich Schuchardt2018-03-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In int ret = A; ret = B; the first assignment has not effect. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | lan7xxx: Require phylibAlexander Graf2018-03-221-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | The lan75xx and lan78xx drivers need to drive their phy via the generic phylib framework. Let's reflect that dependency in Kconfig, so that we don't get build errors when phylib does not get selected. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net/phy/cortina: Add No firmware upload optionPriyanka Jain2018-03-221-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current Cortina phy driver assumes that firmware upload is required during initialization and is dependent on presence of corresponding macros like CONFIG_CORTINA_FW_ADDR for compilation. But Cortina phy has provision to store phy firmware in attached dedicated EEPROM. And boards designed with such EEPROM does not require firmware upload. Add CORTINA_NO_FW_UPLOAD option in cortina.c to support such boards. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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