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* net: cpsw: Add __maybe_unused to generated inlinesTom Rini2020-06-161-2/+3
| | | | | | | | | | | We generate a number of helper inline functions to make accesses easier. However not all permutations of each function will be used and clang will warn about unused ones. Decorate all of them with __maybe_unused because of this. Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
* mmc: omap_hsmmc: Add guards around omap_hsmmc_get_cfg()Tom Rini2020-06-161-0/+3
| | | | | | | | | | | | We only call the function omap_hsmmc_get_cfg in the case of OMAP34XX or when we have to iodelay recalibration. Add guards for these checks as clang will otherwise warn. Cc: Peng Fan <peng.fan@nxp.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* gpio: omap_gpio: Fix unused function warning in non-DM caseTom Rini2020-06-161-5/+4
| | | | | | | | | | In the case of non-DM_GPIO the function get_gpio_index() will never be called, and clang will warn about this. Move this to be with the other non-DM code for easier removal later. Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* phy: omap-usb2-phy: disable phy charger detectBin Liu2020-06-161-5/+28
| | | | | | | | | | | | | AM654x PG1.0 has a silicon bug that D+ is pulled high after POR, which could cause enumeration failure with some USB hubs. Disabling the USB2_PHY Charger Detect function will put D+ into the normal state. Using property "ti,dis-chg-det-quirk" in the DT usb2-phy node to enable this workaround for AM654x PG1.0. Signed-off-by: Bin Liu <b-liu@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com>
* mmc: davinci_mmc: Cleanup to use dt in U-boot and static platdata in SPLFaiz Abbas2020-06-131-37/+26
| | | | | | | | | | | | | | | | | Cleanup this driver to use dt in U-boot and static platdata in SPL. This requires the following steps: 1. Move all platdata assignment from probe() to ofdata_to_platdata(). This function is only called in U-boot. 2. Replicate all the platdata assignment being done in ofdata_to_platdata() in the omapl138 board file. This data is used in the SPL case where SPL_OF_CONTROL is not enabled. 3. Remove SPL_OF_CONTROL and related configs from omapl138_lcdk_defconfig This cleanup effectively reverts 3ef94715cc ('mmc: davinci: fix mmc boot in SPL') Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Tested-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
* Merge tag 'u-boot-imx-20200609' of ↵WIP/09Jun2020Tom Rini2020-06-091-0/+7
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx Fixes for 2020.07 ----------------- - mx53: mx53menlo Convert to DM_ETH, fix fail boot - imx8mp_evk: fix boot issue - MX6, display5: fix environment - drop warnings (watchdog) for i.MX8mm i.mx8mp - enable bootaux for i.MX8M Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/695929999
| * power: pmic: Add SPL Kconfig entry for PFUZE100Marek Vasut2020-06-081-0/+7
| | | | | | | | | | | | | | | | | | | | | | Add Kconfig entry for the PFUZE PMIC, SPL variant. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xxWIP/08Jun2020Tom Rini2020-06-088-71/+273
|\ \ | | | | | | | | | | | | | | | | | | - DM_ETH support for P2041RDB, T1024RDB, P5040DS, P3041DS, P4080DS, bug fixes - Add TBI PHY access through MII - DDR: Rework errata workaround for A008109, A008378, 009942
| * | ddr: Rework errata A008109, A008378, 009942 workaroundJaiprakash Singh2020-06-043-65/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move errata A008109, A008378, 009942 workaround implementation from compute_fsl_memctl_config_regs() to fsl_ddr_set_memctl_regs() and add register write after each workaround implementation. Signed-off-by: Jaiprakash Singh <Jaiprakash.singh@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | ddr: fsl: Impl. Erratum A008109Joakim Tjernlund2020-06-042-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | Impl. erratum as descibed in errata doc. Enable A008109 for T1040 and T1024 Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | net: tsec: Access TBI PHY through the corresponding MIIHou Zhiqiang2020-06-041-4/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When an eTSEC is configured to use TBI, configuration of the TBI is done through the MIIM registers for that eTSEC. For example, if a TBI interface is required on eTSEC2, then the MIIM registers starting at offset 0x2_5520 are used to configure it. Fixes: 9a1d6af55ecd ("net: tsec: Add driver model ethernet support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | net: tsec: Access eTSEC registers using virtual addressHou Zhiqiang2020-06-041-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code accesses eTSEC registers using physical address directly, it's not correct, though no problem on current platforms. It won't work on platforms, which does not support 1:1 virtual-physical address map. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | net: tsec: fsl_mdio: add DM MDIO supportMadalin Bucur2020-06-041-6/+134
| | | | | | | | | | | | | | | | | | | | | Allow the MDIO devices to be probed based on the device tree. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | drivers: net: qe: deselect QE when DM_ETH is enabledMadalin Bucur2020-06-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A compilation error appears when QE is compiled with DM_ETH enabled: drivers/qe/uec.c: In function 'init_phy': drivers/qe/uec.c:425:28: error: dereferencing pointer to incomplete type 'struct eth_device' uec = (uec_private_t *)dev->priv; ^~ drivers/qe/uec.c: In function 'uec_initialize': drivers/qe/uec.c:1357:43: error: invalid application of 'sizeof' to incomplete type 'struct eth_device' dev = (struct eth_device *)malloc(sizeof(struct eth_device)); ^~~~~~ The patch disables CONFIG_QE when CONFIG_DM_ETH is set. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | drivers: net: e1000: with DM_ETH needs DM_PCI tooMadalin Bucur2020-06-031-0/+1
| | | | | | | | | | | | | | | | | | | | | Compilation error occur when DM_ETH is enabled without DM_PCI. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | | virtio: VIRTIO_RNG depends on DM_RNGHeinrich Schuchardt2020-06-051-5/+7
| |/ |/| | | | | | | | | | | | | Add the missing Kconfig dependency and let VIRTIO_RNG default to yes. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | serial: Add missing Kconfig dependencies for debug consolesMichal Simek2020-06-041-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Debug console is the part of serial driver in the same file. It means to be able to enable debug console you also need to enable driver itself. That's why add all dependecies and list only debug consoles which are enabled based on driver selection to avoid compilation error when user asks for certain debug console but driver is not enable for it. Error: aarch64-linux-gnu-ld.bfd: common/built-in.o: in function `putc': /home/monstr/data/disk/u-boot/common/console.c:513: undefined reference to `printch' aarch64-linux-gnu-ld.bfd: common/built-in.o: in function `puts': /home/monstr/data/disk/u-boot/common/console.c:563: undefined reference to `printch' Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Fix ns16550 dependency, add ZYNQ_SERIAL, change S5P] Signed-off-by: Tom Rini <trini@konsulko.com>
* | serial: Convert ARM_DCC to KconfigTom Rini2020-06-041-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | The symbol "CONFIG_ARM_DCC" is used to control building drivers/serial/arm_dcc.c. Provide a simple Kconfig entry for this. Cc: Luca Ceresoli <luca@lucaceresoli.net> Cc: Michal Simek <monstr@monstr.eu> Cc: Tom McLeod <tom.mcleod@opalkelly.com> Cc: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
* | clk: sifive: fu540-prci: Release ethernet clock resetPragnesh Patel2020-06-041-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | U-Boot ethernet works with FSBL flow where releasing ethernet clock reset is part of FSBL itself but with the SPL, We need to release ethernet clock reset explicitly for U-Boot proper. With this change Release ethernet clock reset code in FSBL might not be needed or unaffected. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* | clk: sifive: fu540-prci: Add ddr clock initializationPragnesh Patel2020-06-041-6/+45
| | | | | | | | | | | | | | | | | | | | Release ddr clock reset once clock is initialized Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
* | clk: sifive: fu540-prci: Add clock enable and disable opsPragnesh Patel2020-06-041-12/+96
| | | | | | | | | | | | | | | | | | | | Added clock enable and disable functions in prci ops Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
* | sifive: fu540: add ddr driverPragnesh Patel2020-06-045-0/+432
| | | | | | | | | | | | | | | | | | Add driver for fu540 to support ddr initialization in SPL. This driver is based on FSBL (https://github.com/sifive/freedom-u540-c000-bootloader.git) Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* | misc: add driver for the SiFive otp controllerPragnesh Patel2020-06-043-0/+283
| | | | | | | | | | | | | | | | | | | | Added a misc driver to handle OTP memory in SiFive SoCs. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spiTom Rini2020-06-0312-449/+167
|\ \ | | | | | | | | | | | | | | | - Toshiba spinand (Yoshio) - SPI/SPI Flash cleanup (Jagan) - Remove SH SPI (Jagan)
| * | mtd: sf: Drop plat from sf_probeJagan Teki2020-06-011-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dm_spi_slave_platdata used in sf_probe for printing plat->cs value and there is no relevant usage apart from this. We have enough debug messages available in SPI and SF areas so drop this plat get and associated bug statement. Cc: Simon Glass <sjg@chromium.org> Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | mtd: spi: Call sst_write in _write opsJagan Teki2020-06-011-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently spi-nor code is assigning _write ops for SST and other flashes separately.  Just call the sst_write from generic write ops and return if SST flash found, this way it avoids the confusion of multiple write ops assignment during the scan and makes it more feasible for code readability. No functionality changes. Cc: Simon Glass <sjg@chromium.org> Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sf: Drop spl_flash_get_sw_write_protJagan Teki2020-06-015-38/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The get_sw_write_prot API is used to get the write-protected bits of flash by reading the status register and other wards it's API for reading register bits. 1) This kind of requirement can be achieved using existing flash operations and flash locking API calls instead of making a separate flash API. 2) Technically there is no real hardware user for this API to use in the source tree. 3) Having a flash operations API for simple register read bits also make difficult to extend the flash operations. 4) Instead of touching generic code, it is possible to have this functionality inside spinor operations in the form of flash hooks or fixups for associated flash chips. Considering all these points, this patch drops the get_sw_write_prot and associated code bases. Cc: Simon Glass <sjg@chromium.org> Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | mtd: spi: Use CONFIG_IS_ENABLED to prevent ifdefJagan Teki2020-06-012-9/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use CONFIG_IS_ENABLED to prevent ifdef in sf_probe.c Cc: Simon Glass <sjg@chromium.org> Cc: Vignesh R <vigneshr@ti.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | spi: Zap sh_spi driverJagan Teki2020-06-014-325/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | sh_spi driver is deprecated, no active updates and no board user, hence dropped the same. Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | spi: Kconfig: Move MSCC_BB_SPI, FSL_QSPI into DM_SPIJagan Teki2020-06-011-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - MSCC_BB_SPI - FSL_QSPI Both are fully dm-driven, let's move them into DM_SPI side definition. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | spi: Kconfig: Drop redundant CF_SPI definitionJagan Teki2020-06-011-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | CF_SPI kconfig option defined twice with DM_SPI and non DM_SPI. Drop the non DM_SPI side kconfig definition. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | spi Drop spi_init()Jagan Teki2020-06-012-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | spi_init doesn't exist anywhere in the code. Drop it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | mtd: spinand: toshiba: Support for new Kioxia Serial NANDYoshio Furuyama2020-05-281-16/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for new Kioxia products. The new Kioxia products support program load x4 command, and have HOLD_D bit which is equivalent to QE bit. Signed-off-by: Yoshio Furuyama <ytc-mb-yfuruyama7@kioxia.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/aa69e455beedc5ce0d7141359b9364ed8aec9e65.1584949601.git.ytc-mb-yfuruyama7@kioxia.com Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | mtd: spinand: toshiba: Rename function name to change suffix and prefix (8Gbit)Yoshio Furuyama2020-05-281-27/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The suffix was changed from "G" to "J" to classify between 1st generation and 2nd generation serial NAND devices (which now belong to the Kioxia brand). As reference that's 1st generation device of 1Gbit product is "TC58CVG0S3HRAIG" 2nd generation device of 1Gbit product is "TC58CVG0S3HRAIJ". The 8Gbit type "TH58CxG3S0HRAIJ" is new to Kioxia's serial NAND lineup and the prefix was changed from "TC58" to "TH58". Thus the functions were renamed from tc58cxgxsx_*() to tx58cxgxsxraix_*(). Signed-off-by: Yoshio Furuyama <ytc-mb-yfuruyama7@kioxia.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/0dedd9869569a17625822dba87878254d253ba0e.1584949601.git.ytc-mb-yfuruyama7@kioxia.com Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | | Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini2020-06-032-9/+17
|\ \ \ | | | | | | | | | | | | | | | | - H6 emac support - USB PHY H6 logic alignment
| * | | net: sun8i_emac: Add support for the H6 variantSamuel Holland2020-06-011-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The H6 EMAC is very similar to the H3 variant, except that it uses the same pinmux as R40. Add support for it. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | | net: sun8i_emac: Use consistent clock bitfield definitionsSamuel Holland2020-06-011-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While the R40 uses a different register for EMAC clock configuration than other chips, the register has a very similar layout. Reuse the existing bitfield definitions in this file, since they match. This allows the driver to compile on the H6 platform, where the CCM_GMAC_CTRL definitions are not present. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | | phy: sun4i-usb: Align H6 initialization logic with the kernelRoman Stratiienko2020-06-011-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | H6 SOC needs additional initialization of PHY registers. Corresponding changes can be found in the kernel patch [1]. Without this changes there is no enumeration of 'musb' gadget. [1] - https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=ae409cc7c3cdb9ac4a1dba3eae70efec3d6b6c79 Fixes: 35fa673e0e5f ("sunxi: phy: Add USB PHY support for Allwinner H6") Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | | | bootcount_ext: Add Ext4 build dependencyFrédéric Danis2020-06-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This config option depends on EXT4 support. If Ext4 write capability is not selected, it generate write error messages and is unable to maintain boot counter. Signed-off-by: Frédéric Danis <frederic.danis@collabora.com>
* | | | kconfig: fix typo for OHCI host and add to DM listMarcin Juszkiewicz2020-06-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Description said that OHCI is not supported for driver model while it was converted too. Signed-off-by: Marcin Juszkiewicz <marcin@juszkiewicz.com.pl>
* | | | kconfig: mark SPL/TPL options for DM_KEYBOARDMarcin Juszkiewicz2020-06-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | All three options had the same description. Signed-off-by: Marcin Juszkiewicz <marcin@juszkiewicz.com.pl>
* | | | usb: ohci: Add header file for ARCH_DMA_MINALIGNSimon Glass2020-06-021-0/+1
| |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is defined in the asm/cache.h header file. Update this header file to include it so it gets the same value consistently across U-Boot. This fixes 'usb host' on omapl138_lcdk. Fixes: 90526e9fbac ("common: Drop net.h from common header") Reported-by: Adam Ford <aford173@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | x86: spi: Rewrite logic for obtaining the SPI memory mapSimon Glass2020-06-021-15/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present this logic does not work on link and samus, since their SPI controller is not a PCI device, but a child of the PCH. Unfortunately, fixing this involves a lot of extra logic. Still, this was requested in the review of the fix-up patch, so here it is. Fixes: 92842147c31 ("spi: ich: Add support for get_mmap() method") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> (on Intel minnowmax)
* | | Merge tag 'u-boot-rockchip-20200531' of ↵WIP/31May2020Tom Rini2020-05-3115-258/+1344
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - Fix mmc of path after syncfrom kernel dts; - Add dwc3 host support with DM for rk3399; - Add usb2phy and typec phy for rockchip platform; - Migrate board list doc to rockchip.rst; - Add rk3399 Pinebook Pro board support; - Update dram_init in board_init and add memory node in SPL;
| * | driver: usb: drop legacy rockchip xhci driverFrank Wang2020-05-303-207/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | We have changed to use dwc3 generic driver for usb3.0 host, so the legacy Rockchip's xHCI driver is not needed, and drop it. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | usb: dwc3: add make compatible for rockchip platformFrank Wang2020-05-301-6/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RK3399 Type-C PHY is required that must hold whole USB3.0 OTG controller in resetting to hold pipe power state in P2 before initializing the PHY. This commit fixed it and added device compatible for rockchip platform. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | usb: dwc3: amend UTMI/UTMIW phy interface setupFrank Wang2020-05-293-31/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | usb: dwc3: Enable AutoRetry feature in the controllerJagan Teki2020-05-292-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | usb: dwc3: Add disable u2mac linestate check quirkJagan Teki2020-05-292-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | usb: dwc3: add dis_u2_freeclk_exists_quirkFrank Wang2020-05-292-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
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