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* Convert CONFIG_DRIVER_TI_EMAC_USE_RMII to KconfigAdam Ford2020-07-281-0/+6
| | | | | | | This converts the following to Kconfig: CONFIG_DRIVER_TI_EMAC_USE_RMII Signed-off-by: Adam Ford <aford173@gmail.com>
* Merge tag 'u-boot-amlogic-20200727' of ↵Tom Rini2020-07-271-4/+39
|\ | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - Handle errors in Meson serial driver - Enable HDMI, keyboard and ADC for Odroid-C2
| * serial: meson: handle RX errorsNeil Armstrong2020-07-271-4/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This checks and handles RX errors on the Amlogic UART controller after experiencing errors on the Khadas VIM3 & VIM3L when UART AO A lines are not connected. When the RX line is not connected, the first byte is erroneous and breaks the U-Boot autoboot, breaking automatic boot. This checks and drops any erroneous RX byte on pending and getc callbacks to avoid returning true to pending when an error byte is in the FIFO. Fixes: bfcef28ae4 ("arm: add initial support for Amlogic Meson and ODROID-C2") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Guillaume La Roque <glaroque@baylibre.com>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqWIP/27Jul2020Tom Rini2020-07-2730-687/+1464
|\ \ | | | | | | | | | | | | | | | | | | | | | - Bug fixes and updates on ls2088a,ls1028a, ls1046a, ls1043a, ls1012a - lx2-watchdog support - layerscape: pci-endpoint support, spin table relocation fixes and cleanups - fsl-crypto: RNG support and bug fixes
| * | Watchdog: introduce ARM SBSA watchdog driverZhao Qiang2020-07-273-0/+141
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to Server Base System Architecture (SBSA) specification, the SBSA Generic Watchdog has two stage timeouts: the first signal (WS0) is for alerting the system by interrupt, the second one (WS1) is a real hardware reset. More details about the hardware specification of this device: ARM DEN0029B - Server Base System Architecture (SBSA) This driver can operate ARM SBSA Generic Watchdog as a single stage In the single stage mode, when the timeout is reached, your system will be reset by WS1. The first signal (WS0) is ignored. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pci: layerscape: Add specific config entry for RC and EP mode driverHou Zhiqiang2020-07-272-8/+28
| | | | | | | | | | | | | | | | | | | | | | | | Add Root Complex and Endpoint mode specific config entries, such that it's feasible to enable the RC and/or EP mode driver indepently. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pci_ep: layerscape: Add the PCIe EP mode support for lx2160a-v2Xiaowei Bao2020-07-272-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | Add the PCIe EP mode support for lx2160a-v2 platform. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pci: layerscape: Modify the ls_pcie_dump_atu functionXiaowei Bao2020-07-274-14/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | Modify the ls_pcie_dump_atu function, make it can print the INBOUND windows registers. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pci_ep: layerscape: Add the SRIOV VFs of PF supportXiaowei Bao2020-07-273-13/+42
| | | | | | | | | | | | | | | | | | | | | | | | Add the INBOUND configuration for VFs of PF. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pci_ep: layerscape: Add Support for ls2085a and ls2080a EP modeXiaowei Bao2020-07-271-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | Due to the ls2085a and ls2080a use different way to set the BAR size, so add the BAR size init code here. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pci_ep: layerscape: Add the workaround for errata A-009460Xiaowei Bao2020-07-271-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The VF_BARn_REG register's Prefetchable and Type bit fields are overwritten by a write to VF's BAR Mask register. workaround: Before writing to the VF_BARn_MASK_REG register, write 0b to the PCIE_MISC_CONTROL_1_OFF register. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pcie_ep: layerscape: Add the multiple function supportXiaowei Bao2020-07-273-48/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the multiple function support for Layerscape platform, some PEXs of Layerscaple platform have more than one PF. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pci_ep: Add the init functionXiaowei Bao2020-07-271-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some EP deivces need to initialize before RC scan it, e.g. NXP layerscape platform, so add the init function in pci_ep uclass. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pci: layerscape: Split the EP and RC driverXiaowei Bao2020-07-276-497/+735
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split the RC and EP driver, and reimplement the EP driver base on the EP framework. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | i2c: mxc: move i2c_early_init_f to common functionBiwen Li2020-07-271-68/+70
| | | | | | | | | | | | | | | | | | | | | | | | Move i2c_early_init_f to common function to initialize baudrate of i2c Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | crypto/fsl: add RNG supportMichael Walle2020-07-276-0/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | Register the random number generator with the rng subsystem in u-boot. This way it can be used by EFI as well as for the 'rng' command. Signed-off-by: Michael Walle <michael@walle.cc> Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | crypto/fsl: instantiate the RNG with prediciton resistanceMichael Walle2020-07-274-7/+76
| | | | | | | | | | | | | | | | | | | | | | | | If it is already instantiated tear it down first and then reinstanciate it again with prediction resistance. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | crypto/fsl: don't regenerate secure keysMichael Walle2020-07-273-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | The secure keys (TDKEK, JDKEK, TDSK) can only be generated once after a POR. Otherwise the RNG4 will throw an error. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | crypto/fsl: support newer SEC modulesMichael Walle2020-07-271-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since Era 10, the version registers changed. Add the version registers and use them on newer modules. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | crypto/fsl: export caam_get_era()Michael Walle2020-07-271-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | We need the era in other modules, too. For example, to get the RNG version. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | crypto/fsl: make SEC%u status line consistentMichael Walle2020-07-271-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Align the status line with all the other output in U-Boot. Before the change: DDR 3.9 GiB (DDR3, 32-bit, CL=11, ECC on) SEC0: RNG instantiated WDT: Started with servicing (60s timeout) After the change: DDR 3.9 GiB (DDR3, 32-bit, CL=11, ECC on) SEC0: RNG instantiated WDT: Started with servicing (60s timeout) Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | crypto/fsl: unused value in caam_hash_update()Heinrich Schuchardt2020-07-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The value 0 assigned to final is overwritten before ever being used. Remove the assignment. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | crypto/fsl: correct printf() statement.Heinrich Schuchardt2020-07-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | The sequence of arguments should match the format string. For printing unsigned numbers we should use %u. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | Move eSDHC adapter card identification to board filesYangbo Lu2020-07-275-56/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The eSDHC adapter card identification and multiplexing configuration through FPGA had been implemented in both common mmc driver and fsl_esdhc driver. However it is proper to move these code to board files and do it during board initialization. The FPGA registers are also board specific. This patch is to move eSDHC adapter card identification and multiplexing configuration from mmc driver to specific board files. And the option CONFIG_FSL_ESDHC_ADAPTER_IDENT is no longer needed. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> [Rebased, Removed T1040QDS change as board does not exist] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | Drop global data sdhc_adapter for powerpcYangbo Lu2020-07-271-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sdhc_adapter of global data has not been used, and we do not have to use it as global data even we may need it in the future. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | armv8: ls1012a: RGMII ports require internal delayChaitanya Sakinam2020-07-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The correct setting for the RGMII ports on LS1012ARDB is to enable delay on both Rx and Tx so the interface mode used should be PHY_INTERFACE_MODE_RGMII_ID Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com> Signed-off-by: Anji J <anji.jagarlmudi@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | crypto/fsl: fix unaligned accessMichael Walle2020-07-271-14/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On aarch64 running with dcache off, will result in an unaligned access exception: => dcache off => hash sha1 $kernel_addr_r 100 "Synchronous Abort" handler, esr 0x96000061 elr: 00000000960317d8 lr : 00000000960316a4 (reloc) elr: 00000000fbd787d8 lr : 00000000fbd786a4 [..] The compiler emits a "stur x1, [x0, #12]". x1 is might just be 32 bit aligned pointer. Remove the unused u64 element from the union to drop the minimal alignment to 32 bit. Also remove the union, because it is no more needed. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | net: pfe_eth: Use spi_flash_read API to access flash memoryKuldeep Singh2020-07-271-1/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current PFE firmware access spi-nor memory directly. New spi-mem framework does not support direct memory access. So, let's use spi_flash_read API to access memory instead of directly using it. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | fsl_dspi: Introduce DT bindings for CS-SCK and SCK-CS delaysVladimir Oltean2020-07-271-1/+53
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | Communication with some SPI slaves just won't cut it if these delays (before the beginning, and after the end of a transfer) are not added to the Chip Select signal. These are a straight copy from Linux: Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt drivers/spi/spi-fsl-dspi.c Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* | Merge tag 'dm-pull-20jul20-take2a' of ↵Tom Rini2020-07-27175-203/+507
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-dm binman support for FIT new UCLASS_SOC patman switch 'test' command minor fdt fixes patman usability improvements
| * | treewide: convert devfdt_get_addr() to dev_read_addr()Masahiro Yamada2020-07-25118-123/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | treewide: remove (phys_addr_t) casts from devfdt_get_addr()Masahiro Yamada2020-07-255-5/+5
| | | | | | | | | | | | | | | | | | This cast is unneeded. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | treewide: convert (void *)devfdt_get_addr() to dev_read_addr_ptr()Masahiro Yamada2020-07-2546-47/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the _ptr suffixed variant instead of casting. Also, convert it to dev_read_addr_ptr(), which is safe to CONFIG_OF_LIVE. One curious part is an error check like follows in drivers/watchdog/omap_wdt.c: priv->regs = (struct wd_timer *)devfdt_get_addr(dev); if (!priv->regs) return -EINVAL; devfdt_get_addr() returns FDT_ADDR_T_NONE (i.e. -1) on error. So, this code does not catch any error in DT parsing. dev_read_addr_ptr() returns NULL on error, so this error check will work. I generated this commit by the following command: $ find . -name .git -prune -o -name '*.[ch]' -type f -print | \ xargs sed -i -e 's/([^*)]*\*)devfdt_get_addr(/dev_read_addr_ptr(/' I manually fixed drivers/usb/host/ehci-mx6.c Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | dm: soc: Introduce soc_ti_k3 driver for TI K3 SoCsDave Gerlach2020-07-253-0/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce an soc_ti_k3_driver that allows identification and selection of SoC specific data based on the JTAG ID register for device identification, as described for AM65x[0] and J721E[1] devices. [0] http://www.ti.com/lit/ug/spruid7e/spruid7e.pdf [1] http://www.ti.com/lit/ug/spruil1a/spruil1a.pdf Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * | test: Add tests for SOC uclassDave Gerlach2020-07-252-0/+57
| | | | | | | | | | | | | | | | | | | | | Add a sandbox SOC driver, and some tests for the SOC uclass. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * | dm: soc: Introduce UCLASS_SOC for SOC ID and attribute matchingDave Gerlach2020-07-253-0/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce UCLASS_SOC to be used for SOC identification and attribute matching based on the SoC ID info. This allows drivers to be provided for SoCs to retrieve SoC identifying information and also for matching device attributes for selecting SoC specific data. This is useful for other device drivers that may need different parameters or quirks enabled depending on the specific device variant in use. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * | cpu: Convert the methods to use a const udevice *Simon Glass2020-07-256-32/+34
| | | | | | | | | | | | | | | | | | | | | These functions should not modify the device. Convert them to const so that callers don't need to cast if they have a const udevice *. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: core Fix long line in device_bind_common()Simon Glass2020-07-241-1/+2
| |/ | | | | | | | | | | | | Fix an over-length line in this function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-shTom Rini2020-07-279-1/+373
|\ \ | | | | | | | | | - R8A774A1 / Beacon EmbeddedWorks RZG2M Dev Kit support
| * | mmc: renesas-sdhi: Enable support for R8A774A1Adam Ford2020-07-251-1/+1
| | | | | | | | | | | | | | | | | | | | | The r8a774a1 is compatible with the generic rcar-gen3-sdhi controller. This patch adds the compatibilty flag, to support the SDHI controller. Signed-off-by: Adam Ford <aford173@gmail.com>
| * | pinctrl: renesas: Enable R8A774A1 PFC tablesAdam Ford2020-07-254-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PFC tables for the R8A774A1 are already available, but they not enabled. This patch adds the Kconfig option and builds the corresponding file when PINCTRL_PFC_R8A774A1 is enabled. Signed-off-by: Adam Ford <aford173@gmail.com>
| * | clk: renesas: Add R8A774A1 clock tablesAdam Ford2020-07-254-0/+349
| |/ | | | | | | | | | | | | | | This sync's the clock tables with the official release from Linux 5.8-RC2 and update r8a774a1_mstp_table from Ref Manual v1.00. Signed-off-by: Adam Ford <aford173@gmail.com>
* | net: dc2114x: Add DM supportMarek Vasut2020-07-251-2/+145
| | | | | | | | | | | | | | | | | | With all the changes in place, add support for DM into the dc2114x driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Ramon Fried <rfried.dev@gmail.com>
* | net: dc2114x: Split common parts of non-DM functions outMarek Vasut2020-07-251-50/+67
| | | | | | | | | | | | | | | | | | | | | | Split the common code from the non-DM code, so it can be reused by the DM code later. As always, the recv() function had to be split into the actual receiving part and free_pkt part to fit with the DM. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Ramon Fried <rfried.dev@gmail.com>
* | net: dc2114x: Split RX pathMarek Vasut2020-07-251-24/+43
| | | | | | | | | | | | | | | | | | | | | | Split the RX data check from the rest of the RX function, so that the check can be performed separately from the processing of the packet and the release of the received packet once the processing is finished. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Ramon Fried <rfried.dev@gmail.com>
* | net: dc2114x: Add RX/TX rings into the private dataMarek Vasut2020-07-251-46/+46
| | | | | | | | | | | | | | | | | | The RX/TX DMA descriptor rings are per-device-instance private data, so move them into the private data. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Ramon Fried <rfried.dev@gmail.com>
* | net: dc2114x: Pass PCI BDF into phys_to_bus()Marek Vasut2020-07-251-13/+16
| | | | | | | | | | | | | | | | | | | | | | | | This is a trick in preparation for adding DM support. By passing in the PCI BDF into the phys_to_bus() macros and calling that dev, we can substitute dev with udevice when DM support lands and do minor adjustment to the macros to support both DM and non-DM operation. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Ramon Fried <rfried.dev@gmail.com>
* | net: dc2114x: Pass private data aroundMarek Vasut2020-07-251-64/+71
| | | | | | | | | | | | | | | | | | | | This patch replaces the various uses of struct eth_device for accessing device private data with struct dc2114x_priv, which is compatible both with DM and non-DM operation. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Ramon Fried <rfried.dev@gmail.com>
* | net: dc2114x: Introduce private dataMarek Vasut2020-07-251-7/+18
| | | | | | | | | | | | | | | | | | Introduce dc2114x_priv, which is a super-structure around eth_device and tracks per-device state and the device IO address. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Ramon Fried <rfried.dev@gmail.com>
* | net: dc2114x: Use standard I/O accessorsMarek Vasut2020-07-251-2/+3
| | | | | | | | | | | | | | | | | | | | | | The current dc21x4x driver accesses its memory mapped registers directly instead of using the standard I/O accessors. This can cause problems on some systems as the accesses can get out of order. So convert the direct volatile dereferences to use the normal in/out macros. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Ramon Fried <rfried.dev@gmail.com>
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