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* gpio: Convert to use APIs which support live DTPatrick Delaunay2020-12-011-3/+2
| | | | | | | | | Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the driver can support live DT. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
* Merge tag 'mmc-2020-11-29' of ↵WIP/29Nov2020Tom Rini2020-11-292-94/+91
|\ | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-mmc - mmc minor update for better debug and error check - fsl_esdhc sysctl set and make sure delay check for HS400
| * mmc: check a return value about regulator's always-onJaehoon Chung2020-11-281-2/+2
| | | | | | | | | | | | | | | | | | Regulator can be set to "always-on". It's not error about enable/disable. It needs to check about its condition. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
| * mmc: display an error number to debugJaehoon Chung2020-11-281-5/+5
| | | | | | | | | | | | | | It's useful to know an error number when it's debugging. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
| * mmc: fsl_esdhc: make sure delay chain locked for HS400Yangbo Lu2020-11-281-3/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For eMMC HS400 mode, the DLL reset is a required step for mmc rescan. This step has not been documented in reference manual, but the RM will be fixed sooner or later. In previous commit to support eMMC HS400, db8f936 mmc: fsl_esdhc: support eMMC HS400 mode the steps to configure DLL could be found in commit message, 13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL]. 14. Wait for delay chain to lock. these would be fixed as, 13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL]. 13.1 Write DLLCFG0[DLL_RESET] to 1 and wait for 1us, then write DLLCFG0[DLL_RESET] 14. Wait for delay chain to lock. This patch is to add the step of DLL reset, and make sure delay chain locked for HS400. Fixes: db8f93672b42 ("mmc: fsl_esdhc: support eMMC HS400 mode") Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * mmc: fsl_esdhc: set sysctl register for clock initializationYangbo Lu2020-11-281-1/+1
| | | | | | | | | | | | | | | | | | The initial clock setting should be through sysctl register only, while the mmc_set_clock() will call mmc_set_ios() introduce other configurations like bus width, mode, and so on. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * mmc: Add some helper functions for retrying on errorSean Anderson2020-11-281-83/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | All of the existing quirks add retries to various calls of mmc_send_cmd. mmc_send_cmd_quirks is a helper function to do this retrying behavior. It checks if quirks mode is enabled, and if a specific quirk is activated it retries on error. This also adds mmc_send_cmd_retry, which retries on error every time (instead of if a quirk is activated). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | i2c: ocores: add i2c driver for OpenCores I2C controllerPragnesh Patel2020-11-283-0/+645
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the OpenCores I2C controller IP core (See http://www.opencores.org/projects.cgi/web/i2c/overview). This driver implementation is inspired from the Linux OpenCores I2C driver available. Thanks to Peter Korsgaard <peter@korsgaard.com> for writing Linux OpenCores I2C driver. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
* | i2c: designware_i2c: Don't warn if no reset controllerSimon Glass2020-11-281-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | At present if CONFIG_RESET is not enabled, this code shows a warning: designware_i2c_ofdata_to_platdata() i2c_designware_pci i2c2@16,0: Can't get reset: -524 Avoid this by checking if reset is supported, first. Fixes: 622597dee4f ("i2c: designware: add reset ctrl to driver") Signed-off-by: Simon Glass <sjg@chromium.org>
* | i2c: mvtwsi: disable i2c slave also on Armada 8kBaruch Siach2020-11-281-1/+2
|/ | | | | | | | | | | | | The hidden I2C slave is also present on the Armada 8k AP806. Testing shows that this I2C slave causes the same issues as Armada 38x. Disabling that I2C slave fixes all these issues. I2C blocks on the Armada 8k CP110 are not affected. Extend the I2C slave disable to Armada 8k as well. Cc: Stefan Roese <sr@denx.de> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
* phy: stm32: usbphyc: manage optional vbus regulator on phy_power_on/offPatrick Delaunay2020-11-251-10/+23
| | | | | | | | This patch adds support for optional vbus regulator. It is managed on phy_power_on/off calls and may be needed for host mode. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* pinctrl: stmfx: update pin namePatrick Delaunay2020-11-251-4/+4
| | | | | | | | | | Update pin name to avoid duplicated name with SOC GPIO gpio0...gpio15 / agpio0....agpio7: add a stmfx prefix. This pin name can be used in pinmux command. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* pinctrl: stmfx: update pincontrol and gpio device namePatrick Delaunay2020-11-251-1/+4
| | | | | | | | | | The device name is used in pinmux command and in log trace so it is better to use the parent parent name ("stmfx@42" for example) than a generic name ("pinctrl" or "stmfx-gpio") to identify the device instance. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* gpio: stm32: correct the bias managementPatrick Delaunay2020-11-251-14/+14
| | | | | | | | | | | Use the bias configuration for all the GPIO configurations and not only for input GPIO, as indicated in Reference manual (Table 81. Port bit configuration table). Fixes: 43efbb6a3ebf0223f9eab8d45916f602d876319f ("gpio: stm32: add ops get_dir_flags") Fixes: f13ff88b61c32ac8f0e9068c41328b265ef619eb ("gpio: stm32: add ops set_dir_flags") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* pinctrl: stm32: display bias information for all pinsPatrick Delaunay2020-11-251-12/+12
| | | | | | | | | | Display the bias information for input gpios or AF configuration, and not only for output pin, as described in Reference manual (Table 81. Port bit configuration table). Fixes: da7a0bb1f279 ("pinctrl: stm32: add information on pin configuration") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* remoteproc: stm32: update error management in stm32_copro_startPatrick Delaunay2020-11-251-7/+6
| | | | | | | | | | | | | | The coprocessor is running as soon as the hold boot is de-asserted. So indicate this running state and save the resource table even if the protective assert, to avoid autonomous reboot, is failed. This error case should never occurs. Cc: Fabien DESSENNE <fabien.dessenne@st.com> Cc: Arnaud POULIQUEN <arnaud.pouliquen@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* remoteproc: stm32: use reset for hold bootPatrick Delaunay2020-11-251-68/+25
| | | | | | | | | | | | | | | | Use the reset function to handle the hold boot bit in RCC with device tree handle with MCU_HOLD_BOOT identifier. This generic reset allows to remove the two specific properties: - st,syscfg-holdboot - st,syscfg-tz This patch prepares alignment with kernel device tree. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Cc: Fabien DESSENNE <fabien.dessenne@st.com> Cc: Arnaud POULIQUEN <arnaud.pouliquen@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* reset: stm32: Add support of MCU HOLD BOOTPatrick Delaunay2020-11-251-4/+13
| | | | | | | | | | | | | | | Handle the register RCC_MP_GCR without SET/CLR registers but with a direct access to bit BOOT_MCU: - deassert => set the bit: The MCU will not be in HOLD_BOOT - assert => clear the bit: The MCU will be set in HOLD_BOOT With this patch the RCC driver handles the MCU_HOLD_BOOT_R value added in binding stm32mp1-resets.h Cc: Fabien DESSENNE <fabien.dessenne@st.com> Cc: Arnaud POULIQUEN <arnaud.pouliquen@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-usbWIP/22Nov2020Tom Rini2020-11-223-23/+42
|\ | | | | | | - DWC2, DWC3 fixes
| * usb: gadget: dwc2_udc_otg: return zero when reset property is not presentJaehoon Chung2020-11-221-1/+1
| | | | | | | | | | | | | | If reset DT property is not present, -ENOENT is returned. But it's not really error. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
| * usb: dwc3: Handle case where setup_phy is not neededSiva Durga Prasad Paladugu2020-11-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_PHY is not enabled then the dwc3_setup_phy() returns ENOTSUPP which can be still valid and intentional so modify error check to handle this -ENOTSUPP. The same error handling exists in drivers/usb/host/xhci-dwc3.c already added by commit d648a50c0a27 ("dwc3: move phy operation to core.c"). Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * usb: dwc2: add "u-boot,force-vbus-detection" for stm32Patrick Delaunay2020-11-222-21/+40
| | | | | | | | | | | | | | | | | | | | | | On some board, the ID pin is not connected so the B session must be overridden with "u-boot,force_b_session_valid" but the VBus sensing must continue to be handle. To managed it, this patch adds a new DT field "u-boot,force-vbus-detection" to use with "u-boot,force_b_session_valid" Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* | pinctrl: renesas: Drop unused members from struct sh_pfc_pinctrlLad Prabhakar2020-11-221-4/+0
| | | | | | | | | | | | | | Drop unused members from struct sh_pfc_pinctrl. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
* | pinctrl: renesas: r8a7795: Optimize pinctrl image size for R8A774E1Biju Das2020-11-221-2/+12
| | | | | | | | | | | | | | | | | | | | This driver supports both RZ/G2H and R-Car H3 SoCs. Optimize pinctrl image size for RZ/G2H, when support for R-Car H3 (R8A7795) is not enabled Based on the similar patch on Linux. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
* | pinctrl: renesas: r8a77965: Optimize pinctrl image size for R8A774B1Biju Das2020-11-221-0/+12
| | | | | | | | | | | | | | | | | | | | This driver supports both RZ/G2N and R-Car M3-N SoCs. Optimize pinctrl image size for RZ/G2N, when support for R-Car M3-N (R8A77965) is not enabled. Based on the simialr patch on Linux. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
* | pinctrl: renesas: r8a7796: Optimize pinctrl image size for R8A774A1Biju Das2020-11-221-0/+12
| | | | | | | | | | | | | | | | | | | | This driver supports both RZ/G2M and R-Car M3-W/W+ SoCs. Optimize pinctrl image size for RZ/G2M, when support for R-Car M3-W/W+ (R8A7796[01]) is not enabled. Based on the similar patch on Linux. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
* | pinctrl: renesas: r8a77951: Add R8A774E1 PFC supportBiju Das2020-11-225-409/+519
| | | | | | | | | | | | | | | | | | | | | | | | | | Renesas RZ/G2H (r8a774e1) is pin compatible with R-Car H3 (r8a77951), however it doesn't have several automotive specific peripherals. Add a r8a77951 specific pin groups/functions along with common pin groups/functions for supporting both r8a77951 and r8a774e1 SoC. PFC changes are synced from mainline linux-5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
* | pinctrl: renesas: r8a77965: Add R8A774B1 PFC supportBiju Das2020-11-225-405/+513
|/ | | | | | | | | | | | | Renesas RZ/G2N (r8a774b1) is pin compatible with R-Car M3-N (r8a77965), however it doesn't have several automotive specific peripherals. Add a r8a77965 specific pin groups/functions along with common pin groups/functions for supporting both r8a77965 and r8a774b1 SoC. PFC changes are synced from mainline linux-5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
* Merge tag 'efi-2021-01-rc3-2' of ↵WIP/21Nov2020Tom Rini2020-11-211-2/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2021-01-rc3 (2) The parameter check for UEFI service GetNextVariableName() is corrected. The dependencies of CONFIG_DFU_TFTP are simplified. The set of supported hash algorithms reported by the EFI_TCG2_PROTOCOL is corrected.
| * dfu: simplify the dependencies of DFU_TFTPAKASHI Takahiro2020-11-211-2/+1
| | | | | | | | | | | | | | | | | | | | Since CONFIG_UPDATE_COMMON always selects CONFIG_DFU_WRITE_ALT, we can drop the latter from dependencies of CONFIG_DFU_TFTP. Fixes: 3149e524fc1e ("common: update: add a generic interface for FIT image") Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | tpm: spi: Cleanup source codeMichal Simek2020-11-201-3/+0
|/ | | | | | | There is no need for GD to be used and priv variable is unused. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* drivers: led: bcm6858: set the correct led polarity registerSteven Lawrance2020-11-191-4/+4
| | | | | | | | | This change sets the output (hardware) polarity register instead of the input (software) polarity register for the bcm6858 LED controller. The logic was inverted (a LED configued active high behaved as active low). Signed-off-by: Steven Lawrance <steven.lawrance@softathome.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscvWIP/17Nov2020Tom Rini2020-11-171-9/+12
|\ | | | | | | | | | | | | - Enable SATA disk on QEMU RISC-V and update doc. - k210 pinctrl updates: - Fix inverted IE and OE for I2C. - Rename power domains to match datasheet.
| * pinctrl: k210: Rename power domains to match datasheetSean Anderson2020-11-171-5/+5
| | | | | | | | | | | | | | | | This renames power domains to match the names on the k210 datasheet. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com> Reviewed-by: Rick Chen <rick@andestech.com>
| * pinctrl: k210: Fix inverted IE and OE for I2CSean Anderson2020-11-171-4/+7
| | | | | | | | | | | | | | | | | | I2C and SCCB previously shared defaults. However, SCCB needs OE_INV and IE_INV set, but I2C cannot have those bits set. This adds a separate default for SCCB. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com>
* | sunxi: allow to use AXP20[39] attached to I2C0 on V3 seriesIcenowy Zheng2020-11-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | The reference design of Allwinner V3 series uses an AXP203 or AXP209 PMIC attached to the I2C0 bus of the SoC, although the first community-available V3s board, Lichee Pi Zero, omitted it. Allow to introduce support for the PMIC on boards with it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | clk: sunxi: add compatible string for V3Icenowy Zheng2020-11-171-0/+2
| | | | | | | | | | | | | | | | | | | | | | A new compatible string is introduced for V3 CCU, because it has a few extra features available. Add the compatible string to the clock driver. As the extra features are not touched, just share the description struct now. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | sunxi: gpio: introduce compatible string for V3 GPIOIcenowy Zheng2020-11-171-0/+1
|/ | | | | | | | | | A new compatible string is introduced for V3 GPIO, because it has more pins available than V3s. Add the compatible string to the GPIO driver. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* Merge tag 'ti-v2021.01-rc3' of ↵Tom Rini2020-11-162-4/+4
|\ | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-ti - Fix Nokia RX-51 boot issues - Fix CONFIG_LOGLEVEL on K3 devices - Add phyBOARD REGOR support
| * mtd: OneNAND: Set MTD typePali Rohár2020-11-151-0/+1
| | | | | | | | | | | | | | | | | | onenand_probe() function is missing to set mtd->type. So set same type as which sets onenand Linux kernel driver. After this change 'mtd list' prints correct type instead of 'Unknown'. Signed-off-by: Pali Rohár <pali@kernel.org>
| * power: twl4030: Add twl4030_i2c_read() functionPali Rohár2020-11-151-4/+3
| | | | | | | | | | | | | | | | Function twl4030_i2c_read() is like twl4030_i2c_read_u8() but instead of single value it rather returns array of values. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | Merge tag 'u-boot-amlogic-20201116' of ↵Tom Rini2020-11-164-7/+122
|\ \ | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - Clock fix MMC driver for SM1 based platforms - sync SOC Ids from Linux 5.10-rc1 - fix potential build warning on meson_dw_hdmi and meson-g12a-usb2 phy
| * | mmc: meson-gx: change clock phase value on SM1 SoCsNeil Armstrong2020-11-122-4/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Amlogic SM1 SoCs doesn't work over 50MHz. When phase sets to 270', it's working fine over 50MHz on Amlogic SM1 SoCs. Since Other Amlogic SoCs doens't report an issue, phase value is using to 180' by default. To distinguish which value is used adds an u-boot only sm1 compatible. In future, it needs to find what value is a proper about each SoCs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Anand Moon <linux.amoon@gmail.com>
| * | mmc: meson-gx: move arch header to local headerNeil Armstrong2020-11-122-1/+90
| | | | | | | | | | | | | | | | | | | | | Move the asm/arch-meson/sd_emmc.h to a local meson_gx_mmc.h, remove the useless if/then and fix the meson_gx_mmc.c include. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | video: meson: meson_dw_hdmi: fix the potential build warningJaehoon Chung2020-11-121-0/+2
| | | | | | | | | | | | | | | | | | | | | Fix the potential build warning. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | phy: meson-g12a-usb2: fix the potential build warningJaehoon Chung2020-11-121-2/+2
| |/ | | | | | | | | | | | | Fix the potential build warning. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | Merge tag 'u-boot-rockchip-20201113' of ↵Tom Rini2020-11-1610-15/+25
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - Fix USB support for rk3399 Pinebook Pro; - Fix SPI boot for rk3399 boards other than Bob; - Fix 32bit boards firmware build without SPL_OPTEE support; - Fix rockchip display driver license;
| * | video: rockchip: Restrict EDP, VOP, MIPI files to GPL-2.0Alper Nebi Yasak2020-11-139-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These files have a lot of code in common with their counterparts in coreboot, especially in their earlier revisions: U-Boot | coreboot --------------------------------------|-------------------------------------------- drivers/video/rockchip/: | src/soc/rockchip/: - rk_edp.c (GPL-2.0+) | - common/edp.c (GPL-2.0-only) " | - rk3288/display.c (GPL-2.0-only) " | - rk3399/display.c (GPL-2.0-only) - rk_hdmi.h (GPL-2.0+) | (none) - rk_hdmi.c (GPL-2.0+) | - rk3288/hdmi.c (GPL-2.0-or-later) - rk3288_hdmi.c (GPL-2.0+) | - rk3288/hdmi.c (GPL-2.0-or-later) - rk3399_hdmi.c (GPL-2.0+) | (none) - rk_mipi.h (GPL-2.0+) | (none) - rk_mipi.c (GPL-2.0+) | - rk3399/mipi.c (GPL-2.0-only) - rk3288_mipi.c (GPL-2.0+) | - rk3399/mipi.c (GPL-2.0-only) - rk3399_mipi.c (GPL-2.0+) | - rk3399/mipi.c (GPL-2.0-only) - rk_lvds.c (GPL-2.0+) | (none) - rk_vop.h (GPL-2.0+) | (none) - rk_vop.c (GPL-2.0+) | - common/vop.c (GPL-2.0-only) - rk3288_vop.c (GPL-2.0+) | - common/vop.c (GPL-2.0-only) - rk3399_vop.c (GPL-2.0+) | (none) | arch/arm/include/asm/arch-rockchip/: | src/soc/rockchip/*/include/soc/*: - edp_rk3288.h (GPL-2.0+) | - common/.../edp.h (GPL-2.0-only) " | - rk3288/.../display.h (GPL-2.0-only) " | - rk3399/.../display.h (GPL-2.0-only) - vop_rk3288.h (GPL-2.0+) | - common/.../vop.h (GPL-2.0-only) Restrict the licenses to match coreboot's so that changes from coreboot can be imported to U-Boot as necessary. HDMI files are already 2.0+ there and rk_lvds.c has no counterpart, so keep them as is. Cc: Simon Glass <sjg@chromium.org> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Eric Gao <eric.gao@rock-chips.com> Cc: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * | rockchip: rk3399: Init clocks in U-Boot proper if SPL was not runAlper Nebi Yasak2020-11-131-6/+16
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's possible to chainload U-Boot proper from the vendor firmware in rk3399 chromebooks, but the way the vendor firmware sets up clocks is somehow different than what U-Boot expects. This causes the display to stay devoid of content even though vidconsole claims to work (with patches in process of being upstreamed). This is meant to be a rk3399 version of commit d3cb46aa8c41 ("rockchip: Init clocks again when chain-loading") which can detect the discrepancy, but this patch instead checks whether SPL (and therefore the clock init) was run via the handoff functionality and runs the init if it was not. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
* | cros_ec: Handling EC_CMD_GET_NEXT_EVENTHeinrich Schuchardt2020-11-141-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With commit 690079767803 ("cros_ec: Support keyboard scanning with EC_CMD_GET_NEXT_EVENT") check_for_keys() tries to read keyboard strokes using EC_CMD_GET_NEXT_EVENT. But the sandbox driver does not understand this command. We need to reply with -EC_RES_INVALID_COMMAND to force check_for_keys() to fall back to use EC_CMD_MKBP_STATE. Currently the driver prints ** Unknown EC command 0x67 in this case. With the patch the message is suppressed. In a future patch we should upgrade the sandbox driver to provide EC_CMD_GET_NEXT_EVENT support. Fixes: 690079767803 ("cros_ec: Support keyboard scanning with EC_CMD_GET_NEXT_EVENT") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
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