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* crypto/fsl: fix unaligned accessMichael Walle2020-07-271-14/+13
| | | | | | | | | | | | | | | | | | | | On aarch64 running with dcache off, will result in an unaligned access exception: => dcache off => hash sha1 $kernel_addr_r 100 "Synchronous Abort" handler, esr 0x96000061 elr: 00000000960317d8 lr : 00000000960316a4 (reloc) elr: 00000000fbd787d8 lr : 00000000fbd786a4 [..] The compiler emits a "stur x1, [x0, #12]". x1 is might just be 32 bit aligned pointer. Remove the unused u64 element from the union to drop the minimal alignment to 32 bit. Also remove the union, because it is no more needed. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* net: pfe_eth: Use spi_flash_read API to access flash memoryKuldeep Singh2020-07-271-1/+44
| | | | | | | | | | Current PFE firmware access spi-nor memory directly. New spi-mem framework does not support direct memory access. So, let's use spi_flash_read API to access memory instead of directly using it. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* fsl_dspi: Introduce DT bindings for CS-SCK and SCK-CS delaysVladimir Oltean2020-07-271-1/+53
| | | | | | | | | | | | | | Communication with some SPI slaves just won't cut it if these delays (before the beginning, and after the end of a transfer) are not added to the Chip Select signal. These are a straight copy from Linux: Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt drivers/spi/spi-fsl-dspi.c Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscvWIP/24Jul2020Tom Rini2020-07-243-19/+41
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Fix SiFive HiFive Unleashed board booting failure problem. - Enable SiFive fu540 PWM driver. - Support SiFive fu540: SPI boot. - Update OpenSBI used for RISC-V CI testing. - Revert "riscv: Allow use of reset drivers". - Revert "Revert "riscv: sifive: fu540: Add gpio-restart support"". - sysreset: syscon: - Don't assume default value for offset and mask property. - Support value property. - qemu: Add syscon reboot and poweroff support. - Fix SIFIVE debug serial dependency. - Fix linking error when building u-boot-spl with no SMP support. - AE350 use fdtdec_get_addr_size_auto_noparent to parse smc reg. - Make memory node available to SPL in hifive-unleashed-a00-u-boot.dtsi - SiFive fu540 avoid using hardcoded ram base and size.
| * ram: sifive: Avoid using hardcoded ram base and sizeBin Meng2020-07-241-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | At present the SiFive FU540 RAM driver uses hard-coded memory base address and size to initialize the DDR controller. This may not be true when this driver is used on another board based on FU540. Update the driver to read the memory information from DT and use that during the initialization. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Leo Liang <ycliang@andestech.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
| * serial: Fix SIFIVE debug serial dependencyMichal Simek2020-07-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The commit 4cc24aeaf420 ("serial: Add missing Kconfig dependencies for debug consoles") has added incorrect dependency for SIFIVE debug uart which should depend on SIFIVE driver instead of PL01x. Fixes: 4cc24aeaf420 ("serial: Add missing Kconfig dependencies for debug consoles") Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Leo Liang <ycliang@andestech.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
| * sysreset: syscon: Support value propertyBin Meng2020-07-241-5/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | Per the DT binding, <mask> and <value> property can have either one or both, and if <value> is missing, <mask> should be used, which is what current U-Boot sysreset_syscon driver supports. This adds support to the <value> property to the driver, and <mask> semantics is updated to really be a mask to the value if both exist. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
| * sysreset: syscon: Don't assume default value for offset and mask propertyBin Meng2020-07-241-2/+12
| | | | | | | | | | | | | | | | | | | | Per the DT binding, <offset> is a required property. Let's abort the probe if it is missing. For the <mask> property, current codes assume a default value of zero, which is not correct either. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
* | Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"Tom Rini2020-07-24175-507/+203
|/ | | | | | | | | | This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dmTom Rini2020-07-23175-203/+507
|\ | | | | | | | | | | | | | | binman support for FIT new UCLASS_SOC patman switch 'test' command minor fdt fixes patman usability improvements
| * treewide: convert devfdt_get_addr() to dev_read_addr()Masahiro Yamada2020-07-20118-123/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * treewide: remove (phys_addr_t) casts from devfdt_get_addr()Masahiro Yamada2020-07-205-5/+5
| | | | | | | | | | | | This cast is unneeded. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * treewide: convert (void *)devfdt_get_addr() to dev_read_addr_ptr()Masahiro Yamada2020-07-2046-47/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the _ptr suffixed variant instead of casting. Also, convert it to dev_read_addr_ptr(), which is safe to CONFIG_OF_LIVE. One curious part is an error check like follows in drivers/watchdog/omap_wdt.c: priv->regs = (struct wd_timer *)devfdt_get_addr(dev); if (!priv->regs) return -EINVAL; devfdt_get_addr() returns FDT_ADDR_T_NONE (i.e. -1) on error. So, this code does not catch any error in DT parsing. dev_read_addr_ptr() returns NULL on error, so this error check will work. I generated this commit by the following command: $ find . -name .git -prune -o -name '*.[ch]' -type f -print | \ xargs sed -i -e 's/([^*)]*\*)devfdt_get_addr(/dev_read_addr_ptr(/' I manually fixed drivers/usb/host/ehci-mx6.c Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * dm: soc: Introduce soc_ti_k3 driver for TI K3 SoCsDave Gerlach2020-07-203-0/+132
| | | | | | | | | | | | | | | | | | | | | | Introduce an soc_ti_k3_driver that allows identification and selection of SoC specific data based on the JTAG ID register for device identification, as described for AM65x[0] and J721E[1] devices. [0] http://www.ti.com/lit/ug/spruid7e/spruid7e.pdf [1] http://www.ti.com/lit/ug/spruil1a/spruil1a.pdf Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * test: Add tests for SOC uclassDave Gerlach2020-07-202-0/+57
| | | | | | | | | | | | | | Add a sandbox SOC driver, and some tests for the SOC uclass. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * dm: soc: Introduce UCLASS_SOC for SOC ID and attribute matchingDave Gerlach2020-07-203-0/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce UCLASS_SOC to be used for SOC identification and attribute matching based on the SoC ID info. This allows drivers to be provided for SoCs to retrieve SoC identifying information and also for matching device attributes for selecting SoC specific data. This is useful for other device drivers that may need different parameters or quirks enabled depending on the specific device variant in use. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * cpu: Convert the methods to use a const udevice *Simon Glass2020-07-206-32/+34
| | | | | | | | | | | | | | These functions should not modify the device. Convert them to const so that callers don't need to cast if they have a const udevice *. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: core Fix long line in device_bind_common()Simon Glass2020-07-201-1/+2
| | | | | | | | | | | | | | Fix an over-length line in this function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge tag 'u-boot-rockchip-20200722' of ↵WIP/22Jul2020Tom Rini2020-07-2212-388/+418
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - New rk3326 board: Hardkernel Odroid Go2; - Update board config and dts for RockPI 4/N8/N10; - Update led boot on support for roc-rk3399-pc; - Enable SPI Flash suppor for rk3328 rock64 board; - Update rockchip pcie phy to use generic framework;
| * | pci: rockchip: Drop legacy PHY driverJagan Teki2020-07-224-354/+74
| | | | | | | | | | | | | | | | | | | | | | | | Drop the legacy PHY driver and it's associated code since the PHY handling driver now part of Generic PHY framework. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | pci: rockchip: Switch to generic-phyJagan Teki2020-07-223-10/+16
| | | | | | | | | | | | | | | | | | | | | | | | Now, we have a PCIe PHY driver as part of the Generic PHY framework. Let's use it instead of legacy PHY driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | phy: Add Rockchip PCIe PHY driverJagan Teki2020-07-223-0/+279
| | | | | | | | | | | | | | | | | | | | | | | | Add the Rockchip PCIe PHY driver as part of Generic PHY framework. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: ram: fix debug funcfion define when RAM_ROCKCHIP_DEBUG not setKever Yang2020-07-221-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | The empty function define should not be in the header file, or else the build will error with function multi definition after CONFIG_RAM_ROCKCHIP_DEBUG is disabled. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | ram: rk3399: Mark existing prints via RAM_ROCKCHIP_DEBUGJagan Teki2020-07-221-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Right now all these debug statements are printing on the console to make sure proper dram initialization happens.   Mark them into RAM_ROCKCHIP_DEBUG would be more meaningful and work like before since the RAM_ROCKCHIP_DEBUG is by default yet. No functionality changes. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | ram: rk3399: Drop debug stride in driverJagan Teki2020-07-221-25/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | stride debug is already present in sdram_common.c via RAM_ROCKCHIP_DEBUG. So, drop the redundant debug stride code in rk3399 driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | drivers: spi: rk_spi: Add support for RK3328Johannes Krottmayer2020-07-221-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the RK3328 SPI controller Signed-off-by: Johannes Krottmayer <krjdev@gmail.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | drivers: clk: rockchip: clk_rk3328: Add SPI supportJohannes Krottmayer2020-07-221-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add SPI support for the RK3328 clock driver Signed-off-by: Johannes Krottmayer <krjdev@gmail.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | mtd: spinand: micron: Add new Micron SPI NAND devices with multiple diesShivamurthy Shastri2020-07-201-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add device table for new Micron SPI NAND devices, which have multiple dies. Also, enable support to select the dies. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
* | | mtd: spinand: micron: Add M70A series Micron SPI NAND devicesShivamurthy Shastri2020-07-201-0/+20
| | | | | | | | | | | | | | | | | | | | | Add device table for M70A series Micron SPI NAND devices. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
* | | mtd: spinand: micron: identify SPI NAND device with Continuous Read modeShivamurthy Shastri2020-07-201-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SPINAND_HAS_CR_FEAT_BIT flag to identify the SPI NAND device with the Continuous Read mode. Some of the Micron SPI NAND devices have the "Continuous Read" feature enabled by default, which does not fit the subsystem needs. In this mode, the READ CACHE command doesn't require the starting column address. The device always output the data starting from the first column of the cache register, and once the end of the cache register reached, the data output continues through the next page. With the continuous read mode, it is possible to read out the entire block using a single READ command, and once the end of the block reached, the output pins become High-Z state. However, during this mode the read command doesn't output the OOB area. Hence, we disable the feature at probe time. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
* | | mtd: spinand: micron: Add new Micron SPI NAND devicesShivamurthy Shastri2020-07-201-0/+30
| | | | | | | | | | | | | | | | | | | | | Add device table for M79A and M78A series Micron SPI NAND devices. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
* | | mtd: spinand: micron: Describe the SPI NAND device MT29F2G01ABAGDShivamurthy Shastri2020-07-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add the SPI NAND device MT29F2G01ABAGD series number, size and voltage details as a comment. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
* | | mtd: spinand: micron: Generalize the OOB layout structure and function namesShivamurthy Shastri2020-07-201-14/+14
| |/ |/| | | | | | | | | | | | | In order to add new Micron SPI NAND devices, we generalized the OOB layout structure and function names. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
* | dm: core: Don't show an ACPI warning if there is no orderingSimon Glass2020-07-201-1/+1
| | | | | | | | | | | | | | | | | | Some boards don't care about the ordering of ACPI code fragments. Change the warning to a debug message. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* | sysreset: Add Octeon sysreset driverStefan Roese2020-07-183-0/+60
|/ | | | | | | | This patch adds a UCLASS_SYSRESET sysreset driver for the Octeon SoC family. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* mtd: mtdpart: use uint64_t instead of int for cur_offMartin Kaistra2020-07-171-1/+1
| | | | | | | | | | | | | | | | | The types of "offset" and "size" of "struct mtd_partition" are uint64_t, while mtd_parse_partitions() uses int to work with these values. When the offset reaches 2GB, it is interpreted as a negative value, which leads to error messages like mtd: partition "<partition name>" is out of reach -- disabled eg. when using the "ubi part" command. Fix this by using uint64_t for cur_off and cur_sz. Signed-off-by: Martin Kaistra <martin.kaistra@linutronix.de> Reviewed-by: Kurt Kanzenbach <kurt@linutronix.de> Reviewed-by: Heiko Schocher <hs@denx.de>
* treewide: convert bd_t to struct bd_info manuallyMasahiro Yamada2020-07-173-4/+4
| | | | | | | | | | | Some code was not converted by coccinelle, somehow. I manually fixed up the remaining, and comments, README docs. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> [trini: Add arch/arm/mach-davinci/include/mach/sdmmc_defs.h and include/fdt_support.h] Signed-off-by: Tom Rini <trini@konsulko.com>
* treewide: convert bd_t to struct bd_info by coccinelleMasahiro Yamada2020-07-1771-127/+131
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
* Convert CONFIG_MXC_UART to KconfigTom Rini2020-07-171-1/+2
| | | | | | | | This converts the following to Kconfig: CONFIG_MXC_UART Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Peng Fan <peng.fan@nxp.com>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini2020-07-1726-54/+1107
|\ | | | | | | | | | | | | | | | | | | - New timer API to allow delays with a 32-bit microsecond timer - Add dynamic ACPI structs (DSDT/SSDT) generations to the DM core - x86: Enable ACPI table generation by default - x86: Enable the copy framebuffer on Coral - x86: A few fixes to FSP2 with ApolloLake - x86: Drop setup_pcat_compatibility() - x86: Primary-to-Sideband Bus minor fixes
| * acpi: Enable ACPI table generation by default on x86Simon Glass2020-07-171-1/+1
| | | | | | | | | | | | | | | | This should ideally be used by all x86 boards in U-Boot. Enable it by default. If some boards don't use it, the cost is small. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: apl: Fix save/restore of ITSS prioritiesSimon Glass2020-07-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The FSP-S changes the ITSS priorities. The code that tries to save it before running FSP-S and restore it afterwards does not work as U-Boot relocates in between the save and restore. This means that the driver data saved before relocation is lost and the new driver just sees zeroes. Fix this by allocating space in the relocated memory for the ITSS data. Save it there and access it from the driver after relocation. This fixes interrupt handling on coral. Also drop the log_msg_ret() in irq_first_device_type() since this function can be called speculatively in places where we are not sure if there is an interrupt controller of that type. The resulting log errors are confusing when there is no error. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
| * pmc: Move common registers to the header fileSimon Glass2020-07-171-9/+0
| | | | | | | | | | | | | | | | | | These registers need to be accesses from ACPI code, so move them to the header file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * p2sb: Add a method to hide the busSimon Glass2020-07-171-0/+10
| | | | | | | | | | | | | | | | | | | | The P2SB bus needs to be hidden in some cases so that it does not get auto-configured by Linux. Add a method for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
| * i2c: designware_i2c: Support ACPI table generationSimon Glass2020-07-173-1/+136
| | | | | | | | | | | | | | | | | | | | | | Update the PCI driver to generate ACPI information so that Linux has the full information about each I2C bus. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> [bmeng: Correct one typo in dw_i2c_gen_speed_config() comments] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * i2c: Add log_ret() on errorSimon Glass2020-07-171-2/+2
| | | | | | | | | | | | | | | | | | | | Add a few of these calls to make it easier to see where an error occurs, if CONFIG_LOG_ERROR_RETURN is enabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * i2c: designware_i2c: Add a little more debuggingSimon Glass2020-07-171-5/+5
| | | | | | | | | | | | | | | | | | | | Add debugging for a few more values and also use log to show return values when something goes wrong. This makes it easier to see the root cause. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * x86: gpio: Add support for obtaining ACPI info for a GPIOSimon Glass2020-07-171-0/+34
| | | | | | | | | | | | | | | | Implement the method that converts a GPIO into the form used by ACPI, so that GPIOs can be added to ACPI tables. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: pinctrl: Drop the acpi_path memberSimon Glass2020-07-171-4/+0
| | | | | | | | | | | | | | | | This is in the device tree now, so drop the unnecessary field here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: pinctrl: Set up itss in the probe() methodSimon Glass2020-07-171-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | At present the itss is probed in the ofdata_to_platdata() method. This is incorrect since itss is a child of p2sb which itself needs to probe the pinctrl device. This means that p2sb is effectively not probed when the itss is probed, so we get the wrong register address from p2sb. Fix this by moving the itss probe to the correct place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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