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* power: regulator: tps62360_regulator: Convert ofdata_to_platdata to the ↵Keerthy2020-01-201-2/+2
| | | | | | | | | | | | | | | | | | | | missing probe commit 29f7d05a347a ("dm: core: Move ofdata_to_platdata() call earlier") introduces changes in the order of device_probe execution. ofdata_to_platdata now comes before the probe function which resulted in a deadlock and caused boot hang on AM6 devices. Deadlock sequence: tps62360_regulator_ofdata_to_platdata --> i2c_get_chip --> device_probe(tps62360) --> tps62360_regulator_ofdata_to_platdata Hence convert ofdata_to_platdata to the missing probe function to fix the hang. Fixes: 22e8f18980d6 ("power: regulator: tps6236x: add support for tps6236x regulators") Signed-off-by: Keerthy <j-keerthy@ti.com> Tested-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* mmc: am654_sdhci: Add Support for configuring PHY in J721eFaiz Abbas2020-01-201-29/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Support for writing to PHY registers for J721e. There are number of differences between the J721e 8 bit PHY, J721e 4 bit PHY and AM654 PHY. Create a driver_data structure with an ops and flags field and use the flags field to indicate these differences. The differences are as follows: 1. The J721e 4 bit instance PHY does not have a DLL. Introduce a DLL_PRESENT flag to make sure that DLL related registers are accessed only where they are present. Also add a separate set_ios_post() callback. 2. The J721e 8 bit instance is not muxed with anything else inside the SoC and hence the IOMUX_ENABLE filed does not exist. Add a flag which is used to indicate the presence of this field. 3. The register field used to select DLL frequency is 3 bit wide in J721e as compared to 2 bits in AM65x. Add another flag that distinguishes these fields. 4. The strobe select field is 8 bit wide as compared to 4 bit wide for AM65x. Add yet another flag to indicate this difference. Strobe select is used only for HS400 speed mode, support for which has not been added in AM65x. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* mmc: am654_sdhci: Get Xin clock by nameFaiz Abbas2020-01-201-1/+1
| | | | | | | | Get clk_xin by name instead of by index to avoid having to put clocks in the same order in all devices. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* dma: ti: k3-udma: Fix build warnings when building for 32 bit platformsVignesh Raghavendra2020-01-201-8/+8
| | | | | | | | | Cast pointers properly so as to avoid warnings when driver is built for 32 bit platforms Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* dma: ti: k3-udma: Fix ring push operation for 32 bit coresVignesh Raghavendra2020-01-201-3/+11
| | | | | | | | | | | UDMA always expects 64 bit address pointer of the transfer descriptor in the Ring. But on 32 bit cores like R5, pointer is always 32 bit in size. Therefore copy over 32 bit pointer value to 64 bit variable before pushing it over to the ring, so that upper 32 bits are 0s. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* dma: ti: k3-udma: Switch to exposed ring modeVignesh Raghavendra2020-01-201-2/+2
| | | | | | | | | Exposed ring mode works well with 32 bit and 64 bit cores without need for Proxies for 32 bit cores. Therefore switch to exposed ring mode. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* dma: ti: k3-udma: Fix debug prints during enabling MEM_TO_DEV transfersVignesh Raghavendra2020-01-201-2/+2
| | | | | | | | | Fix up the debug prints that were dumping state of TCHAN RT registers to use tchan for MEM_TO_DEV transfers. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* dma: ti: k3-udma: Remove coherency check for cache opsVignesh Raghavendra2020-01-201-33/+16
| | | | | | | | | | Remove redundant coherency checks before calling cache ops in UDMA driver. This is now handled in arch specific cache operation implementation based on Kconfig option Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* soc: ti: k3-navss-ringacc: Get SYSFW reference from DT phandleVignesh Raghavendra2020-01-201-1/+2
| | | | | | | | | | Instead of looking getting reference to SYSFW device using name which is not guaranteed to be constant, use phandle supplied in the DT node to get reference to SYSFW Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* soc: ti: k3-navss-ringacc: Flush/invalidate caches on ring push/popVignesh Raghavendra2020-01-201-0/+11
| | | | | | | | | | | Flush caches when pushing an element to ring and invalidate caches when popping an element from ring in Exposed Ring mode. Otherwise DMA transfers don't work properly in R5 SPL (with caches enabled) where the core is not in coherency domain. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* dma: ti: k3-udma: Query DMA channels allocated from Resource ManagerVignesh Raghavendra2020-01-201-79/+214
| | | | | | | | | | | On K3 SoCs, DMA channels are shared across multiple entities, therefore U-Boot DMA driver needs to query resource range from centralised resource management controller i.e SystemFirmware and use DMA channels allocated for A72 host. Add support for the same. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* thermal: ti-bandgap: Fix adc value datatypeFaiz Abbas2020-01-201-3/+3
| | | | | | | | | The CORE_TEMP_SENSOR_MPU register gives a raw adc value which needs to be indexed into a lookup table to get the actual temperature. Fix the naming and datatype of the adc value variable. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* Merge tag 'mmc-1-16-2020' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmcWIP/16Jan2020Tom Rini2020-01-164-70/+39
|\ | | | | | | | | - Cleanup of fsl_esdhc driver together with arch/defconfig change - Add quirk for APP_CMD retry
| * mmc: config help typo fixJoel Johnson2020-01-161-1/+1
| | | | | | | | | | | | Fix typo in description of MMC_QUIRKS config option. Signed-off-by: Joel Johnson <mrjoel@lixil.net>
| * mmc: add additional quirk for APP_CMD retryJoel Johnson2020-01-161-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | It was observed (on ClearFog Base) that sending MMC APP_CMD returned an error on the first attempt. The issue appears to be timing related since even inserting a puts() short debug entry before the execution added sufficient delay to receive success on first attempt. Follow the existing quirks pattern to retry if initial issuance failed so as to not introduce any delay unless needed. Signed-off-by: Joel Johnson <mrjoel@lixil.net>
| * Drop CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK usageYangbo Lu2020-01-162-19/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The eSDHC reference clocks should be provided by speed.c in arch/. And we do not need CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK option to select which clock to use. Because we can make the driver to select the periperhal clock which is better (provides higher frequency) automatically if its value is provided by speed.c. This patch is to drop this option and make driver to select clock automatically. Also fix peripheral clock calculation issue in fsl_lsch2_speed.c/fsl_lsch3_speed.c. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * mmc: fsl_esdhc: drop useless fdt fixupYangbo Lu2020-01-161-9/+0
| | | | | | | | | | | | | | | | The fdt fixup for properties "peripheral-frequency" and "adapter-type" was once for a Freescale SDK release. The properties haven't been existed in linux mainline. Drop these useless code. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * mmc: fsl_esdhc_imx: drop QorIQ eSDHC specific peripheral clock codeYangbo Lu2020-01-161-40/+0
| | | | | | | | | | | | Drop QorIQ eSDHC specific peripheral clock code. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
* | Merge tag 'xilinx-for-v2020.04' of ↵Tom Rini2020-01-166-220/+314
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx/FPGA changes for v2020.04 ARM64: - Add INIT_SPL_RELATIVE dependency SPL: - FIT image fix - Enable customization of bl2_plat_get_bl31_params() Pytest: - Add test for octal/hex conversions Microblaze: - Fix manual relocation for one SPI instance Nand: - Convert zynq/zynqmp drivers to DM Xilinx: - Enable boot script location via Kconfig - Support OF_SEPARATE in board FDT selection - Remove low level uart setup it is done later by code - Add support for DEVICE_TREE variable passing for SPL Zynq: - Enable jtag boot mode via distro boot - Removing unused baseaddresses from hardware.h - DT fixups ZynqMP: - Fix emmc boot sequence - Simplify spl logic around bss and board_init_r() - Support psu_post_config_data() calling - Tune mini-nand DTS - Fix psu wiring for a2197 boards - Add runtime MMC device boot order filling in spl - Clear ATF handoff handling with custom bl2_plat_get_bl31_params() - Add support u-boot.its generation - Use single image configuration for all platforms - Enable PANIC_HANG via Kconfig - DT fixups - Firmware fixes - Add support for zcu208 and zcu1285 Versal: - Fix emmc boot sequence - Enable board_late_init() by default
| * | net: zynq: Add a note about RX_BUF macroMichal Simek2020-01-141-0/+1
| | | | | | | | | | | | | | | | | | Record note about reducing number of BDs. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | firmware: Remove probe which is causing extra bindAshok Reddy Soma2020-01-141-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove probe function dm_scan_fdt_dev from zynqmp-firmware driver. It is just binding its subnode zynqmp-clk. As a result one extra node is showing up in dm tree. This is not required, it is anyway bound from it's own zynqmp-clk driver. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | zynq: mtd: nand: Remove hardcoded base addressesAshok Reddy Soma2020-01-141-37/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove hardcoded base addresses of smc controller and nand controller. Get those addresses from dt and replace wherever they are used. Remove smc and nand base address from header file too. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | zynq: mtd: nand: Move zynq nand driver to driver modelAshok Reddy Soma2020-01-142-11/+34
| | | | | | | | | | | | | | | | | | | | | | | | Move the zynq nand driver to driver model. Select DM_MTD if zynq nand controller (NAND_ZYNQ) is selected. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | spi: Fix manual relocation calling more timesAshok Reddy Soma2020-01-141-15/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When two instances of AXI QSPI with flash are added and tested simultaneously the spi driver operations are relocated twice. As a result code is accessing addresses outside of RAM when relocated second time which is causing a crash. Tested on Microblaze. Similar change was done in past by: commit f238b3f0fbc9 ("watchdog: dm: Support manual relocation for watchdogs") commit 2588f2ddfd60 ("dm: sf: Add support for all targets which requires MANUAL_RELOC") commit 1b4c2aa25bdf ("gpio: dm: Support manual relocation for gpio") Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | mtd: nand: Remove hardcoded base address of nandAshok Reddy Soma2020-01-141-148/+174
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove hardcoded base address of nand and replace it with the value taken from device tree. Remove base address from header file too. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | mtd: nand: Move arasan nand driver to driver modelAshok Reddy Soma2020-01-142-16/+37
| | | | | | | | | | | | | | | | | | | | | | | | Make changes to arasan nand driver to move it to driver model. Select DM_MTD if arasan nand driver is selected. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | mmc: add mmc and sd support for MT7622Sam Shih2020-01-161-0/+10
| | | | | | | | | | | | | | | | | | | | | This patch add mmc and sd support for Mediatek MT7622 SoCs Signed-off-by: Sam Shih <sam.shih@mediatek.com> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
* | | power: domain: add power domain support for MT7622Sam Shih2020-01-161-0/+6
| | | | | | | | | | | | | | | | | | | | | This patch add power domain support for Mediatek MT7622 SoCs Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Sam Shih <sam.shih@mediatek.com>
* | | clk: mediatek: fix clock-rate overflow problemSam Shih2020-01-161-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | This patch fix clock-rate overflow problem in mediatek clock driver common part. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
* | | clk: mediatek: add driver for MT7622Sam Shih2020-01-162-0/+679
| | | | | | | | | | | | | | | | | | | | | This patch add clock driver for MediaTek MT7622 SoC. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Sam Shih <sam.shih@mediatek.com>
* | | pinctrl: mediatek: add support for different pinctrlSam Shih2020-01-167-19/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | Due to the pinctrl hardware of MT7622 is difference from others SoC which using the common part of mediatek pinctrl. So we need to modify the common part of mediatek pinctrl. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
* | | pinctrl: mediatek: add driver for MT7622Sam Shih2020-01-163-0/+757
| | | | | | | | | | | | | | | | | | | | | This patch add Pinctrl driver for MediaTek MT7622 SoC. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
* | | phy: phy-mtk-tphy: make ref clock optionalChunfeng Yun2020-01-161-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | If make the ref clock optional, no need refer to fixed-clock when the ref clock is always on or comes from oscillator directly. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
* | | phy: phy-mtk-tphy: remove the check of -ENOSYSChunfeng Yun2020-01-161-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | No need check -ENOSYS anymore after add dummy_enable() for fixed-clock. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
* | | clk: fixed_rate: add dummy enable() functionChunfeng Yun2020-01-161-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | This is used to avoid clk_enable() return -ENOSYS. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
* | | clk: add APIs to get (optional) clock by name without a deviceChunfeng Yun2020-01-161-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes we may need get (optional) clock without a device, that means use ofnode. e.g. when the phy node has subnode, and there is no device created for subnode, in this case, we need these new APIs to get subnode's clock. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
* | | clk: check valid clock by clk_valid()Chunfeng Yun2020-01-161-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add valid check for clk->dev, it's useful when get optional clock even when the clk point is valid, but its dev will be NULL. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
* | | clk: fix error check for devm_clk_get_optional()Chunfeng Yun2020-01-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | If skip all return error number, it may skip some real error cases, so only skip the error when the clock is not provided in DTS Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
* | | clk: mediatek: mt7629: add support for ssusbsysChunfeng Yun2020-01-161-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | The SSUSB IP's clocks come from ssusbsys module on mt7629, so add its driver Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
* | | mmc: mtk-sd: fix hang when data read quicklymingming lee2020-01-161-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For CMD21 tuning data, the 128/64 bytes data may coming in very short time, before msdc_start_data(), the read data has already come, in this case, clear MSDC_INT will cause the interrupt disappear and lead to the thread hang. the solution is just clear all interrupts before command was sent. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
* | | mmc: mtk-sd: add support for MediaTek MT8512/MT8110 SoCsmingming lee2020-01-161-33/+101
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds mmc support for MediaTek MT8512/MT8110 SoCs. MT8512/MT8110 SoCs puts the tune register at top layer, so need add new code to support it. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
* | | pinctrl: mediatek: add driver for MT8512mingming lee2020-01-163-0/+392
| | | | | | | | | | | | | | | | | | Add Pinctrl driver for MediaTek MT8512 SoC. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
* | | clk: mediatek: add configurable pcw_chg_reg/ibits/fmin to mtk_pllmingming lee2020-01-162-8/+20
| | | | | | | | | | | | Add configurable pcw_chg_reg/ibits/fmin to mtk_pll to support mt8512
* | | clk: mediatek: add set_clr_upd mux type flowmingming lee2020-01-162-11/+55
| | | | | | | | | | | | | | | Add new set_clr_upd mux type and related operation to mtk common clock driver to support mt8512
* | | clk: mediatek: add driver support for MT8512mingming lee2020-01-162-0/+874
| | | | | | | | | | | | | | | | | | | | | Add clock driver for MediaTek MT8512 SoC, include topckgen, apmixedsys and infracfg support. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
* | | Add dependencies for MALLOC_F and OF_LIBFDTSean Anderson2020-01-151-0/+3
| | | | | | | | | | | | | | | | | | | | | Some features implicitly depended on MALLOC_F and OF_LIBFDT and would fail at link-time if these features were not enabled. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* | | Kconfig: Rename CONFIG_SPL_DMA_SUPPORT to CONFIG_SPL_DMAVignesh Raghavendra2020-01-151-1/+1
| |/ |/| | | | | | | | | | | | | | | Rename CONFIG_SPL_DMA_SUPPORT to CONFIG_SPL_DMA. This allows to use macros such as CONFIG_IS_ENABLED() that allow conditional compilation of code for SPL and U-Boot. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | mmc: fsl_esdhc: add compatible for fsl, imxrt-usdhcGiulio Benetti2020-01-142-2/+3
| | | | | | | | | | | | | | Add compatible "fsl,imxrt-usdhc" to make mmc working on i.MXRT platforms with CONFIG_DM_MMC=y. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
* | mmc: fsl_esdhc: make if(CONFIG_IS_ENABLED(CLK)) an #if statementGiulio Benetti2020-01-141-19/+19
| | | | | | | | | | | | | | | | | | | | Not all architectures(i.e. i.MXRT) support mxc_get_clock() and use DM_CLK instead. So building could result in failure due to missing mxc_get_clock(). Make if(CONFIG_IS_ENABLED(CLK)) an #if statement. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
* | ram: add SDRAM driver for i.MXRT SoCsGiulio Benetti2020-01-143-0/+449
| | | | | | | | | | | | Add SDRAM driver for i.MXRT SoCs. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
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