From 15ca9ebb074e9eca5a8264c93f5678df240fa54d Mon Sep 17 00:00:00 2001 From: Manish Narani Date: Wed, 14 Jul 2021 06:17:19 -0600 Subject: arm64: zynqmp: Move USB3 PHY properties from DWC3 node to USB node Move the PHY properties from DWC3 node to USB node in ZynqMP DTs as here the USB3 PHY used is PSGTR, which is connected to Xilinx USB core. This PHY initialization should be handled from Xilinx USB core as the prerequisite register configurations are done here only. Signed-off-by: Manish Narani Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zcu100-revC.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm/dts/zynqmp-zcu100-revC.dts') diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index 2d61577478..ea630a43dc 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -561,13 +561,13 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 0>; }; &dwc3_0 { status = "okay"; dr_mode = "peripheral"; - phy-names = "usb3-phy"; - phys = <&psgtr 2 PHY_TYPE_USB3 0 0>; maximum-speed = "super-speed"; }; @@ -576,13 +576,13 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 3 PHY_TYPE_USB3 1 0>; }; &dwc3_1 { status = "okay"; dr_mode = "host"; - phy-names = "usb3-phy"; - phys = <&psgtr 3 PHY_TYPE_USB3 1 0>; maximum-speed = "super-speed"; }; -- cgit v1.2.1