From 696f81f9a97d352651e2ffe970dc1d643d70dd19 Mon Sep 17 00:00:00 2001 From: Taras Kondratiuk Date: Tue, 6 Aug 2013 15:18:48 +0300 Subject: ARM: OMAP4470: Add OMAP4470 identification Signed-off-by: Taras Kondratiuk --- arch/arm/include/asm/arch-omap4/omap.h | 1 + arch/arm/include/asm/omap_common.h | 1 + 2 files changed, 2 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index 3823a37f2f..9129c0dd7c 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -41,6 +41,7 @@ #define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F #define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F #define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F +#define OMAP4470_CONTROL_ID_CODE_ES1_0 0x0B97502F /* UART */ #define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000) diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 66f416f99c..5e2f027ba4 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -622,6 +622,7 @@ static inline u8 is_omap54xx(void) #define OMAP4430_ES2_3 0x44300230 #define OMAP4460_ES1_0 0x44600100 #define OMAP4460_ES1_1 0x44600110 +#define OMAP4470_ES1_0 0x44700100 /* omap5 */ #define OMAP5430_SILICON_ID_INVALID 0 -- cgit v1.2.1 From 40aadf9201b6f9ee840ce09c06c3eebd26c67386 Mon Sep 17 00:00:00 2001 From: Taras Kondratiuk Date: Tue, 6 Aug 2013 15:18:49 +0300 Subject: ARM: OMAP4470: Add voltage and dpll data OMAP4470 reference design uses TWL6032 PMIC with a following connection scheme: VDD_CORE = TWL6032 SMPS2 VDD_MPU = TWL6032 SMPS1 VDD_IVA = TWL6032 SMPS5 Set voltage and frequency values according to OMAP4470 Data Manual Operating Condition Addendum v0.7 Signed-off-by: Taras Kondratiuk --- arch/arm/include/asm/arch-omap4/clock.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-omap4/clock.h b/arch/arm/include/asm/arch-omap4/clock.h index b2e03d6e1e..f3a682a197 100644 --- a/arch/arm/include/asm/arch-omap4/clock.h +++ b/arch/arm/include/asm/arch-omap4/clock.h @@ -149,11 +149,16 @@ /* PRM_VC_VAL_BYPASS */ #define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 -/* SMPS */ +/* PMIC */ #define SMPS_I2C_SLAVE_ADDR 0x12 +/* TWL6030 SMPS */ #define SMPS_REG_ADDR_VCORE1 0x55 #define SMPS_REG_ADDR_VCORE2 0x5B #define SMPS_REG_ADDR_VCORE3 0x61 +/* TWL6032 SMPS */ +#define SMPS_REG_ADDR_SMPS1 0x55 +#define SMPS_REG_ADDR_SMPS2 0x5B +#define SMPS_REG_ADDR_SMPS5 0x49 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000 -- cgit v1.2.1 From 8d20836615eb7fa6330935a5f63e5cdd05cac7e5 Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Sat, 10 Aug 2013 19:03:59 +0200 Subject: arm: omap3: fix SRAM copy and execution sequence Fix size calculation in copy of go_to_speed into SRAM. Use SRAM_CLK_CODE in call to SRAM-based go_to_speed. Signed-off-by: Albert ARIBAUD --- arch/arm/include/asm/arch-omap3/clock.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-omap3/clock.h b/arch/arm/include/asm/arch-omap3/clock.h index 514839c778..be669c156f 100644 --- a/arch/arm/include/asm/arch-omap3/clock.h +++ b/arch/arm/include/asm/arch-omap3/clock.h @@ -63,6 +63,4 @@ extern dpll_param *get_36x_core_dpll_param(void); extern dpll_param *get_36x_per_dpll_param(void); extern dpll_param *get_36x_per2_dpll_param(void); -extern void *_end_vect, *_start; - #endif -- cgit v1.2.1 From c27efde68dfd7fd2da364d556d586495e78d3396 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 20 Aug 2013 08:53:43 -0400 Subject: am33xx: Correct and expand comments on CONFIG_SPL_MAX_SIZE We had been allowing the max size to be larger than actually allowed by the ROM. Expand the commentary here to explain why we set these locations. Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-am33xx/omap.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index 1f8431196f..225072186d 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -18,7 +18,7 @@ #ifdef CONFIG_AM33XX #define NON_SECURE_SRAM_START 0x402F0400 #define NON_SECURE_SRAM_END 0x40310000 -#define SRAM_SCRATCH_SPACE_ADDR 0x4030C000 +#define SRAM_SCRATCH_SPACE_ADDR 0x4030B800 #elif defined(CONFIG_TI81XX) #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40320000 -- cgit v1.2.1 From c3799fceda6c37ad04bd62b6dd0db6225c11626b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 20 Aug 2013 08:53:45 -0400 Subject: omap5: Expand CONFIG_SPL_MAX_SIZE and comment upon SRAM_SCRATCH_SPACE_ADDR After examining both TRMs and doing some experimentation, we can rely on using the start of the download area for CONFIG_SPL_TEXT_BASE and then move SRAM_SCRATCH_SPACE_ADDR up, just like am335x. This is required for peripheral boot modes such as UART. Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-omap5/omap.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 597c692b97..e9a51d3403 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -153,6 +153,15 @@ struct s32ktimer { #define EFUSE_4 0x45145100 #endif /* __ASSEMBLY__ */ +/* + * In all cases, the TRM defines the RAM Memory Map for the processor + * and indicates the area for the downloaded image. We use all of that + * space for download and once up and running may use other parts of the + * map for our needs. We set a scratch space that is at the end of the + * OMAP5 download area, but within the DRA7xx download area (as it is + * much larger) and do not, at this time, make use of the additional + * space. + */ #ifdef CONFIG_DRA7XX #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */ @@ -160,7 +169,7 @@ struct s32ktimer { #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ #endif -#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START +#define SRAM_SCRATCH_SPACE_ADDR 0x4031E000 /* base address for indirect vectors (internal boot mode) */ #define SRAM_ROM_VECT_BASE 0x4031F000 -- cgit v1.2.1 From dafd4db33a99f05616f02283f6fd3ba065278dcb Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 19 Aug 2013 16:38:56 +0200 Subject: arm, am33xx: add defines for gmii_sel_register bits Signed-off-by: Heiko Schocher Acked-by: Mugunthan V N --- arch/arm/include/asm/arch-am33xx/cpu.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 10b56e0db4..f77ac1e844 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -486,6 +486,25 @@ struct ctrl_dev { unsigned int resv4[4]; unsigned int miisel; /* offset 0x50 */ }; + +/* gmii_sel register defines */ +#define GMII1_SEL_MII 0x0 +#define GMII1_SEL_RMII 0x1 +#define GMII1_SEL_RGMII 0x2 +#define GMII2_SEL_MII 0x0 +#define GMII2_SEL_RMII 0x4 +#define GMII2_SEL_RGMII 0x8 +#define RGMII1_IDMODE BIT(4) +#define RGMII2_IDMODE BIT(5) +#define RMII1_IO_CLK_EN BIT(6) +#define RMII2_IO_CLK_EN BIT(7) + +#define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII) +#define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII) +#define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII) +#define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE) +#define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN) + #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */ -- cgit v1.2.1 From 14c0158b180c78b2e5482ae5c419862cfcf3226d Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 19 Aug 2013 16:38:57 +0200 Subject: arm, am335x: add some missing registers and defines for lcd and epwm support - add missing register defines in struct cm_perpl epwmss0clkctrl epwmss2clkctrl lcdcclkstctrl - add missing register defines in struct cm_dpll clklcdcpixelclk - add struct pwmss_regs - add struct pwmss_ecap_regs - add LCD Controller base LCD_CNTL_BASE - add PWM0 controller base PWMSS0_BASE Signed-off-by: Heiko Schocher Cc: Tom Rini --- arch/arm/include/asm/arch-am33xx/cpu.h | 35 +++++++++++++++++++++- arch/arm/include/asm/arch-am33xx/hardware_am33xx.h | 7 +++++ 2 files changed, 41 insertions(+), 1 deletion(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index f77ac1e844..1835c8939b 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -193,7 +193,8 @@ struct cm_perpll { unsigned int dcan1clkctrl; /* offset 0xC4 */ unsigned int resv6[2]; unsigned int emiffwclkctrl; /* offset 0xD0 */ - unsigned int resv7[2]; + unsigned int epwmss0clkctrl; /* offset 0xD4 */ + unsigned int epwmss2clkctrl; /* offset 0xD8 */ unsigned int l3instrclkctrl; /* offset 0xDC */ unsigned int l3clkctrl; /* Offset 0xE0 */ unsigned int resv8[4]; @@ -204,6 +205,7 @@ struct cm_perpll { unsigned int l4hsclkctrl; /* offset 0x120 */ unsigned int resv10[8]; unsigned int cpswclkstctrl; /* offset 0x144 */ + unsigned int lcdcclkstctrl; /* offset 0x148 */ }; #else /* Encapsulating core pll registers */ @@ -366,6 +368,8 @@ struct cm_perpll { struct cm_dpll { unsigned int resv1[2]; unsigned int clktimer2clk; /* offset 0x08 */ + unsigned int resv2[10]; + unsigned int clklcdcpixelclk; /* offset 0x34 */ }; /* Control Module RTC registers */ @@ -505,6 +509,35 @@ struct ctrl_dev { #define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE) #define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN) +/* PWMSS */ +struct pwmss_regs { + unsigned int idver; + unsigned int sysconfig; + unsigned int clkconfig; + unsigned int clkstatus; +}; +#define ECAP_CLK_EN BIT(0) +#define ECAP_CLK_STOP_REQ BIT(1) + +struct pwmss_ecap_regs { + unsigned int tsctr; + unsigned int ctrphs; + unsigned int cap1; + unsigned int cap2; + unsigned int cap3; + unsigned int cap4; + unsigned int resv1[4]; + unsigned short ecctl1; + unsigned short ecctl2; +}; + +/* Capture Control register 2 */ +#define ECTRL2_SYNCOSEL_MASK (0x03 << 6) +#define ECTRL2_MDSL_ECAP BIT(9) +#define ECTRL2_CTRSTP_FREERUN BIT(4) +#define ECTRL2_PLSL_LOW BIT(10) +#define ECTRL2_SYNC_EN BIT(5) + #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h index 8973fd884f..e4231c81ad 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h @@ -58,4 +58,11 @@ #define USB0_OTG_BASE 0x47401000 #define USB1_OTG_BASE 0x47401800 +/* LCD Controller */ +#define LCD_CNTL_BASE 0x4830E000 + +/* PWMSS */ +#define PWMSS0_BASE 0x48300000 +#define AM33XX_ECAP0_BASE 0x48300100 + #endif /* __AM33XX_HARDWARE_AM33XX_H */ -- cgit v1.2.1 From 988ea355018a7060768b8e6ddcee1ffa7cf6351b Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 19 Aug 2013 16:38:59 +0200 Subject: arm, am335x: add watchdog support Add TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog support. Signed-off-by: Heiko Schocher Reviewed-by: Tom Rini Cc: Albert Aribaud --- arch/arm/include/asm/arch-am33xx/cpu.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 1835c8939b..73e6db8998 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -46,6 +46,26 @@ #define PRM_RSTCTRL_RESET 0x01 #define PRM_RSTST_WARM_RESET_MASK 0x232 +/* + * Watchdog: + * Using the prescaler, the OMAP watchdog could go for many + * months before firing. These limits work without scaling, + * with the 60 second default assumed by most tools and docs. + */ +#define TIMER_MARGIN_MAX (24 * 60 * 60) /* 1 day */ +#define TIMER_MARGIN_DEFAULT 60 /* 60 secs */ +#define TIMER_MARGIN_MIN 1 + +#define PTV 0 /* prescale */ +#define GET_WLDR_VAL(secs) (0xffffffff - ((secs) * (32768/(1<