From 0b8f6378cbf20e56f49a52a584c1374f11020cbf Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 18 Aug 2018 19:11:52 +0200 Subject: ARM: socfpga: Reorder Arria10 SPL The Arria10 SPL is a complete mess of calls to functions which are called in the wrong context and it is surprise it works at all. This patch tries to clean that mess up by shuffling the function calls around and moving the calls into the correct context. Due to the delicate nature of the reordering, this is done in one huge patch. The following changes happen in this patch: - Security policy init and NIC301 happens first in board_init_f() - The clock init happens very early in board_init_f() in SPL only - arch_early_init_r() only registers the FPGA, just like on Gen5 - arch_early_init_r() is never called from any _f() function - Dedicated FPGA pins are inited in board_init_f() as on Gen5 Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Ley Foon Tan --- arch/arm/mach-socfpga/spl_a10.c | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) (limited to 'arch/arm/mach-socfpga/spl_a10.c') diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index 7d35e9daa8..3ea64f7e94 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -68,33 +68,26 @@ u32 spl_boot_mode(const u32 boot_device) void spl_board_init(void) { - /* configuring the clock based on handoff */ - cm_basic_init(gd->fdt_blob); - WATCHDOG_RESET(); - - config_dedicated_pins(gd->fdt_blob); - WATCHDOG_RESET(); - /* enable console uart printing */ preloader_console_init(); - WATCHDOG_RESET(); - /* Add device descriptor to FPGA device table */ - socfpga_fpga_add(); + arch_early_init_r(); } void board_init_f(ulong dummy) { - /* - * Configure Clock Manager to use intosc clock instead external osc to - * ensure success watchdog operation. We do it as early as possible. - */ - cm_use_intosc(); + socfpga_init_security_policies(); + socfpga_sdram_remap_zero(); + /* Assert reset to all except L4WD0 and L4TIMER0 */ + socfpga_per_reset_all(); socfpga_watchdog_disable(); - arch_early_init_r(); + spl_early_init(); + + /* Configure the clock based on handoff */ + cm_basic_init(gd->fdt_blob); #ifdef CONFIG_HW_WATCHDOG /* release osc1 watchdog timer 0 from reset */ @@ -104,4 +97,7 @@ void board_init_f(ulong dummy) hw_watchdog_init(); WATCHDOG_RESET(); #endif /* CONFIG_HW_WATCHDOG */ + + config_dedicated_pins(gd->fdt_blob); + WATCHDOG_RESET(); } -- cgit v1.2.1